stabilization.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000000bc 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 00009d20 080000bc 080000bc 000010bc 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000200 08009de0 08009de0 0000ade0 2**3 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 08009fe0 08009fe0 0000b070 2**0 CONTENTS 4 .ARM 00000000 08009fe0 08009fe0 0000b070 2**0 CONTENTS 5 .preinit_array 00000000 08009fe0 08009fe0 0000b070 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 08009fe0 08009fe0 0000afe0 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .fini_array 00000004 08009fe4 08009fe4 0000afe4 2**2 CONTENTS, ALLOC, LOAD, DATA 8 .data 00000070 20000000 08009fe8 0000b000 2**3 CONTENTS, ALLOC, LOAD, DATA 9 .bss 00000acc 20000070 0800a058 0000b070 2**2 ALLOC 10 ._user_heap_stack 00000604 20000b3c 0800a058 0000bb3c 2**0 ALLOC 11 .ARM.attributes 00000028 00000000 00000000 0000b070 2**0 CONTENTS, READONLY 12 .debug_info 0000f323 00000000 00000000 0000b098 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 00002702 00000000 00000000 0001a3bb 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_aranges 00000f50 00000000 00000000 0001cac0 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_rnglists 00000bf0 00000000 00000000 0001da10 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 00017011 00000000 00000000 0001e600 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_line 00012ce7 00000000 00000000 00035611 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_str 0009120c 00000000 00000000 000482f8 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .comment 00000043 00000000 00000000 000d9504 2**0 CONTENTS, READONLY 20 .debug_frame 00003ff4 00000000 00000000 000d9548 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 21 .debug_line_str 00000058 00000000 00000000 000dd53c 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080000bc <__do_global_dtors_aux>: 80000bc: b510 push {r4, lr} 80000be: 4c06 ldr r4, [pc, #24] @ (80000d8 <__do_global_dtors_aux+0x1c>) 80000c0: 7823 ldrb r3, [r4, #0] 80000c2: 2b00 cmp r3, #0 80000c4: d107 bne.n 80000d6 <__do_global_dtors_aux+0x1a> 80000c6: 4b05 ldr r3, [pc, #20] @ (80000dc <__do_global_dtors_aux+0x20>) 80000c8: 2b00 cmp r3, #0 80000ca: d002 beq.n 80000d2 <__do_global_dtors_aux+0x16> 80000cc: 4804 ldr r0, [pc, #16] @ (80000e0 <__do_global_dtors_aux+0x24>) 80000ce: e000 b.n 80000d2 <__do_global_dtors_aux+0x16> 80000d0: bf00 nop 80000d2: 2301 movs r3, #1 80000d4: 7023 strb r3, [r4, #0] 80000d6: bd10 pop {r4, pc} 80000d8: 20000070 .word 0x20000070 80000dc: 00000000 .word 0x00000000 80000e0: 08009dc4 .word 0x08009dc4 080000e4 : 80000e4: 4b04 ldr r3, [pc, #16] @ (80000f8 ) 80000e6: b510 push {r4, lr} 80000e8: 2b00 cmp r3, #0 80000ea: d003 beq.n 80000f4 80000ec: 4903 ldr r1, [pc, #12] @ (80000fc ) 80000ee: 4804 ldr r0, [pc, #16] @ (8000100 ) 80000f0: e000 b.n 80000f4 80000f2: bf00 nop 80000f4: bd10 pop {r4, pc} 80000f6: 46c0 nop @ (mov r8, r8) 80000f8: 00000000 .word 0x00000000 80000fc: 20000074 .word 0x20000074 8000100: 08009dc4 .word 0x08009dc4 08000104 <__udivsi3>: 8000104: 2200 movs r2, #0 8000106: 0843 lsrs r3, r0, #1 8000108: 428b cmp r3, r1 800010a: d374 bcc.n 80001f6 <__udivsi3+0xf2> 800010c: 0903 lsrs r3, r0, #4 800010e: 428b cmp r3, r1 8000110: d35f bcc.n 80001d2 <__udivsi3+0xce> 8000112: 0a03 lsrs r3, r0, #8 8000114: 428b cmp r3, r1 8000116: d344 bcc.n 80001a2 <__udivsi3+0x9e> 8000118: 0b03 lsrs r3, r0, #12 800011a: 428b cmp r3, r1 800011c: d328 bcc.n 8000170 <__udivsi3+0x6c> 800011e: 0c03 lsrs r3, r0, #16 8000120: 428b cmp r3, r1 8000122: d30d bcc.n 8000140 <__udivsi3+0x3c> 8000124: 22ff movs r2, #255 @ 0xff 8000126: 0209 lsls r1, r1, #8 8000128: ba12 rev r2, r2 800012a: 0c03 lsrs r3, r0, #16 800012c: 428b cmp r3, r1 800012e: d302 bcc.n 8000136 <__udivsi3+0x32> 8000130: 1212 asrs r2, r2, #8 8000132: 0209 lsls r1, r1, #8 8000134: d065 beq.n 8000202 <__udivsi3+0xfe> 8000136: 0b03 lsrs r3, r0, #12 8000138: 428b cmp r3, r1 800013a: d319 bcc.n 8000170 <__udivsi3+0x6c> 800013c: e000 b.n 8000140 <__udivsi3+0x3c> 800013e: 0a09 lsrs r1, r1, #8 8000140: 0bc3 lsrs r3, r0, #15 8000142: 428b cmp r3, r1 8000144: d301 bcc.n 800014a <__udivsi3+0x46> 8000146: 03cb lsls r3, r1, #15 8000148: 1ac0 subs r0, r0, r3 800014a: 4152 adcs r2, r2 800014c: 0b83 lsrs r3, r0, #14 800014e: 428b cmp r3, r1 8000150: d301 bcc.n 8000156 <__udivsi3+0x52> 8000152: 038b lsls r3, r1, #14 8000154: 1ac0 subs r0, r0, r3 8000156: 4152 adcs r2, r2 8000158: 0b43 lsrs r3, r0, #13 800015a: 428b cmp r3, r1 800015c: d301 bcc.n 8000162 <__udivsi3+0x5e> 800015e: 034b lsls r3, r1, #13 8000160: 1ac0 subs r0, r0, r3 8000162: 4152 adcs r2, r2 8000164: 0b03 lsrs r3, r0, #12 8000166: 428b cmp r3, r1 8000168: d301 bcc.n 800016e <__udivsi3+0x6a> 800016a: 030b lsls r3, r1, #12 800016c: 1ac0 subs r0, r0, r3 800016e: 4152 adcs r2, r2 8000170: 0ac3 lsrs r3, r0, #11 8000172: 428b cmp r3, r1 8000174: d301 bcc.n 800017a <__udivsi3+0x76> 8000176: 02cb lsls r3, r1, #11 8000178: 1ac0 subs r0, r0, r3 800017a: 4152 adcs r2, r2 800017c: 0a83 lsrs r3, r0, #10 800017e: 428b cmp r3, r1 8000180: d301 bcc.n 8000186 <__udivsi3+0x82> 8000182: 028b lsls r3, r1, #10 8000184: 1ac0 subs r0, r0, r3 8000186: 4152 adcs r2, r2 8000188: 0a43 lsrs r3, r0, #9 800018a: 428b cmp r3, r1 800018c: d301 bcc.n 8000192 <__udivsi3+0x8e> 800018e: 024b lsls r3, r1, #9 8000190: 1ac0 subs r0, r0, r3 8000192: 4152 adcs r2, r2 8000194: 0a03 lsrs r3, r0, #8 8000196: 428b cmp r3, r1 8000198: d301 bcc.n 800019e <__udivsi3+0x9a> 800019a: 020b lsls r3, r1, #8 800019c: 1ac0 subs r0, r0, r3 800019e: 4152 adcs r2, r2 80001a0: d2cd bcs.n 800013e <__udivsi3+0x3a> 80001a2: 09c3 lsrs r3, r0, #7 80001a4: 428b cmp r3, r1 80001a6: d301 bcc.n 80001ac <__udivsi3+0xa8> 80001a8: 01cb lsls r3, r1, #7 80001aa: 1ac0 subs r0, r0, r3 80001ac: 4152 adcs r2, r2 80001ae: 0983 lsrs r3, r0, #6 80001b0: 428b cmp r3, r1 80001b2: d301 bcc.n 80001b8 <__udivsi3+0xb4> 80001b4: 018b lsls r3, r1, #6 80001b6: 1ac0 subs r0, r0, r3 80001b8: 4152 adcs r2, r2 80001ba: 0943 lsrs r3, r0, #5 80001bc: 428b cmp r3, r1 80001be: d301 bcc.n 80001c4 <__udivsi3+0xc0> 80001c0: 014b lsls r3, r1, #5 80001c2: 1ac0 subs r0, r0, r3 80001c4: 4152 adcs r2, r2 80001c6: 0903 lsrs r3, r0, #4 80001c8: 428b cmp r3, r1 80001ca: d301 bcc.n 80001d0 <__udivsi3+0xcc> 80001cc: 010b lsls r3, r1, #4 80001ce: 1ac0 subs r0, r0, r3 80001d0: 4152 adcs r2, r2 80001d2: 08c3 lsrs r3, r0, #3 80001d4: 428b cmp r3, r1 80001d6: d301 bcc.n 80001dc <__udivsi3+0xd8> 80001d8: 00cb lsls r3, r1, #3 80001da: 1ac0 subs r0, r0, r3 80001dc: 4152 adcs r2, r2 80001de: 0883 lsrs r3, r0, #2 80001e0: 428b cmp r3, r1 80001e2: d301 bcc.n 80001e8 <__udivsi3+0xe4> 80001e4: 008b lsls r3, r1, #2 80001e6: 1ac0 subs r0, r0, r3 80001e8: 4152 adcs r2, r2 80001ea: 0843 lsrs r3, r0, #1 80001ec: 428b cmp r3, r1 80001ee: d301 bcc.n 80001f4 <__udivsi3+0xf0> 80001f0: 004b lsls r3, r1, #1 80001f2: 1ac0 subs r0, r0, r3 80001f4: 4152 adcs r2, r2 80001f6: 1a41 subs r1, r0, r1 80001f8: d200 bcs.n 80001fc <__udivsi3+0xf8> 80001fa: 4601 mov r1, r0 80001fc: 4152 adcs r2, r2 80001fe: 4610 mov r0, r2 8000200: 4770 bx lr 8000202: e7ff b.n 8000204 <__udivsi3+0x100> 8000204: b501 push {r0, lr} 8000206: 2000 movs r0, #0 8000208: f000 f806 bl 8000218 <__aeabi_idiv0> 800020c: bd02 pop {r1, pc} 800020e: 46c0 nop @ (mov r8, r8) 08000210 <__aeabi_uidivmod>: 8000210: 2900 cmp r1, #0 8000212: d0f7 beq.n 8000204 <__udivsi3+0x100> 8000214: e776 b.n 8000104 <__udivsi3> 8000216: 4770 bx lr 08000218 <__aeabi_idiv0>: 8000218: 4770 bx lr 800021a: 46c0 nop @ (mov r8, r8) 0800021c <__aeabi_cdrcmple>: 800021c: 4684 mov ip, r0 800021e: 0010 movs r0, r2 8000220: 4662 mov r2, ip 8000222: 468c mov ip, r1 8000224: 0019 movs r1, r3 8000226: 4663 mov r3, ip 8000228: e000 b.n 800022c <__aeabi_cdcmpeq> 800022a: 46c0 nop @ (mov r8, r8) 0800022c <__aeabi_cdcmpeq>: 800022c: b51f push {r0, r1, r2, r3, r4, lr} 800022e: f001 fe41 bl 8001eb4 <__ledf2> 8000232: 2800 cmp r0, #0 8000234: d401 bmi.n 800023a <__aeabi_cdcmpeq+0xe> 8000236: 2100 movs r1, #0 8000238: 42c8 cmn r0, r1 800023a: bd1f pop {r0, r1, r2, r3, r4, pc} 0800023c <__aeabi_dcmpeq>: 800023c: b510 push {r4, lr} 800023e: f001 fd81 bl 8001d44 <__eqdf2> 8000242: 4240 negs r0, r0 8000244: 3001 adds r0, #1 8000246: bd10 pop {r4, pc} 08000248 <__aeabi_dcmplt>: 8000248: b510 push {r4, lr} 800024a: f001 fe33 bl 8001eb4 <__ledf2> 800024e: 2800 cmp r0, #0 8000250: db01 blt.n 8000256 <__aeabi_dcmplt+0xe> 8000252: 2000 movs r0, #0 8000254: bd10 pop {r4, pc} 8000256: 2001 movs r0, #1 8000258: bd10 pop {r4, pc} 800025a: 46c0 nop @ (mov r8, r8) 0800025c <__aeabi_dcmple>: 800025c: b510 push {r4, lr} 800025e: f001 fe29 bl 8001eb4 <__ledf2> 8000262: 2800 cmp r0, #0 8000264: dd01 ble.n 800026a <__aeabi_dcmple+0xe> 8000266: 2000 movs r0, #0 8000268: bd10 pop {r4, pc} 800026a: 2001 movs r0, #1 800026c: bd10 pop {r4, pc} 800026e: 46c0 nop @ (mov r8, r8) 08000270 <__aeabi_dcmpgt>: 8000270: b510 push {r4, lr} 8000272: f001 fdab bl 8001dcc <__gedf2> 8000276: 2800 cmp r0, #0 8000278: dc01 bgt.n 800027e <__aeabi_dcmpgt+0xe> 800027a: 2000 movs r0, #0 800027c: bd10 pop {r4, pc} 800027e: 2001 movs r0, #1 8000280: bd10 pop {r4, pc} 8000282: 46c0 nop @ (mov r8, r8) 08000284 <__aeabi_dcmpge>: 8000284: b510 push {r4, lr} 8000286: f001 fda1 bl 8001dcc <__gedf2> 800028a: 2800 cmp r0, #0 800028c: da01 bge.n 8000292 <__aeabi_dcmpge+0xe> 800028e: 2000 movs r0, #0 8000290: bd10 pop {r4, pc} 8000292: 2001 movs r0, #1 8000294: bd10 pop {r4, pc} 8000296: 46c0 nop @ (mov r8, r8) 08000298 <__aeabi_cfrcmple>: 8000298: 4684 mov ip, r0 800029a: 0008 movs r0, r1 800029c: 4661 mov r1, ip 800029e: e7ff b.n 80002a0 <__aeabi_cfcmpeq> 080002a0 <__aeabi_cfcmpeq>: 80002a0: b51f push {r0, r1, r2, r3, r4, lr} 80002a2: f000 fb55 bl 8000950 <__lesf2> 80002a6: 2800 cmp r0, #0 80002a8: d401 bmi.n 80002ae <__aeabi_cfcmpeq+0xe> 80002aa: 2100 movs r1, #0 80002ac: 42c8 cmn r0, r1 80002ae: bd1f pop {r0, r1, r2, r3, r4, pc} 080002b0 <__aeabi_fcmpeq>: 80002b0: b510 push {r4, lr} 80002b2: f000 fad5 bl 8000860 <__eqsf2> 80002b6: 4240 negs r0, r0 80002b8: 3001 adds r0, #1 80002ba: bd10 pop {r4, pc} 080002bc <__aeabi_fcmplt>: 80002bc: b510 push {r4, lr} 80002be: f000 fb47 bl 8000950 <__lesf2> 80002c2: 2800 cmp r0, #0 80002c4: db01 blt.n 80002ca <__aeabi_fcmplt+0xe> 80002c6: 2000 movs r0, #0 80002c8: bd10 pop {r4, pc} 80002ca: 2001 movs r0, #1 80002cc: bd10 pop {r4, pc} 80002ce: 46c0 nop @ (mov r8, r8) 080002d0 <__aeabi_fcmple>: 80002d0: b510 push {r4, lr} 80002d2: f000 fb3d bl 8000950 <__lesf2> 80002d6: 2800 cmp r0, #0 80002d8: dd01 ble.n 80002de <__aeabi_fcmple+0xe> 80002da: 2000 movs r0, #0 80002dc: bd10 pop {r4, pc} 80002de: 2001 movs r0, #1 80002e0: bd10 pop {r4, pc} 80002e2: 46c0 nop @ (mov r8, r8) 080002e4 <__aeabi_fcmpgt>: 80002e4: b510 push {r4, lr} 80002e6: f000 fae3 bl 80008b0 <__gesf2> 80002ea: 2800 cmp r0, #0 80002ec: dc01 bgt.n 80002f2 <__aeabi_fcmpgt+0xe> 80002ee: 2000 movs r0, #0 80002f0: bd10 pop {r4, pc} 80002f2: 2001 movs r0, #1 80002f4: bd10 pop {r4, pc} 80002f6: 46c0 nop @ (mov r8, r8) 080002f8 <__aeabi_fcmpge>: 80002f8: b510 push {r4, lr} 80002fa: f000 fad9 bl 80008b0 <__gesf2> 80002fe: 2800 cmp r0, #0 8000300: da01 bge.n 8000306 <__aeabi_fcmpge+0xe> 8000302: 2000 movs r0, #0 8000304: bd10 pop {r4, pc} 8000306: 2001 movs r0, #1 8000308: bd10 pop {r4, pc} 800030a: 46c0 nop @ (mov r8, r8) 0800030c <__aeabi_fadd>: 800030c: b5f8 push {r3, r4, r5, r6, r7, lr} 800030e: 46ce mov lr, r9 8000310: 4647 mov r7, r8 8000312: 0243 lsls r3, r0, #9 8000314: 0a5a lsrs r2, r3, #9 8000316: 024e lsls r6, r1, #9 8000318: 0045 lsls r5, r0, #1 800031a: 0fc4 lsrs r4, r0, #31 800031c: 0048 lsls r0, r1, #1 800031e: 4691 mov r9, r2 8000320: 0e2d lsrs r5, r5, #24 8000322: 0a72 lsrs r2, r6, #9 8000324: 0e00 lsrs r0, r0, #24 8000326: 4694 mov ip, r2 8000328: b580 push {r7, lr} 800032a: 099b lsrs r3, r3, #6 800032c: 0fc9 lsrs r1, r1, #31 800032e: 09b6 lsrs r6, r6, #6 8000330: 1a2a subs r2, r5, r0 8000332: 428c cmp r4, r1 8000334: d021 beq.n 800037a <__aeabi_fadd+0x6e> 8000336: 2a00 cmp r2, #0 8000338: dd0d ble.n 8000356 <__aeabi_fadd+0x4a> 800033a: 2800 cmp r0, #0 800033c: d12d bne.n 800039a <__aeabi_fadd+0x8e> 800033e: 2e00 cmp r6, #0 8000340: d100 bne.n 8000344 <__aeabi_fadd+0x38> 8000342: e08d b.n 8000460 <__aeabi_fadd+0x154> 8000344: 1e51 subs r1, r2, #1 8000346: 2a01 cmp r2, #1 8000348: d100 bne.n 800034c <__aeabi_fadd+0x40> 800034a: e11d b.n 8000588 <__aeabi_fadd+0x27c> 800034c: 2aff cmp r2, #255 @ 0xff 800034e: d100 bne.n 8000352 <__aeabi_fadd+0x46> 8000350: e0ab b.n 80004aa <__aeabi_fadd+0x19e> 8000352: 000a movs r2, r1 8000354: e027 b.n 80003a6 <__aeabi_fadd+0x9a> 8000356: 2a00 cmp r2, #0 8000358: d04d beq.n 80003f6 <__aeabi_fadd+0xea> 800035a: 1b42 subs r2, r0, r5 800035c: 2d00 cmp r5, #0 800035e: d000 beq.n 8000362 <__aeabi_fadd+0x56> 8000360: e0cc b.n 80004fc <__aeabi_fadd+0x1f0> 8000362: 2b00 cmp r3, #0 8000364: d100 bne.n 8000368 <__aeabi_fadd+0x5c> 8000366: e079 b.n 800045c <__aeabi_fadd+0x150> 8000368: 1e54 subs r4, r2, #1 800036a: 2a01 cmp r2, #1 800036c: d100 bne.n 8000370 <__aeabi_fadd+0x64> 800036e: e128 b.n 80005c2 <__aeabi_fadd+0x2b6> 8000370: 2aff cmp r2, #255 @ 0xff 8000372: d100 bne.n 8000376 <__aeabi_fadd+0x6a> 8000374: e097 b.n 80004a6 <__aeabi_fadd+0x19a> 8000376: 0022 movs r2, r4 8000378: e0c5 b.n 8000506 <__aeabi_fadd+0x1fa> 800037a: 2a00 cmp r2, #0 800037c: dc00 bgt.n 8000380 <__aeabi_fadd+0x74> 800037e: e096 b.n 80004ae <__aeabi_fadd+0x1a2> 8000380: 2800 cmp r0, #0 8000382: d04f beq.n 8000424 <__aeabi_fadd+0x118> 8000384: 2dff cmp r5, #255 @ 0xff 8000386: d100 bne.n 800038a <__aeabi_fadd+0x7e> 8000388: e08f b.n 80004aa <__aeabi_fadd+0x19e> 800038a: 2180 movs r1, #128 @ 0x80 800038c: 04c9 lsls r1, r1, #19 800038e: 430e orrs r6, r1 8000390: 2a1b cmp r2, #27 8000392: dd51 ble.n 8000438 <__aeabi_fadd+0x12c> 8000394: 002a movs r2, r5 8000396: 3301 adds r3, #1 8000398: e018 b.n 80003cc <__aeabi_fadd+0xc0> 800039a: 2dff cmp r5, #255 @ 0xff 800039c: d100 bne.n 80003a0 <__aeabi_fadd+0x94> 800039e: e084 b.n 80004aa <__aeabi_fadd+0x19e> 80003a0: 2180 movs r1, #128 @ 0x80 80003a2: 04c9 lsls r1, r1, #19 80003a4: 430e orrs r6, r1 80003a6: 2101 movs r1, #1 80003a8: 2a1b cmp r2, #27 80003aa: dc08 bgt.n 80003be <__aeabi_fadd+0xb2> 80003ac: 0031 movs r1, r6 80003ae: 2020 movs r0, #32 80003b0: 40d1 lsrs r1, r2 80003b2: 1a82 subs r2, r0, r2 80003b4: 4096 lsls r6, r2 80003b6: 0032 movs r2, r6 80003b8: 1e50 subs r0, r2, #1 80003ba: 4182 sbcs r2, r0 80003bc: 4311 orrs r1, r2 80003be: 1a5b subs r3, r3, r1 80003c0: 015a lsls r2, r3, #5 80003c2: d459 bmi.n 8000478 <__aeabi_fadd+0x16c> 80003c4: 2107 movs r1, #7 80003c6: 002a movs r2, r5 80003c8: 4019 ands r1, r3 80003ca: d049 beq.n 8000460 <__aeabi_fadd+0x154> 80003cc: 210f movs r1, #15 80003ce: 4019 ands r1, r3 80003d0: 2904 cmp r1, #4 80003d2: d000 beq.n 80003d6 <__aeabi_fadd+0xca> 80003d4: 3304 adds r3, #4 80003d6: 0159 lsls r1, r3, #5 80003d8: d542 bpl.n 8000460 <__aeabi_fadd+0x154> 80003da: 1c50 adds r0, r2, #1 80003dc: 2afe cmp r2, #254 @ 0xfe 80003de: d03a beq.n 8000456 <__aeabi_fadd+0x14a> 80003e0: 019b lsls r3, r3, #6 80003e2: b2c0 uxtb r0, r0 80003e4: 0a5b lsrs r3, r3, #9 80003e6: 05c0 lsls r0, r0, #23 80003e8: 4318 orrs r0, r3 80003ea: 07e4 lsls r4, r4, #31 80003ec: 4320 orrs r0, r4 80003ee: bcc0 pop {r6, r7} 80003f0: 46b9 mov r9, r7 80003f2: 46b0 mov r8, r6 80003f4: bdf8 pop {r3, r4, r5, r6, r7, pc} 80003f6: 20fe movs r0, #254 @ 0xfe 80003f8: 4680 mov r8, r0 80003fa: 1c6f adds r7, r5, #1 80003fc: 0038 movs r0, r7 80003fe: 4647 mov r7, r8 8000400: 4207 tst r7, r0 8000402: d000 beq.n 8000406 <__aeabi_fadd+0xfa> 8000404: e08e b.n 8000524 <__aeabi_fadd+0x218> 8000406: 2d00 cmp r5, #0 8000408: d000 beq.n 800040c <__aeabi_fadd+0x100> 800040a: e0b4 b.n 8000576 <__aeabi_fadd+0x26a> 800040c: 2b00 cmp r3, #0 800040e: d100 bne.n 8000412 <__aeabi_fadd+0x106> 8000410: e0db b.n 80005ca <__aeabi_fadd+0x2be> 8000412: 2e00 cmp r6, #0 8000414: d06c beq.n 80004f0 <__aeabi_fadd+0x1e4> 8000416: 1b98 subs r0, r3, r6 8000418: 0145 lsls r5, r0, #5 800041a: d400 bmi.n 800041e <__aeabi_fadd+0x112> 800041c: e0f7 b.n 800060e <__aeabi_fadd+0x302> 800041e: 000c movs r4, r1 8000420: 1af3 subs r3, r6, r3 8000422: e03d b.n 80004a0 <__aeabi_fadd+0x194> 8000424: 2e00 cmp r6, #0 8000426: d01b beq.n 8000460 <__aeabi_fadd+0x154> 8000428: 1e51 subs r1, r2, #1 800042a: 2a01 cmp r2, #1 800042c: d100 bne.n 8000430 <__aeabi_fadd+0x124> 800042e: e082 b.n 8000536 <__aeabi_fadd+0x22a> 8000430: 2aff cmp r2, #255 @ 0xff 8000432: d03a beq.n 80004aa <__aeabi_fadd+0x19e> 8000434: 000a movs r2, r1 8000436: e7ab b.n 8000390 <__aeabi_fadd+0x84> 8000438: 0031 movs r1, r6 800043a: 2020 movs r0, #32 800043c: 40d1 lsrs r1, r2 800043e: 1a82 subs r2, r0, r2 8000440: 4096 lsls r6, r2 8000442: 0032 movs r2, r6 8000444: 1e50 subs r0, r2, #1 8000446: 4182 sbcs r2, r0 8000448: 430a orrs r2, r1 800044a: 189b adds r3, r3, r2 800044c: 015a lsls r2, r3, #5 800044e: d5b9 bpl.n 80003c4 <__aeabi_fadd+0xb8> 8000450: 1c6a adds r2, r5, #1 8000452: 2dfe cmp r5, #254 @ 0xfe 8000454: d175 bne.n 8000542 <__aeabi_fadd+0x236> 8000456: 20ff movs r0, #255 @ 0xff 8000458: 2300 movs r3, #0 800045a: e7c4 b.n 80003e6 <__aeabi_fadd+0xda> 800045c: 000c movs r4, r1 800045e: 0033 movs r3, r6 8000460: 08db lsrs r3, r3, #3 8000462: 2aff cmp r2, #255 @ 0xff 8000464: d146 bne.n 80004f4 <__aeabi_fadd+0x1e8> 8000466: 2b00 cmp r3, #0 8000468: d0f5 beq.n 8000456 <__aeabi_fadd+0x14a> 800046a: 2280 movs r2, #128 @ 0x80 800046c: 03d2 lsls r2, r2, #15 800046e: 4313 orrs r3, r2 8000470: 025b lsls r3, r3, #9 8000472: 20ff movs r0, #255 @ 0xff 8000474: 0a5b lsrs r3, r3, #9 8000476: e7b6 b.n 80003e6 <__aeabi_fadd+0xda> 8000478: 019f lsls r7, r3, #6 800047a: 09bf lsrs r7, r7, #6 800047c: 0038 movs r0, r7 800047e: f002 fcdd bl 8002e3c <__clzsi2> 8000482: 3805 subs r0, #5 8000484: 4087 lsls r7, r0 8000486: 4285 cmp r5, r0 8000488: dc24 bgt.n 80004d4 <__aeabi_fadd+0x1c8> 800048a: 003b movs r3, r7 800048c: 2120 movs r1, #32 800048e: 1b42 subs r2, r0, r5 8000490: 3201 adds r2, #1 8000492: 40d3 lsrs r3, r2 8000494: 1a8a subs r2, r1, r2 8000496: 4097 lsls r7, r2 8000498: 1e7a subs r2, r7, #1 800049a: 4197 sbcs r7, r2 800049c: 2200 movs r2, #0 800049e: 433b orrs r3, r7 80004a0: 0759 lsls r1, r3, #29 80004a2: d193 bne.n 80003cc <__aeabi_fadd+0xc0> 80004a4: e797 b.n 80003d6 <__aeabi_fadd+0xca> 80004a6: 000c movs r4, r1 80004a8: 0033 movs r3, r6 80004aa: 08db lsrs r3, r3, #3 80004ac: e7db b.n 8000466 <__aeabi_fadd+0x15a> 80004ae: 2a00 cmp r2, #0 80004b0: d014 beq.n 80004dc <__aeabi_fadd+0x1d0> 80004b2: 1b42 subs r2, r0, r5 80004b4: 2d00 cmp r5, #0 80004b6: d14b bne.n 8000550 <__aeabi_fadd+0x244> 80004b8: 2b00 cmp r3, #0 80004ba: d0d0 beq.n 800045e <__aeabi_fadd+0x152> 80004bc: 1e51 subs r1, r2, #1 80004be: 2a01 cmp r2, #1 80004c0: d100 bne.n 80004c4 <__aeabi_fadd+0x1b8> 80004c2: e09e b.n 8000602 <__aeabi_fadd+0x2f6> 80004c4: 2aff cmp r2, #255 @ 0xff 80004c6: d0ef beq.n 80004a8 <__aeabi_fadd+0x19c> 80004c8: 000a movs r2, r1 80004ca: 2a1b cmp r2, #27 80004cc: dd5f ble.n 800058e <__aeabi_fadd+0x282> 80004ce: 0002 movs r2, r0 80004d0: 1c73 adds r3, r6, #1 80004d2: e77b b.n 80003cc <__aeabi_fadd+0xc0> 80004d4: 4b50 ldr r3, [pc, #320] @ (8000618 <__aeabi_fadd+0x30c>) 80004d6: 1a2a subs r2, r5, r0 80004d8: 403b ands r3, r7 80004da: e7e1 b.n 80004a0 <__aeabi_fadd+0x194> 80004dc: 21fe movs r1, #254 @ 0xfe 80004de: 1c6a adds r2, r5, #1 80004e0: 4211 tst r1, r2 80004e2: d13b bne.n 800055c <__aeabi_fadd+0x250> 80004e4: 2d00 cmp r5, #0 80004e6: d15d bne.n 80005a4 <__aeabi_fadd+0x298> 80004e8: 2b00 cmp r3, #0 80004ea: d07f beq.n 80005ec <__aeabi_fadd+0x2e0> 80004ec: 2e00 cmp r6, #0 80004ee: d17f bne.n 80005f0 <__aeabi_fadd+0x2e4> 80004f0: 2200 movs r2, #0 80004f2: 08db lsrs r3, r3, #3 80004f4: 025b lsls r3, r3, #9 80004f6: 0a5b lsrs r3, r3, #9 80004f8: b2d0 uxtb r0, r2 80004fa: e774 b.n 80003e6 <__aeabi_fadd+0xda> 80004fc: 28ff cmp r0, #255 @ 0xff 80004fe: d0d2 beq.n 80004a6 <__aeabi_fadd+0x19a> 8000500: 2480 movs r4, #128 @ 0x80 8000502: 04e4 lsls r4, r4, #19 8000504: 4323 orrs r3, r4 8000506: 2401 movs r4, #1 8000508: 2a1b cmp r2, #27 800050a: dc07 bgt.n 800051c <__aeabi_fadd+0x210> 800050c: 001c movs r4, r3 800050e: 2520 movs r5, #32 8000510: 40d4 lsrs r4, r2 8000512: 1aaa subs r2, r5, r2 8000514: 4093 lsls r3, r2 8000516: 1e5a subs r2, r3, #1 8000518: 4193 sbcs r3, r2 800051a: 431c orrs r4, r3 800051c: 1b33 subs r3, r6, r4 800051e: 0005 movs r5, r0 8000520: 000c movs r4, r1 8000522: e74d b.n 80003c0 <__aeabi_fadd+0xb4> 8000524: 1b9f subs r7, r3, r6 8000526: 017a lsls r2, r7, #5 8000528: d422 bmi.n 8000570 <__aeabi_fadd+0x264> 800052a: 2f00 cmp r7, #0 800052c: d1a6 bne.n 800047c <__aeabi_fadd+0x170> 800052e: 2400 movs r4, #0 8000530: 2000 movs r0, #0 8000532: 2300 movs r3, #0 8000534: e757 b.n 80003e6 <__aeabi_fadd+0xda> 8000536: 199b adds r3, r3, r6 8000538: 2501 movs r5, #1 800053a: 3201 adds r2, #1 800053c: 0159 lsls r1, r3, #5 800053e: d400 bmi.n 8000542 <__aeabi_fadd+0x236> 8000540: e740 b.n 80003c4 <__aeabi_fadd+0xb8> 8000542: 2101 movs r1, #1 8000544: 4835 ldr r0, [pc, #212] @ (800061c <__aeabi_fadd+0x310>) 8000546: 4019 ands r1, r3 8000548: 085b lsrs r3, r3, #1 800054a: 4003 ands r3, r0 800054c: 430b orrs r3, r1 800054e: e7a7 b.n 80004a0 <__aeabi_fadd+0x194> 8000550: 28ff cmp r0, #255 @ 0xff 8000552: d0a9 beq.n 80004a8 <__aeabi_fadd+0x19c> 8000554: 2180 movs r1, #128 @ 0x80 8000556: 04c9 lsls r1, r1, #19 8000558: 430b orrs r3, r1 800055a: e7b6 b.n 80004ca <__aeabi_fadd+0x1be> 800055c: 2aff cmp r2, #255 @ 0xff 800055e: d100 bne.n 8000562 <__aeabi_fadd+0x256> 8000560: e779 b.n 8000456 <__aeabi_fadd+0x14a> 8000562: 199b adds r3, r3, r6 8000564: 085b lsrs r3, r3, #1 8000566: 0759 lsls r1, r3, #29 8000568: d000 beq.n 800056c <__aeabi_fadd+0x260> 800056a: e72f b.n 80003cc <__aeabi_fadd+0xc0> 800056c: 08db lsrs r3, r3, #3 800056e: e7c1 b.n 80004f4 <__aeabi_fadd+0x1e8> 8000570: 000c movs r4, r1 8000572: 1af7 subs r7, r6, r3 8000574: e782 b.n 800047c <__aeabi_fadd+0x170> 8000576: 2b00 cmp r3, #0 8000578: d12c bne.n 80005d4 <__aeabi_fadd+0x2c8> 800057a: 2e00 cmp r6, #0 800057c: d193 bne.n 80004a6 <__aeabi_fadd+0x19a> 800057e: 2380 movs r3, #128 @ 0x80 8000580: 2400 movs r4, #0 8000582: 20ff movs r0, #255 @ 0xff 8000584: 03db lsls r3, r3, #15 8000586: e72e b.n 80003e6 <__aeabi_fadd+0xda> 8000588: 2501 movs r5, #1 800058a: 1b9b subs r3, r3, r6 800058c: e718 b.n 80003c0 <__aeabi_fadd+0xb4> 800058e: 0019 movs r1, r3 8000590: 2520 movs r5, #32 8000592: 40d1 lsrs r1, r2 8000594: 1aaa subs r2, r5, r2 8000596: 4093 lsls r3, r2 8000598: 1e5a subs r2, r3, #1 800059a: 4193 sbcs r3, r2 800059c: 430b orrs r3, r1 800059e: 0005 movs r5, r0 80005a0: 199b adds r3, r3, r6 80005a2: e753 b.n 800044c <__aeabi_fadd+0x140> 80005a4: 2b00 cmp r3, #0 80005a6: d100 bne.n 80005aa <__aeabi_fadd+0x29e> 80005a8: e77e b.n 80004a8 <__aeabi_fadd+0x19c> 80005aa: 2e00 cmp r6, #0 80005ac: d100 bne.n 80005b0 <__aeabi_fadd+0x2a4> 80005ae: e77c b.n 80004aa <__aeabi_fadd+0x19e> 80005b0: 2280 movs r2, #128 @ 0x80 80005b2: 03d2 lsls r2, r2, #15 80005b4: 4591 cmp r9, r2 80005b6: d302 bcc.n 80005be <__aeabi_fadd+0x2b2> 80005b8: 4594 cmp ip, r2 80005ba: d200 bcs.n 80005be <__aeabi_fadd+0x2b2> 80005bc: 0033 movs r3, r6 80005be: 08db lsrs r3, r3, #3 80005c0: e753 b.n 800046a <__aeabi_fadd+0x15e> 80005c2: 000c movs r4, r1 80005c4: 1af3 subs r3, r6, r3 80005c6: 3501 adds r5, #1 80005c8: e6fa b.n 80003c0 <__aeabi_fadd+0xb4> 80005ca: 2e00 cmp r6, #0 80005cc: d0af beq.n 800052e <__aeabi_fadd+0x222> 80005ce: 000c movs r4, r1 80005d0: 0033 movs r3, r6 80005d2: e78d b.n 80004f0 <__aeabi_fadd+0x1e4> 80005d4: 2e00 cmp r6, #0 80005d6: d100 bne.n 80005da <__aeabi_fadd+0x2ce> 80005d8: e767 b.n 80004aa <__aeabi_fadd+0x19e> 80005da: 2280 movs r2, #128 @ 0x80 80005dc: 03d2 lsls r2, r2, #15 80005de: 4591 cmp r9, r2 80005e0: d3ed bcc.n 80005be <__aeabi_fadd+0x2b2> 80005e2: 4594 cmp ip, r2 80005e4: d2eb bcs.n 80005be <__aeabi_fadd+0x2b2> 80005e6: 000c movs r4, r1 80005e8: 0033 movs r3, r6 80005ea: e7e8 b.n 80005be <__aeabi_fadd+0x2b2> 80005ec: 0033 movs r3, r6 80005ee: e77f b.n 80004f0 <__aeabi_fadd+0x1e4> 80005f0: 199b adds r3, r3, r6 80005f2: 2200 movs r2, #0 80005f4: 0159 lsls r1, r3, #5 80005f6: d5b9 bpl.n 800056c <__aeabi_fadd+0x260> 80005f8: 4a07 ldr r2, [pc, #28] @ (8000618 <__aeabi_fadd+0x30c>) 80005fa: 4013 ands r3, r2 80005fc: 08db lsrs r3, r3, #3 80005fe: 2201 movs r2, #1 8000600: e778 b.n 80004f4 <__aeabi_fadd+0x1e8> 8000602: 199b adds r3, r3, r6 8000604: 3201 adds r2, #1 8000606: 3501 adds r5, #1 8000608: 0159 lsls r1, r3, #5 800060a: d49a bmi.n 8000542 <__aeabi_fadd+0x236> 800060c: e6da b.n 80003c4 <__aeabi_fadd+0xb8> 800060e: 1e03 subs r3, r0, #0 8000610: d08d beq.n 800052e <__aeabi_fadd+0x222> 8000612: 08db lsrs r3, r3, #3 8000614: e76e b.n 80004f4 <__aeabi_fadd+0x1e8> 8000616: 46c0 nop @ (mov r8, r8) 8000618: fbffffff .word 0xfbffffff 800061c: 7dffffff .word 0x7dffffff 08000620 <__aeabi_fdiv>: 8000620: b5f0 push {r4, r5, r6, r7, lr} 8000622: 464f mov r7, r9 8000624: 4646 mov r6, r8 8000626: 46d6 mov lr, sl 8000628: 0244 lsls r4, r0, #9 800062a: b5c0 push {r6, r7, lr} 800062c: 0047 lsls r7, r0, #1 800062e: 1c0e adds r6, r1, #0 8000630: 0a64 lsrs r4, r4, #9 8000632: 0e3f lsrs r7, r7, #24 8000634: 0fc5 lsrs r5, r0, #31 8000636: 2f00 cmp r7, #0 8000638: d03c beq.n 80006b4 <__aeabi_fdiv+0x94> 800063a: 2fff cmp r7, #255 @ 0xff 800063c: d042 beq.n 80006c4 <__aeabi_fdiv+0xa4> 800063e: 2300 movs r3, #0 8000640: 2280 movs r2, #128 @ 0x80 8000642: 4699 mov r9, r3 8000644: 469a mov sl, r3 8000646: 00e4 lsls r4, r4, #3 8000648: 04d2 lsls r2, r2, #19 800064a: 4314 orrs r4, r2 800064c: 3f7f subs r7, #127 @ 0x7f 800064e: 0273 lsls r3, r6, #9 8000650: 0a5b lsrs r3, r3, #9 8000652: 4698 mov r8, r3 8000654: 0073 lsls r3, r6, #1 8000656: 0e1b lsrs r3, r3, #24 8000658: 0ff6 lsrs r6, r6, #31 800065a: 2b00 cmp r3, #0 800065c: d01b beq.n 8000696 <__aeabi_fdiv+0x76> 800065e: 2bff cmp r3, #255 @ 0xff 8000660: d013 beq.n 800068a <__aeabi_fdiv+0x6a> 8000662: 4642 mov r2, r8 8000664: 2180 movs r1, #128 @ 0x80 8000666: 00d2 lsls r2, r2, #3 8000668: 04c9 lsls r1, r1, #19 800066a: 4311 orrs r1, r2 800066c: 4688 mov r8, r1 800066e: 2000 movs r0, #0 8000670: 3b7f subs r3, #127 @ 0x7f 8000672: 0029 movs r1, r5 8000674: 1aff subs r7, r7, r3 8000676: 464b mov r3, r9 8000678: 4071 eors r1, r6 800067a: b2c9 uxtb r1, r1 800067c: 2b0f cmp r3, #15 800067e: d900 bls.n 8000682 <__aeabi_fdiv+0x62> 8000680: e0b5 b.n 80007ee <__aeabi_fdiv+0x1ce> 8000682: 4a74 ldr r2, [pc, #464] @ (8000854 <__aeabi_fdiv+0x234>) 8000684: 009b lsls r3, r3, #2 8000686: 58d3 ldr r3, [r2, r3] 8000688: 469f mov pc, r3 800068a: 4643 mov r3, r8 800068c: 2b00 cmp r3, #0 800068e: d13f bne.n 8000710 <__aeabi_fdiv+0xf0> 8000690: 3fff subs r7, #255 @ 0xff 8000692: 3302 adds r3, #2 8000694: e003 b.n 800069e <__aeabi_fdiv+0x7e> 8000696: 4643 mov r3, r8 8000698: 2b00 cmp r3, #0 800069a: d12d bne.n 80006f8 <__aeabi_fdiv+0xd8> 800069c: 2301 movs r3, #1 800069e: 0029 movs r1, r5 80006a0: 464a mov r2, r9 80006a2: 4071 eors r1, r6 80006a4: b2c9 uxtb r1, r1 80006a6: 431a orrs r2, r3 80006a8: 2a0e cmp r2, #14 80006aa: d838 bhi.n 800071e <__aeabi_fdiv+0xfe> 80006ac: 486a ldr r0, [pc, #424] @ (8000858 <__aeabi_fdiv+0x238>) 80006ae: 0092 lsls r2, r2, #2 80006b0: 5882 ldr r2, [r0, r2] 80006b2: 4697 mov pc, r2 80006b4: 2c00 cmp r4, #0 80006b6: d113 bne.n 80006e0 <__aeabi_fdiv+0xc0> 80006b8: 2304 movs r3, #4 80006ba: 4699 mov r9, r3 80006bc: 3b03 subs r3, #3 80006be: 2700 movs r7, #0 80006c0: 469a mov sl, r3 80006c2: e7c4 b.n 800064e <__aeabi_fdiv+0x2e> 80006c4: 2c00 cmp r4, #0 80006c6: d105 bne.n 80006d4 <__aeabi_fdiv+0xb4> 80006c8: 2308 movs r3, #8 80006ca: 4699 mov r9, r3 80006cc: 3b06 subs r3, #6 80006ce: 27ff movs r7, #255 @ 0xff 80006d0: 469a mov sl, r3 80006d2: e7bc b.n 800064e <__aeabi_fdiv+0x2e> 80006d4: 230c movs r3, #12 80006d6: 4699 mov r9, r3 80006d8: 3b09 subs r3, #9 80006da: 27ff movs r7, #255 @ 0xff 80006dc: 469a mov sl, r3 80006de: e7b6 b.n 800064e <__aeabi_fdiv+0x2e> 80006e0: 0020 movs r0, r4 80006e2: f002 fbab bl 8002e3c <__clzsi2> 80006e6: 2776 movs r7, #118 @ 0x76 80006e8: 1f43 subs r3, r0, #5 80006ea: 409c lsls r4, r3 80006ec: 2300 movs r3, #0 80006ee: 427f negs r7, r7 80006f0: 4699 mov r9, r3 80006f2: 469a mov sl, r3 80006f4: 1a3f subs r7, r7, r0 80006f6: e7aa b.n 800064e <__aeabi_fdiv+0x2e> 80006f8: 4640 mov r0, r8 80006fa: f002 fb9f bl 8002e3c <__clzsi2> 80006fe: 4642 mov r2, r8 8000700: 1f43 subs r3, r0, #5 8000702: 409a lsls r2, r3 8000704: 2376 movs r3, #118 @ 0x76 8000706: 425b negs r3, r3 8000708: 1a1b subs r3, r3, r0 800070a: 4690 mov r8, r2 800070c: 2000 movs r0, #0 800070e: e7b0 b.n 8000672 <__aeabi_fdiv+0x52> 8000710: 2303 movs r3, #3 8000712: 464a mov r2, r9 8000714: 431a orrs r2, r3 8000716: 4691 mov r9, r2 8000718: 2003 movs r0, #3 800071a: 33fc adds r3, #252 @ 0xfc 800071c: e7a9 b.n 8000672 <__aeabi_fdiv+0x52> 800071e: 000d movs r5, r1 8000720: 20ff movs r0, #255 @ 0xff 8000722: 2200 movs r2, #0 8000724: 05c0 lsls r0, r0, #23 8000726: 07ed lsls r5, r5, #31 8000728: 4310 orrs r0, r2 800072a: 4328 orrs r0, r5 800072c: bce0 pop {r5, r6, r7} 800072e: 46ba mov sl, r7 8000730: 46b1 mov r9, r6 8000732: 46a8 mov r8, r5 8000734: bdf0 pop {r4, r5, r6, r7, pc} 8000736: 000d movs r5, r1 8000738: 2000 movs r0, #0 800073a: 2200 movs r2, #0 800073c: e7f2 b.n 8000724 <__aeabi_fdiv+0x104> 800073e: 4653 mov r3, sl 8000740: 2b02 cmp r3, #2 8000742: d0ed beq.n 8000720 <__aeabi_fdiv+0x100> 8000744: 2b03 cmp r3, #3 8000746: d033 beq.n 80007b0 <__aeabi_fdiv+0x190> 8000748: 46a0 mov r8, r4 800074a: 2b01 cmp r3, #1 800074c: d105 bne.n 800075a <__aeabi_fdiv+0x13a> 800074e: 2000 movs r0, #0 8000750: 2200 movs r2, #0 8000752: e7e7 b.n 8000724 <__aeabi_fdiv+0x104> 8000754: 0035 movs r5, r6 8000756: 2803 cmp r0, #3 8000758: d07a beq.n 8000850 <__aeabi_fdiv+0x230> 800075a: 003b movs r3, r7 800075c: 337f adds r3, #127 @ 0x7f 800075e: 2b00 cmp r3, #0 8000760: dd2d ble.n 80007be <__aeabi_fdiv+0x19e> 8000762: 4642 mov r2, r8 8000764: 0752 lsls r2, r2, #29 8000766: d007 beq.n 8000778 <__aeabi_fdiv+0x158> 8000768: 220f movs r2, #15 800076a: 4641 mov r1, r8 800076c: 400a ands r2, r1 800076e: 2a04 cmp r2, #4 8000770: d002 beq.n 8000778 <__aeabi_fdiv+0x158> 8000772: 2204 movs r2, #4 8000774: 4694 mov ip, r2 8000776: 44e0 add r8, ip 8000778: 4642 mov r2, r8 800077a: 0112 lsls r2, r2, #4 800077c: d505 bpl.n 800078a <__aeabi_fdiv+0x16a> 800077e: 4642 mov r2, r8 8000780: 4b36 ldr r3, [pc, #216] @ (800085c <__aeabi_fdiv+0x23c>) 8000782: 401a ands r2, r3 8000784: 003b movs r3, r7 8000786: 4690 mov r8, r2 8000788: 3380 adds r3, #128 @ 0x80 800078a: 2bfe cmp r3, #254 @ 0xfe 800078c: dcc8 bgt.n 8000720 <__aeabi_fdiv+0x100> 800078e: 4642 mov r2, r8 8000790: 0192 lsls r2, r2, #6 8000792: 0a52 lsrs r2, r2, #9 8000794: b2d8 uxtb r0, r3 8000796: e7c5 b.n 8000724 <__aeabi_fdiv+0x104> 8000798: 2280 movs r2, #128 @ 0x80 800079a: 2500 movs r5, #0 800079c: 20ff movs r0, #255 @ 0xff 800079e: 03d2 lsls r2, r2, #15 80007a0: e7c0 b.n 8000724 <__aeabi_fdiv+0x104> 80007a2: 2280 movs r2, #128 @ 0x80 80007a4: 03d2 lsls r2, r2, #15 80007a6: 4214 tst r4, r2 80007a8: d002 beq.n 80007b0 <__aeabi_fdiv+0x190> 80007aa: 4643 mov r3, r8 80007ac: 4213 tst r3, r2 80007ae: d049 beq.n 8000844 <__aeabi_fdiv+0x224> 80007b0: 2280 movs r2, #128 @ 0x80 80007b2: 03d2 lsls r2, r2, #15 80007b4: 4322 orrs r2, r4 80007b6: 0252 lsls r2, r2, #9 80007b8: 20ff movs r0, #255 @ 0xff 80007ba: 0a52 lsrs r2, r2, #9 80007bc: e7b2 b.n 8000724 <__aeabi_fdiv+0x104> 80007be: 2201 movs r2, #1 80007c0: 1ad3 subs r3, r2, r3 80007c2: 2b1b cmp r3, #27 80007c4: dcc3 bgt.n 800074e <__aeabi_fdiv+0x12e> 80007c6: 4642 mov r2, r8 80007c8: 40da lsrs r2, r3 80007ca: 4643 mov r3, r8 80007cc: 379e adds r7, #158 @ 0x9e 80007ce: 40bb lsls r3, r7 80007d0: 1e59 subs r1, r3, #1 80007d2: 418b sbcs r3, r1 80007d4: 431a orrs r2, r3 80007d6: 0753 lsls r3, r2, #29 80007d8: d004 beq.n 80007e4 <__aeabi_fdiv+0x1c4> 80007da: 230f movs r3, #15 80007dc: 4013 ands r3, r2 80007de: 2b04 cmp r3, #4 80007e0: d000 beq.n 80007e4 <__aeabi_fdiv+0x1c4> 80007e2: 3204 adds r2, #4 80007e4: 0153 lsls r3, r2, #5 80007e6: d529 bpl.n 800083c <__aeabi_fdiv+0x21c> 80007e8: 2001 movs r0, #1 80007ea: 2200 movs r2, #0 80007ec: e79a b.n 8000724 <__aeabi_fdiv+0x104> 80007ee: 4642 mov r2, r8 80007f0: 0163 lsls r3, r4, #5 80007f2: 0155 lsls r5, r2, #5 80007f4: 42ab cmp r3, r5 80007f6: d215 bcs.n 8000824 <__aeabi_fdiv+0x204> 80007f8: 201b movs r0, #27 80007fa: 2200 movs r2, #0 80007fc: 3f01 subs r7, #1 80007fe: 2601 movs r6, #1 8000800: 001c movs r4, r3 8000802: 0052 lsls r2, r2, #1 8000804: 005b lsls r3, r3, #1 8000806: 2c00 cmp r4, #0 8000808: db01 blt.n 800080e <__aeabi_fdiv+0x1ee> 800080a: 429d cmp r5, r3 800080c: d801 bhi.n 8000812 <__aeabi_fdiv+0x1f2> 800080e: 1b5b subs r3, r3, r5 8000810: 4332 orrs r2, r6 8000812: 3801 subs r0, #1 8000814: 2800 cmp r0, #0 8000816: d1f3 bne.n 8000800 <__aeabi_fdiv+0x1e0> 8000818: 1e58 subs r0, r3, #1 800081a: 4183 sbcs r3, r0 800081c: 4313 orrs r3, r2 800081e: 4698 mov r8, r3 8000820: 000d movs r5, r1 8000822: e79a b.n 800075a <__aeabi_fdiv+0x13a> 8000824: 201a movs r0, #26 8000826: 2201 movs r2, #1 8000828: 1b5b subs r3, r3, r5 800082a: e7e8 b.n 80007fe <__aeabi_fdiv+0x1de> 800082c: 3b02 subs r3, #2 800082e: 425a negs r2, r3 8000830: 4153 adcs r3, r2 8000832: 425b negs r3, r3 8000834: 0035 movs r5, r6 8000836: 2200 movs r2, #0 8000838: b2d8 uxtb r0, r3 800083a: e773 b.n 8000724 <__aeabi_fdiv+0x104> 800083c: 0192 lsls r2, r2, #6 800083e: 2000 movs r0, #0 8000840: 0a52 lsrs r2, r2, #9 8000842: e76f b.n 8000724 <__aeabi_fdiv+0x104> 8000844: 431a orrs r2, r3 8000846: 0252 lsls r2, r2, #9 8000848: 0035 movs r5, r6 800084a: 20ff movs r0, #255 @ 0xff 800084c: 0a52 lsrs r2, r2, #9 800084e: e769 b.n 8000724 <__aeabi_fdiv+0x104> 8000850: 4644 mov r4, r8 8000852: e7ad b.n 80007b0 <__aeabi_fdiv+0x190> 8000854: 08009de0 .word 0x08009de0 8000858: 08009e20 .word 0x08009e20 800085c: f7ffffff .word 0xf7ffffff 08000860 <__eqsf2>: 8000860: b570 push {r4, r5, r6, lr} 8000862: 0042 lsls r2, r0, #1 8000864: 024e lsls r6, r1, #9 8000866: 004c lsls r4, r1, #1 8000868: 0245 lsls r5, r0, #9 800086a: 0a6d lsrs r5, r5, #9 800086c: 0e12 lsrs r2, r2, #24 800086e: 0fc3 lsrs r3, r0, #31 8000870: 0a76 lsrs r6, r6, #9 8000872: 0e24 lsrs r4, r4, #24 8000874: 0fc9 lsrs r1, r1, #31 8000876: 2aff cmp r2, #255 @ 0xff 8000878: d010 beq.n 800089c <__eqsf2+0x3c> 800087a: 2cff cmp r4, #255 @ 0xff 800087c: d00c beq.n 8000898 <__eqsf2+0x38> 800087e: 2001 movs r0, #1 8000880: 42a2 cmp r2, r4 8000882: d10a bne.n 800089a <__eqsf2+0x3a> 8000884: 42b5 cmp r5, r6 8000886: d108 bne.n 800089a <__eqsf2+0x3a> 8000888: 428b cmp r3, r1 800088a: d00f beq.n 80008ac <__eqsf2+0x4c> 800088c: 2a00 cmp r2, #0 800088e: d104 bne.n 800089a <__eqsf2+0x3a> 8000890: 0028 movs r0, r5 8000892: 1e43 subs r3, r0, #1 8000894: 4198 sbcs r0, r3 8000896: e000 b.n 800089a <__eqsf2+0x3a> 8000898: 2001 movs r0, #1 800089a: bd70 pop {r4, r5, r6, pc} 800089c: 2001 movs r0, #1 800089e: 2cff cmp r4, #255 @ 0xff 80008a0: d1fb bne.n 800089a <__eqsf2+0x3a> 80008a2: 4335 orrs r5, r6 80008a4: d1f9 bne.n 800089a <__eqsf2+0x3a> 80008a6: 404b eors r3, r1 80008a8: 0018 movs r0, r3 80008aa: e7f6 b.n 800089a <__eqsf2+0x3a> 80008ac: 2000 movs r0, #0 80008ae: e7f4 b.n 800089a <__eqsf2+0x3a> 080008b0 <__gesf2>: 80008b0: b530 push {r4, r5, lr} 80008b2: 0042 lsls r2, r0, #1 80008b4: 0244 lsls r4, r0, #9 80008b6: 024d lsls r5, r1, #9 80008b8: 0fc3 lsrs r3, r0, #31 80008ba: 0048 lsls r0, r1, #1 80008bc: 0a64 lsrs r4, r4, #9 80008be: 0e12 lsrs r2, r2, #24 80008c0: 0a6d lsrs r5, r5, #9 80008c2: 0e00 lsrs r0, r0, #24 80008c4: 0fc9 lsrs r1, r1, #31 80008c6: 2aff cmp r2, #255 @ 0xff 80008c8: d019 beq.n 80008fe <__gesf2+0x4e> 80008ca: 28ff cmp r0, #255 @ 0xff 80008cc: d00b beq.n 80008e6 <__gesf2+0x36> 80008ce: 2a00 cmp r2, #0 80008d0: d11e bne.n 8000910 <__gesf2+0x60> 80008d2: 2800 cmp r0, #0 80008d4: d10b bne.n 80008ee <__gesf2+0x3e> 80008d6: 2d00 cmp r5, #0 80008d8: d027 beq.n 800092a <__gesf2+0x7a> 80008da: 2c00 cmp r4, #0 80008dc: d134 bne.n 8000948 <__gesf2+0x98> 80008de: 2900 cmp r1, #0 80008e0: d02f beq.n 8000942 <__gesf2+0x92> 80008e2: 0008 movs r0, r1 80008e4: bd30 pop {r4, r5, pc} 80008e6: 2d00 cmp r5, #0 80008e8: d128 bne.n 800093c <__gesf2+0x8c> 80008ea: 2a00 cmp r2, #0 80008ec: d101 bne.n 80008f2 <__gesf2+0x42> 80008ee: 2c00 cmp r4, #0 80008f0: d0f5 beq.n 80008de <__gesf2+0x2e> 80008f2: 428b cmp r3, r1 80008f4: d107 bne.n 8000906 <__gesf2+0x56> 80008f6: 2b00 cmp r3, #0 80008f8: d023 beq.n 8000942 <__gesf2+0x92> 80008fa: 0018 movs r0, r3 80008fc: e7f2 b.n 80008e4 <__gesf2+0x34> 80008fe: 2c00 cmp r4, #0 8000900: d11c bne.n 800093c <__gesf2+0x8c> 8000902: 28ff cmp r0, #255 @ 0xff 8000904: d014 beq.n 8000930 <__gesf2+0x80> 8000906: 1e58 subs r0, r3, #1 8000908: 2302 movs r3, #2 800090a: 4018 ands r0, r3 800090c: 3801 subs r0, #1 800090e: e7e9 b.n 80008e4 <__gesf2+0x34> 8000910: 2800 cmp r0, #0 8000912: d0f8 beq.n 8000906 <__gesf2+0x56> 8000914: 428b cmp r3, r1 8000916: d1f6 bne.n 8000906 <__gesf2+0x56> 8000918: 4282 cmp r2, r0 800091a: dcf4 bgt.n 8000906 <__gesf2+0x56> 800091c: dbeb blt.n 80008f6 <__gesf2+0x46> 800091e: 42ac cmp r4, r5 8000920: d8f1 bhi.n 8000906 <__gesf2+0x56> 8000922: 2000 movs r0, #0 8000924: 42ac cmp r4, r5 8000926: d2dd bcs.n 80008e4 <__gesf2+0x34> 8000928: e7e5 b.n 80008f6 <__gesf2+0x46> 800092a: 2c00 cmp r4, #0 800092c: d0da beq.n 80008e4 <__gesf2+0x34> 800092e: e7ea b.n 8000906 <__gesf2+0x56> 8000930: 2d00 cmp r5, #0 8000932: d103 bne.n 800093c <__gesf2+0x8c> 8000934: 428b cmp r3, r1 8000936: d1e6 bne.n 8000906 <__gesf2+0x56> 8000938: 2000 movs r0, #0 800093a: e7d3 b.n 80008e4 <__gesf2+0x34> 800093c: 2002 movs r0, #2 800093e: 4240 negs r0, r0 8000940: e7d0 b.n 80008e4 <__gesf2+0x34> 8000942: 2001 movs r0, #1 8000944: 4240 negs r0, r0 8000946: e7cd b.n 80008e4 <__gesf2+0x34> 8000948: 428b cmp r3, r1 800094a: d0e8 beq.n 800091e <__gesf2+0x6e> 800094c: e7db b.n 8000906 <__gesf2+0x56> 800094e: 46c0 nop @ (mov r8, r8) 08000950 <__lesf2>: 8000950: b530 push {r4, r5, lr} 8000952: 0042 lsls r2, r0, #1 8000954: 0244 lsls r4, r0, #9 8000956: 024d lsls r5, r1, #9 8000958: 0fc3 lsrs r3, r0, #31 800095a: 0048 lsls r0, r1, #1 800095c: 0a64 lsrs r4, r4, #9 800095e: 0e12 lsrs r2, r2, #24 8000960: 0a6d lsrs r5, r5, #9 8000962: 0e00 lsrs r0, r0, #24 8000964: 0fc9 lsrs r1, r1, #31 8000966: 2aff cmp r2, #255 @ 0xff 8000968: d01a beq.n 80009a0 <__lesf2+0x50> 800096a: 28ff cmp r0, #255 @ 0xff 800096c: d00e beq.n 800098c <__lesf2+0x3c> 800096e: 2a00 cmp r2, #0 8000970: d11e bne.n 80009b0 <__lesf2+0x60> 8000972: 2800 cmp r0, #0 8000974: d10e bne.n 8000994 <__lesf2+0x44> 8000976: 2d00 cmp r5, #0 8000978: d02a beq.n 80009d0 <__lesf2+0x80> 800097a: 2c00 cmp r4, #0 800097c: d00c beq.n 8000998 <__lesf2+0x48> 800097e: 428b cmp r3, r1 8000980: d01d beq.n 80009be <__lesf2+0x6e> 8000982: 1e58 subs r0, r3, #1 8000984: 2302 movs r3, #2 8000986: 4018 ands r0, r3 8000988: 3801 subs r0, #1 800098a: e010 b.n 80009ae <__lesf2+0x5e> 800098c: 2d00 cmp r5, #0 800098e: d10d bne.n 80009ac <__lesf2+0x5c> 8000990: 2a00 cmp r2, #0 8000992: d120 bne.n 80009d6 <__lesf2+0x86> 8000994: 2c00 cmp r4, #0 8000996: d11e bne.n 80009d6 <__lesf2+0x86> 8000998: 2900 cmp r1, #0 800099a: d023 beq.n 80009e4 <__lesf2+0x94> 800099c: 0008 movs r0, r1 800099e: e006 b.n 80009ae <__lesf2+0x5e> 80009a0: 2c00 cmp r4, #0 80009a2: d103 bne.n 80009ac <__lesf2+0x5c> 80009a4: 28ff cmp r0, #255 @ 0xff 80009a6: d1ec bne.n 8000982 <__lesf2+0x32> 80009a8: 2d00 cmp r5, #0 80009aa: d017 beq.n 80009dc <__lesf2+0x8c> 80009ac: 2002 movs r0, #2 80009ae: bd30 pop {r4, r5, pc} 80009b0: 2800 cmp r0, #0 80009b2: d0e6 beq.n 8000982 <__lesf2+0x32> 80009b4: 428b cmp r3, r1 80009b6: d1e4 bne.n 8000982 <__lesf2+0x32> 80009b8: 4282 cmp r2, r0 80009ba: dce2 bgt.n 8000982 <__lesf2+0x32> 80009bc: db04 blt.n 80009c8 <__lesf2+0x78> 80009be: 42ac cmp r4, r5 80009c0: d8df bhi.n 8000982 <__lesf2+0x32> 80009c2: 2000 movs r0, #0 80009c4: 42ac cmp r4, r5 80009c6: d2f2 bcs.n 80009ae <__lesf2+0x5e> 80009c8: 2b00 cmp r3, #0 80009ca: d00b beq.n 80009e4 <__lesf2+0x94> 80009cc: 0018 movs r0, r3 80009ce: e7ee b.n 80009ae <__lesf2+0x5e> 80009d0: 2c00 cmp r4, #0 80009d2: d0ec beq.n 80009ae <__lesf2+0x5e> 80009d4: e7d5 b.n 8000982 <__lesf2+0x32> 80009d6: 428b cmp r3, r1 80009d8: d1d3 bne.n 8000982 <__lesf2+0x32> 80009da: e7f5 b.n 80009c8 <__lesf2+0x78> 80009dc: 2000 movs r0, #0 80009de: 428b cmp r3, r1 80009e0: d0e5 beq.n 80009ae <__lesf2+0x5e> 80009e2: e7ce b.n 8000982 <__lesf2+0x32> 80009e4: 2001 movs r0, #1 80009e6: 4240 negs r0, r0 80009e8: e7e1 b.n 80009ae <__lesf2+0x5e> 80009ea: 46c0 nop @ (mov r8, r8) 080009ec <__aeabi_fmul>: 80009ec: b5f0 push {r4, r5, r6, r7, lr} 80009ee: 464f mov r7, r9 80009f0: 4646 mov r6, r8 80009f2: 46d6 mov lr, sl 80009f4: 0243 lsls r3, r0, #9 80009f6: 0a5b lsrs r3, r3, #9 80009f8: 0045 lsls r5, r0, #1 80009fa: b5c0 push {r6, r7, lr} 80009fc: 4699 mov r9, r3 80009fe: 1c0f adds r7, r1, #0 8000a00: 0e2d lsrs r5, r5, #24 8000a02: 0fc6 lsrs r6, r0, #31 8000a04: 2d00 cmp r5, #0 8000a06: d100 bne.n 8000a0a <__aeabi_fmul+0x1e> 8000a08: e088 b.n 8000b1c <__aeabi_fmul+0x130> 8000a0a: 2dff cmp r5, #255 @ 0xff 8000a0c: d100 bne.n 8000a10 <__aeabi_fmul+0x24> 8000a0e: e08d b.n 8000b2c <__aeabi_fmul+0x140> 8000a10: 2280 movs r2, #128 @ 0x80 8000a12: 00db lsls r3, r3, #3 8000a14: 04d2 lsls r2, r2, #19 8000a16: 431a orrs r2, r3 8000a18: 2300 movs r3, #0 8000a1a: 4691 mov r9, r2 8000a1c: 4698 mov r8, r3 8000a1e: 469a mov sl, r3 8000a20: 3d7f subs r5, #127 @ 0x7f 8000a22: 027c lsls r4, r7, #9 8000a24: 007b lsls r3, r7, #1 8000a26: 0a64 lsrs r4, r4, #9 8000a28: 0e1b lsrs r3, r3, #24 8000a2a: 0fff lsrs r7, r7, #31 8000a2c: 2b00 cmp r3, #0 8000a2e: d068 beq.n 8000b02 <__aeabi_fmul+0x116> 8000a30: 2bff cmp r3, #255 @ 0xff 8000a32: d021 beq.n 8000a78 <__aeabi_fmul+0x8c> 8000a34: 2280 movs r2, #128 @ 0x80 8000a36: 00e4 lsls r4, r4, #3 8000a38: 04d2 lsls r2, r2, #19 8000a3a: 4314 orrs r4, r2 8000a3c: 4642 mov r2, r8 8000a3e: 3b7f subs r3, #127 @ 0x7f 8000a40: 195b adds r3, r3, r5 8000a42: 2100 movs r1, #0 8000a44: 1c5d adds r5, r3, #1 8000a46: 2a0a cmp r2, #10 8000a48: dc2e bgt.n 8000aa8 <__aeabi_fmul+0xbc> 8000a4a: 407e eors r6, r7 8000a4c: 4642 mov r2, r8 8000a4e: 2a02 cmp r2, #2 8000a50: dc23 bgt.n 8000a9a <__aeabi_fmul+0xae> 8000a52: 3a01 subs r2, #1 8000a54: 2a01 cmp r2, #1 8000a56: d900 bls.n 8000a5a <__aeabi_fmul+0x6e> 8000a58: e0bd b.n 8000bd6 <__aeabi_fmul+0x1ea> 8000a5a: 2902 cmp r1, #2 8000a5c: d06e beq.n 8000b3c <__aeabi_fmul+0x150> 8000a5e: 2901 cmp r1, #1 8000a60: d12c bne.n 8000abc <__aeabi_fmul+0xd0> 8000a62: 2000 movs r0, #0 8000a64: 2200 movs r2, #0 8000a66: 05c0 lsls r0, r0, #23 8000a68: 07f6 lsls r6, r6, #31 8000a6a: 4310 orrs r0, r2 8000a6c: 4330 orrs r0, r6 8000a6e: bce0 pop {r5, r6, r7} 8000a70: 46ba mov sl, r7 8000a72: 46b1 mov r9, r6 8000a74: 46a8 mov r8, r5 8000a76: bdf0 pop {r4, r5, r6, r7, pc} 8000a78: 002b movs r3, r5 8000a7a: 33ff adds r3, #255 @ 0xff 8000a7c: 2c00 cmp r4, #0 8000a7e: d065 beq.n 8000b4c <__aeabi_fmul+0x160> 8000a80: 2203 movs r2, #3 8000a82: 4641 mov r1, r8 8000a84: 4311 orrs r1, r2 8000a86: 0032 movs r2, r6 8000a88: 3501 adds r5, #1 8000a8a: 4688 mov r8, r1 8000a8c: 407a eors r2, r7 8000a8e: 35ff adds r5, #255 @ 0xff 8000a90: 290a cmp r1, #10 8000a92: dd00 ble.n 8000a96 <__aeabi_fmul+0xaa> 8000a94: e0d8 b.n 8000c48 <__aeabi_fmul+0x25c> 8000a96: 0016 movs r6, r2 8000a98: 2103 movs r1, #3 8000a9a: 4640 mov r0, r8 8000a9c: 2201 movs r2, #1 8000a9e: 4082 lsls r2, r0 8000aa0: 20a6 movs r0, #166 @ 0xa6 8000aa2: 00c0 lsls r0, r0, #3 8000aa4: 4202 tst r2, r0 8000aa6: d020 beq.n 8000aea <__aeabi_fmul+0xfe> 8000aa8: 4653 mov r3, sl 8000aaa: 2b02 cmp r3, #2 8000aac: d046 beq.n 8000b3c <__aeabi_fmul+0x150> 8000aae: 2b03 cmp r3, #3 8000ab0: d100 bne.n 8000ab4 <__aeabi_fmul+0xc8> 8000ab2: e0bb b.n 8000c2c <__aeabi_fmul+0x240> 8000ab4: 4651 mov r1, sl 8000ab6: 464c mov r4, r9 8000ab8: 2901 cmp r1, #1 8000aba: d0d2 beq.n 8000a62 <__aeabi_fmul+0x76> 8000abc: 002b movs r3, r5 8000abe: 337f adds r3, #127 @ 0x7f 8000ac0: 2b00 cmp r3, #0 8000ac2: dd70 ble.n 8000ba6 <__aeabi_fmul+0x1ba> 8000ac4: 0762 lsls r2, r4, #29 8000ac6: d004 beq.n 8000ad2 <__aeabi_fmul+0xe6> 8000ac8: 220f movs r2, #15 8000aca: 4022 ands r2, r4 8000acc: 2a04 cmp r2, #4 8000ace: d000 beq.n 8000ad2 <__aeabi_fmul+0xe6> 8000ad0: 3404 adds r4, #4 8000ad2: 0122 lsls r2, r4, #4 8000ad4: d503 bpl.n 8000ade <__aeabi_fmul+0xf2> 8000ad6: 4b63 ldr r3, [pc, #396] @ (8000c64 <__aeabi_fmul+0x278>) 8000ad8: 401c ands r4, r3 8000ada: 002b movs r3, r5 8000adc: 3380 adds r3, #128 @ 0x80 8000ade: 2bfe cmp r3, #254 @ 0xfe 8000ae0: dc2c bgt.n 8000b3c <__aeabi_fmul+0x150> 8000ae2: 01a2 lsls r2, r4, #6 8000ae4: 0a52 lsrs r2, r2, #9 8000ae6: b2d8 uxtb r0, r3 8000ae8: e7bd b.n 8000a66 <__aeabi_fmul+0x7a> 8000aea: 2090 movs r0, #144 @ 0x90 8000aec: 0080 lsls r0, r0, #2 8000aee: 4202 tst r2, r0 8000af0: d127 bne.n 8000b42 <__aeabi_fmul+0x156> 8000af2: 38b9 subs r0, #185 @ 0xb9 8000af4: 38ff subs r0, #255 @ 0xff 8000af6: 4210 tst r0, r2 8000af8: d06d beq.n 8000bd6 <__aeabi_fmul+0x1ea> 8000afa: 003e movs r6, r7 8000afc: 46a1 mov r9, r4 8000afe: 468a mov sl, r1 8000b00: e7d2 b.n 8000aa8 <__aeabi_fmul+0xbc> 8000b02: 2c00 cmp r4, #0 8000b04: d141 bne.n 8000b8a <__aeabi_fmul+0x19e> 8000b06: 2301 movs r3, #1 8000b08: 4642 mov r2, r8 8000b0a: 431a orrs r2, r3 8000b0c: 4690 mov r8, r2 8000b0e: 002b movs r3, r5 8000b10: 4642 mov r2, r8 8000b12: 2101 movs r1, #1 8000b14: 1c5d adds r5, r3, #1 8000b16: 2a0a cmp r2, #10 8000b18: dd97 ble.n 8000a4a <__aeabi_fmul+0x5e> 8000b1a: e7c5 b.n 8000aa8 <__aeabi_fmul+0xbc> 8000b1c: 2b00 cmp r3, #0 8000b1e: d126 bne.n 8000b6e <__aeabi_fmul+0x182> 8000b20: 2304 movs r3, #4 8000b22: 4698 mov r8, r3 8000b24: 3b03 subs r3, #3 8000b26: 2500 movs r5, #0 8000b28: 469a mov sl, r3 8000b2a: e77a b.n 8000a22 <__aeabi_fmul+0x36> 8000b2c: 2b00 cmp r3, #0 8000b2e: d118 bne.n 8000b62 <__aeabi_fmul+0x176> 8000b30: 2308 movs r3, #8 8000b32: 4698 mov r8, r3 8000b34: 3b06 subs r3, #6 8000b36: 25ff movs r5, #255 @ 0xff 8000b38: 469a mov sl, r3 8000b3a: e772 b.n 8000a22 <__aeabi_fmul+0x36> 8000b3c: 20ff movs r0, #255 @ 0xff 8000b3e: 2200 movs r2, #0 8000b40: e791 b.n 8000a66 <__aeabi_fmul+0x7a> 8000b42: 2280 movs r2, #128 @ 0x80 8000b44: 2600 movs r6, #0 8000b46: 20ff movs r0, #255 @ 0xff 8000b48: 03d2 lsls r2, r2, #15 8000b4a: e78c b.n 8000a66 <__aeabi_fmul+0x7a> 8000b4c: 4641 mov r1, r8 8000b4e: 2202 movs r2, #2 8000b50: 3501 adds r5, #1 8000b52: 4311 orrs r1, r2 8000b54: 4688 mov r8, r1 8000b56: 35ff adds r5, #255 @ 0xff 8000b58: 290a cmp r1, #10 8000b5a: dca5 bgt.n 8000aa8 <__aeabi_fmul+0xbc> 8000b5c: 2102 movs r1, #2 8000b5e: 407e eors r6, r7 8000b60: e774 b.n 8000a4c <__aeabi_fmul+0x60> 8000b62: 230c movs r3, #12 8000b64: 4698 mov r8, r3 8000b66: 3b09 subs r3, #9 8000b68: 25ff movs r5, #255 @ 0xff 8000b6a: 469a mov sl, r3 8000b6c: e759 b.n 8000a22 <__aeabi_fmul+0x36> 8000b6e: 0018 movs r0, r3 8000b70: f002 f964 bl 8002e3c <__clzsi2> 8000b74: 464a mov r2, r9 8000b76: 1f43 subs r3, r0, #5 8000b78: 2576 movs r5, #118 @ 0x76 8000b7a: 409a lsls r2, r3 8000b7c: 2300 movs r3, #0 8000b7e: 426d negs r5, r5 8000b80: 4691 mov r9, r2 8000b82: 4698 mov r8, r3 8000b84: 469a mov sl, r3 8000b86: 1a2d subs r5, r5, r0 8000b88: e74b b.n 8000a22 <__aeabi_fmul+0x36> 8000b8a: 0020 movs r0, r4 8000b8c: f002 f956 bl 8002e3c <__clzsi2> 8000b90: 4642 mov r2, r8 8000b92: 1f43 subs r3, r0, #5 8000b94: 409c lsls r4, r3 8000b96: 1a2b subs r3, r5, r0 8000b98: 3b76 subs r3, #118 @ 0x76 8000b9a: 2100 movs r1, #0 8000b9c: 1c5d adds r5, r3, #1 8000b9e: 2a0a cmp r2, #10 8000ba0: dc00 bgt.n 8000ba4 <__aeabi_fmul+0x1b8> 8000ba2: e752 b.n 8000a4a <__aeabi_fmul+0x5e> 8000ba4: e780 b.n 8000aa8 <__aeabi_fmul+0xbc> 8000ba6: 2201 movs r2, #1 8000ba8: 1ad3 subs r3, r2, r3 8000baa: 2b1b cmp r3, #27 8000bac: dd00 ble.n 8000bb0 <__aeabi_fmul+0x1c4> 8000bae: e758 b.n 8000a62 <__aeabi_fmul+0x76> 8000bb0: 359e adds r5, #158 @ 0x9e 8000bb2: 0022 movs r2, r4 8000bb4: 40ac lsls r4, r5 8000bb6: 40da lsrs r2, r3 8000bb8: 1e63 subs r3, r4, #1 8000bba: 419c sbcs r4, r3 8000bbc: 4322 orrs r2, r4 8000bbe: 0753 lsls r3, r2, #29 8000bc0: d004 beq.n 8000bcc <__aeabi_fmul+0x1e0> 8000bc2: 230f movs r3, #15 8000bc4: 4013 ands r3, r2 8000bc6: 2b04 cmp r3, #4 8000bc8: d000 beq.n 8000bcc <__aeabi_fmul+0x1e0> 8000bca: 3204 adds r2, #4 8000bcc: 0153 lsls r3, r2, #5 8000bce: d537 bpl.n 8000c40 <__aeabi_fmul+0x254> 8000bd0: 2001 movs r0, #1 8000bd2: 2200 movs r2, #0 8000bd4: e747 b.n 8000a66 <__aeabi_fmul+0x7a> 8000bd6: 0c21 lsrs r1, r4, #16 8000bd8: 464a mov r2, r9 8000bda: 0424 lsls r4, r4, #16 8000bdc: 0c24 lsrs r4, r4, #16 8000bde: 0027 movs r7, r4 8000be0: 0c10 lsrs r0, r2, #16 8000be2: 0412 lsls r2, r2, #16 8000be4: 0c12 lsrs r2, r2, #16 8000be6: 4344 muls r4, r0 8000be8: 4357 muls r7, r2 8000bea: 4348 muls r0, r1 8000bec: 4351 muls r1, r2 8000bee: 0c3a lsrs r2, r7, #16 8000bf0: 1909 adds r1, r1, r4 8000bf2: 1852 adds r2, r2, r1 8000bf4: 4294 cmp r4, r2 8000bf6: d903 bls.n 8000c00 <__aeabi_fmul+0x214> 8000bf8: 2180 movs r1, #128 @ 0x80 8000bfa: 0249 lsls r1, r1, #9 8000bfc: 468c mov ip, r1 8000bfe: 4460 add r0, ip 8000c00: 043f lsls r7, r7, #16 8000c02: 0411 lsls r1, r2, #16 8000c04: 0c3f lsrs r7, r7, #16 8000c06: 19c9 adds r1, r1, r7 8000c08: 018c lsls r4, r1, #6 8000c0a: 1e67 subs r7, r4, #1 8000c0c: 41bc sbcs r4, r7 8000c0e: 0c12 lsrs r2, r2, #16 8000c10: 0e89 lsrs r1, r1, #26 8000c12: 1812 adds r2, r2, r0 8000c14: 430c orrs r4, r1 8000c16: 0192 lsls r2, r2, #6 8000c18: 4314 orrs r4, r2 8000c1a: 0112 lsls r2, r2, #4 8000c1c: d50e bpl.n 8000c3c <__aeabi_fmul+0x250> 8000c1e: 2301 movs r3, #1 8000c20: 0862 lsrs r2, r4, #1 8000c22: 401c ands r4, r3 8000c24: 4314 orrs r4, r2 8000c26: e749 b.n 8000abc <__aeabi_fmul+0xd0> 8000c28: 003e movs r6, r7 8000c2a: 46a1 mov r9, r4 8000c2c: 2280 movs r2, #128 @ 0x80 8000c2e: 464b mov r3, r9 8000c30: 03d2 lsls r2, r2, #15 8000c32: 431a orrs r2, r3 8000c34: 0252 lsls r2, r2, #9 8000c36: 20ff movs r0, #255 @ 0xff 8000c38: 0a52 lsrs r2, r2, #9 8000c3a: e714 b.n 8000a66 <__aeabi_fmul+0x7a> 8000c3c: 001d movs r5, r3 8000c3e: e73d b.n 8000abc <__aeabi_fmul+0xd0> 8000c40: 0192 lsls r2, r2, #6 8000c42: 2000 movs r0, #0 8000c44: 0a52 lsrs r2, r2, #9 8000c46: e70e b.n 8000a66 <__aeabi_fmul+0x7a> 8000c48: 290f cmp r1, #15 8000c4a: d1ed bne.n 8000c28 <__aeabi_fmul+0x23c> 8000c4c: 2280 movs r2, #128 @ 0x80 8000c4e: 464b mov r3, r9 8000c50: 03d2 lsls r2, r2, #15 8000c52: 4213 tst r3, r2 8000c54: d0ea beq.n 8000c2c <__aeabi_fmul+0x240> 8000c56: 4214 tst r4, r2 8000c58: d1e8 bne.n 8000c2c <__aeabi_fmul+0x240> 8000c5a: 003e movs r6, r7 8000c5c: 20ff movs r0, #255 @ 0xff 8000c5e: 4322 orrs r2, r4 8000c60: e701 b.n 8000a66 <__aeabi_fmul+0x7a> 8000c62: 46c0 nop @ (mov r8, r8) 8000c64: f7ffffff .word 0xf7ffffff 08000c68 <__aeabi_fsub>: 8000c68: b5f8 push {r3, r4, r5, r6, r7, lr} 8000c6a: 4647 mov r7, r8 8000c6c: 46ce mov lr, r9 8000c6e: 024e lsls r6, r1, #9 8000c70: 0243 lsls r3, r0, #9 8000c72: 0045 lsls r5, r0, #1 8000c74: 0a72 lsrs r2, r6, #9 8000c76: 0fc4 lsrs r4, r0, #31 8000c78: 0048 lsls r0, r1, #1 8000c7a: b580 push {r7, lr} 8000c7c: 4694 mov ip, r2 8000c7e: 0a5f lsrs r7, r3, #9 8000c80: 0e2d lsrs r5, r5, #24 8000c82: 099b lsrs r3, r3, #6 8000c84: 0e00 lsrs r0, r0, #24 8000c86: 0fc9 lsrs r1, r1, #31 8000c88: 09b6 lsrs r6, r6, #6 8000c8a: 28ff cmp r0, #255 @ 0xff 8000c8c: d024 beq.n 8000cd8 <__aeabi_fsub+0x70> 8000c8e: 2201 movs r2, #1 8000c90: 4051 eors r1, r2 8000c92: 1a2a subs r2, r5, r0 8000c94: 428c cmp r4, r1 8000c96: d00f beq.n 8000cb8 <__aeabi_fsub+0x50> 8000c98: 2a00 cmp r2, #0 8000c9a: dc00 bgt.n 8000c9e <__aeabi_fsub+0x36> 8000c9c: e16a b.n 8000f74 <__aeabi_fsub+0x30c> 8000c9e: 2800 cmp r0, #0 8000ca0: d135 bne.n 8000d0e <__aeabi_fsub+0xa6> 8000ca2: 2e00 cmp r6, #0 8000ca4: d100 bne.n 8000ca8 <__aeabi_fsub+0x40> 8000ca6: e0a2 b.n 8000dee <__aeabi_fsub+0x186> 8000ca8: 1e51 subs r1, r2, #1 8000caa: 2a01 cmp r2, #1 8000cac: d100 bne.n 8000cb0 <__aeabi_fsub+0x48> 8000cae: e124 b.n 8000efa <__aeabi_fsub+0x292> 8000cb0: 2aff cmp r2, #255 @ 0xff 8000cb2: d021 beq.n 8000cf8 <__aeabi_fsub+0x90> 8000cb4: 000a movs r2, r1 8000cb6: e02f b.n 8000d18 <__aeabi_fsub+0xb0> 8000cb8: 2a00 cmp r2, #0 8000cba: dc00 bgt.n 8000cbe <__aeabi_fsub+0x56> 8000cbc: e167 b.n 8000f8e <__aeabi_fsub+0x326> 8000cbe: 2800 cmp r0, #0 8000cc0: d05e beq.n 8000d80 <__aeabi_fsub+0x118> 8000cc2: 2dff cmp r5, #255 @ 0xff 8000cc4: d018 beq.n 8000cf8 <__aeabi_fsub+0x90> 8000cc6: 2180 movs r1, #128 @ 0x80 8000cc8: 04c9 lsls r1, r1, #19 8000cca: 430e orrs r6, r1 8000ccc: 2a1b cmp r2, #27 8000cce: dc00 bgt.n 8000cd2 <__aeabi_fsub+0x6a> 8000cd0: e076 b.n 8000dc0 <__aeabi_fsub+0x158> 8000cd2: 002a movs r2, r5 8000cd4: 3301 adds r3, #1 8000cd6: e032 b.n 8000d3e <__aeabi_fsub+0xd6> 8000cd8: 002a movs r2, r5 8000cda: 3aff subs r2, #255 @ 0xff 8000cdc: 4691 mov r9, r2 8000cde: 2e00 cmp r6, #0 8000ce0: d042 beq.n 8000d68 <__aeabi_fsub+0x100> 8000ce2: 428c cmp r4, r1 8000ce4: d055 beq.n 8000d92 <__aeabi_fsub+0x12a> 8000ce6: 464a mov r2, r9 8000ce8: 2a00 cmp r2, #0 8000cea: d100 bne.n 8000cee <__aeabi_fsub+0x86> 8000cec: e09c b.n 8000e28 <__aeabi_fsub+0x1c0> 8000cee: 2d00 cmp r5, #0 8000cf0: d100 bne.n 8000cf4 <__aeabi_fsub+0x8c> 8000cf2: e077 b.n 8000de4 <__aeabi_fsub+0x17c> 8000cf4: 000c movs r4, r1 8000cf6: 0033 movs r3, r6 8000cf8: 08db lsrs r3, r3, #3 8000cfa: 2b00 cmp r3, #0 8000cfc: d100 bne.n 8000d00 <__aeabi_fsub+0x98> 8000cfe: e06e b.n 8000dde <__aeabi_fsub+0x176> 8000d00: 2280 movs r2, #128 @ 0x80 8000d02: 03d2 lsls r2, r2, #15 8000d04: 4313 orrs r3, r2 8000d06: 025b lsls r3, r3, #9 8000d08: 20ff movs r0, #255 @ 0xff 8000d0a: 0a5b lsrs r3, r3, #9 8000d0c: e024 b.n 8000d58 <__aeabi_fsub+0xf0> 8000d0e: 2dff cmp r5, #255 @ 0xff 8000d10: d0f2 beq.n 8000cf8 <__aeabi_fsub+0x90> 8000d12: 2180 movs r1, #128 @ 0x80 8000d14: 04c9 lsls r1, r1, #19 8000d16: 430e orrs r6, r1 8000d18: 2101 movs r1, #1 8000d1a: 2a1b cmp r2, #27 8000d1c: dc08 bgt.n 8000d30 <__aeabi_fsub+0xc8> 8000d1e: 0031 movs r1, r6 8000d20: 2020 movs r0, #32 8000d22: 40d1 lsrs r1, r2 8000d24: 1a82 subs r2, r0, r2 8000d26: 4096 lsls r6, r2 8000d28: 0032 movs r2, r6 8000d2a: 1e50 subs r0, r2, #1 8000d2c: 4182 sbcs r2, r0 8000d2e: 4311 orrs r1, r2 8000d30: 1a5b subs r3, r3, r1 8000d32: 015a lsls r2, r3, #5 8000d34: d460 bmi.n 8000df8 <__aeabi_fsub+0x190> 8000d36: 2107 movs r1, #7 8000d38: 002a movs r2, r5 8000d3a: 4019 ands r1, r3 8000d3c: d057 beq.n 8000dee <__aeabi_fsub+0x186> 8000d3e: 210f movs r1, #15 8000d40: 4019 ands r1, r3 8000d42: 2904 cmp r1, #4 8000d44: d000 beq.n 8000d48 <__aeabi_fsub+0xe0> 8000d46: 3304 adds r3, #4 8000d48: 0159 lsls r1, r3, #5 8000d4a: d550 bpl.n 8000dee <__aeabi_fsub+0x186> 8000d4c: 1c50 adds r0, r2, #1 8000d4e: 2afe cmp r2, #254 @ 0xfe 8000d50: d045 beq.n 8000dde <__aeabi_fsub+0x176> 8000d52: 019b lsls r3, r3, #6 8000d54: b2c0 uxtb r0, r0 8000d56: 0a5b lsrs r3, r3, #9 8000d58: 05c0 lsls r0, r0, #23 8000d5a: 4318 orrs r0, r3 8000d5c: 07e4 lsls r4, r4, #31 8000d5e: 4320 orrs r0, r4 8000d60: bcc0 pop {r6, r7} 8000d62: 46b9 mov r9, r7 8000d64: 46b0 mov r8, r6 8000d66: bdf8 pop {r3, r4, r5, r6, r7, pc} 8000d68: 2201 movs r2, #1 8000d6a: 4051 eors r1, r2 8000d6c: 428c cmp r4, r1 8000d6e: d1ba bne.n 8000ce6 <__aeabi_fsub+0x7e> 8000d70: 464a mov r2, r9 8000d72: 2a00 cmp r2, #0 8000d74: d010 beq.n 8000d98 <__aeabi_fsub+0x130> 8000d76: 2d00 cmp r5, #0 8000d78: d100 bne.n 8000d7c <__aeabi_fsub+0x114> 8000d7a: e098 b.n 8000eae <__aeabi_fsub+0x246> 8000d7c: 2300 movs r3, #0 8000d7e: e7bb b.n 8000cf8 <__aeabi_fsub+0x90> 8000d80: 2e00 cmp r6, #0 8000d82: d034 beq.n 8000dee <__aeabi_fsub+0x186> 8000d84: 1e51 subs r1, r2, #1 8000d86: 2a01 cmp r2, #1 8000d88: d06e beq.n 8000e68 <__aeabi_fsub+0x200> 8000d8a: 2aff cmp r2, #255 @ 0xff 8000d8c: d0b4 beq.n 8000cf8 <__aeabi_fsub+0x90> 8000d8e: 000a movs r2, r1 8000d90: e79c b.n 8000ccc <__aeabi_fsub+0x64> 8000d92: 2a00 cmp r2, #0 8000d94: d000 beq.n 8000d98 <__aeabi_fsub+0x130> 8000d96: e088 b.n 8000eaa <__aeabi_fsub+0x242> 8000d98: 20fe movs r0, #254 @ 0xfe 8000d9a: 1c6a adds r2, r5, #1 8000d9c: 4210 tst r0, r2 8000d9e: d000 beq.n 8000da2 <__aeabi_fsub+0x13a> 8000da0: e092 b.n 8000ec8 <__aeabi_fsub+0x260> 8000da2: 2d00 cmp r5, #0 8000da4: d000 beq.n 8000da8 <__aeabi_fsub+0x140> 8000da6: e0a4 b.n 8000ef2 <__aeabi_fsub+0x28a> 8000da8: 2b00 cmp r3, #0 8000daa: d100 bne.n 8000dae <__aeabi_fsub+0x146> 8000dac: e0cb b.n 8000f46 <__aeabi_fsub+0x2de> 8000dae: 2e00 cmp r6, #0 8000db0: d000 beq.n 8000db4 <__aeabi_fsub+0x14c> 8000db2: e0ca b.n 8000f4a <__aeabi_fsub+0x2e2> 8000db4: 2200 movs r2, #0 8000db6: 08db lsrs r3, r3, #3 8000db8: 025b lsls r3, r3, #9 8000dba: 0a5b lsrs r3, r3, #9 8000dbc: b2d0 uxtb r0, r2 8000dbe: e7cb b.n 8000d58 <__aeabi_fsub+0xf0> 8000dc0: 0031 movs r1, r6 8000dc2: 2020 movs r0, #32 8000dc4: 40d1 lsrs r1, r2 8000dc6: 1a82 subs r2, r0, r2 8000dc8: 4096 lsls r6, r2 8000dca: 0032 movs r2, r6 8000dcc: 1e50 subs r0, r2, #1 8000dce: 4182 sbcs r2, r0 8000dd0: 430a orrs r2, r1 8000dd2: 189b adds r3, r3, r2 8000dd4: 015a lsls r2, r3, #5 8000dd6: d5ae bpl.n 8000d36 <__aeabi_fsub+0xce> 8000dd8: 1c6a adds r2, r5, #1 8000dda: 2dfe cmp r5, #254 @ 0xfe 8000ddc: d14a bne.n 8000e74 <__aeabi_fsub+0x20c> 8000dde: 20ff movs r0, #255 @ 0xff 8000de0: 2300 movs r3, #0 8000de2: e7b9 b.n 8000d58 <__aeabi_fsub+0xf0> 8000de4: 22ff movs r2, #255 @ 0xff 8000de6: 2b00 cmp r3, #0 8000de8: d14b bne.n 8000e82 <__aeabi_fsub+0x21a> 8000dea: 000c movs r4, r1 8000dec: 0033 movs r3, r6 8000dee: 08db lsrs r3, r3, #3 8000df0: 2aff cmp r2, #255 @ 0xff 8000df2: d100 bne.n 8000df6 <__aeabi_fsub+0x18e> 8000df4: e781 b.n 8000cfa <__aeabi_fsub+0x92> 8000df6: e7df b.n 8000db8 <__aeabi_fsub+0x150> 8000df8: 019f lsls r7, r3, #6 8000dfa: 09bf lsrs r7, r7, #6 8000dfc: 0038 movs r0, r7 8000dfe: f002 f81d bl 8002e3c <__clzsi2> 8000e02: 3805 subs r0, #5 8000e04: 4087 lsls r7, r0 8000e06: 4285 cmp r5, r0 8000e08: dc21 bgt.n 8000e4e <__aeabi_fsub+0x1e6> 8000e0a: 003b movs r3, r7 8000e0c: 2120 movs r1, #32 8000e0e: 1b42 subs r2, r0, r5 8000e10: 3201 adds r2, #1 8000e12: 40d3 lsrs r3, r2 8000e14: 1a8a subs r2, r1, r2 8000e16: 4097 lsls r7, r2 8000e18: 1e7a subs r2, r7, #1 8000e1a: 4197 sbcs r7, r2 8000e1c: 2200 movs r2, #0 8000e1e: 433b orrs r3, r7 8000e20: 0759 lsls r1, r3, #29 8000e22: d000 beq.n 8000e26 <__aeabi_fsub+0x1be> 8000e24: e78b b.n 8000d3e <__aeabi_fsub+0xd6> 8000e26: e78f b.n 8000d48 <__aeabi_fsub+0xe0> 8000e28: 20fe movs r0, #254 @ 0xfe 8000e2a: 1c6a adds r2, r5, #1 8000e2c: 4210 tst r0, r2 8000e2e: d112 bne.n 8000e56 <__aeabi_fsub+0x1ee> 8000e30: 2d00 cmp r5, #0 8000e32: d152 bne.n 8000eda <__aeabi_fsub+0x272> 8000e34: 2b00 cmp r3, #0 8000e36: d07c beq.n 8000f32 <__aeabi_fsub+0x2ca> 8000e38: 2e00 cmp r6, #0 8000e3a: d0bb beq.n 8000db4 <__aeabi_fsub+0x14c> 8000e3c: 1b9a subs r2, r3, r6 8000e3e: 0150 lsls r0, r2, #5 8000e40: d400 bmi.n 8000e44 <__aeabi_fsub+0x1dc> 8000e42: e08b b.n 8000f5c <__aeabi_fsub+0x2f4> 8000e44: 2401 movs r4, #1 8000e46: 2200 movs r2, #0 8000e48: 1af3 subs r3, r6, r3 8000e4a: 400c ands r4, r1 8000e4c: e7e8 b.n 8000e20 <__aeabi_fsub+0x1b8> 8000e4e: 4b56 ldr r3, [pc, #344] @ (8000fa8 <__aeabi_fsub+0x340>) 8000e50: 1a2a subs r2, r5, r0 8000e52: 403b ands r3, r7 8000e54: e7e4 b.n 8000e20 <__aeabi_fsub+0x1b8> 8000e56: 1b9f subs r7, r3, r6 8000e58: 017a lsls r2, r7, #5 8000e5a: d446 bmi.n 8000eea <__aeabi_fsub+0x282> 8000e5c: 2f00 cmp r7, #0 8000e5e: d1cd bne.n 8000dfc <__aeabi_fsub+0x194> 8000e60: 2400 movs r4, #0 8000e62: 2000 movs r0, #0 8000e64: 2300 movs r3, #0 8000e66: e777 b.n 8000d58 <__aeabi_fsub+0xf0> 8000e68: 199b adds r3, r3, r6 8000e6a: 2501 movs r5, #1 8000e6c: 3201 adds r2, #1 8000e6e: 0159 lsls r1, r3, #5 8000e70: d400 bmi.n 8000e74 <__aeabi_fsub+0x20c> 8000e72: e760 b.n 8000d36 <__aeabi_fsub+0xce> 8000e74: 2101 movs r1, #1 8000e76: 484d ldr r0, [pc, #308] @ (8000fac <__aeabi_fsub+0x344>) 8000e78: 4019 ands r1, r3 8000e7a: 085b lsrs r3, r3, #1 8000e7c: 4003 ands r3, r0 8000e7e: 430b orrs r3, r1 8000e80: e7ce b.n 8000e20 <__aeabi_fsub+0x1b8> 8000e82: 1e57 subs r7, r2, #1 8000e84: 2a01 cmp r2, #1 8000e86: d05a beq.n 8000f3e <__aeabi_fsub+0x2d6> 8000e88: 000c movs r4, r1 8000e8a: 2aff cmp r2, #255 @ 0xff 8000e8c: d033 beq.n 8000ef6 <__aeabi_fsub+0x28e> 8000e8e: 2201 movs r2, #1 8000e90: 2f1b cmp r7, #27 8000e92: dc07 bgt.n 8000ea4 <__aeabi_fsub+0x23c> 8000e94: 2120 movs r1, #32 8000e96: 1bc9 subs r1, r1, r7 8000e98: 001a movs r2, r3 8000e9a: 408b lsls r3, r1 8000e9c: 40fa lsrs r2, r7 8000e9e: 1e59 subs r1, r3, #1 8000ea0: 418b sbcs r3, r1 8000ea2: 431a orrs r2, r3 8000ea4: 0005 movs r5, r0 8000ea6: 1ab3 subs r3, r6, r2 8000ea8: e743 b.n 8000d32 <__aeabi_fsub+0xca> 8000eaa: 2d00 cmp r5, #0 8000eac: d123 bne.n 8000ef6 <__aeabi_fsub+0x28e> 8000eae: 22ff movs r2, #255 @ 0xff 8000eb0: 2b00 cmp r3, #0 8000eb2: d09b beq.n 8000dec <__aeabi_fsub+0x184> 8000eb4: 1e51 subs r1, r2, #1 8000eb6: 2a01 cmp r2, #1 8000eb8: d0d6 beq.n 8000e68 <__aeabi_fsub+0x200> 8000eba: 2aff cmp r2, #255 @ 0xff 8000ebc: d01b beq.n 8000ef6 <__aeabi_fsub+0x28e> 8000ebe: 291b cmp r1, #27 8000ec0: dd2c ble.n 8000f1c <__aeabi_fsub+0x2b4> 8000ec2: 0002 movs r2, r0 8000ec4: 1c73 adds r3, r6, #1 8000ec6: e73a b.n 8000d3e <__aeabi_fsub+0xd6> 8000ec8: 2aff cmp r2, #255 @ 0xff 8000eca: d088 beq.n 8000dde <__aeabi_fsub+0x176> 8000ecc: 199b adds r3, r3, r6 8000ece: 085b lsrs r3, r3, #1 8000ed0: 0759 lsls r1, r3, #29 8000ed2: d000 beq.n 8000ed6 <__aeabi_fsub+0x26e> 8000ed4: e733 b.n 8000d3e <__aeabi_fsub+0xd6> 8000ed6: 08db lsrs r3, r3, #3 8000ed8: e76e b.n 8000db8 <__aeabi_fsub+0x150> 8000eda: 2b00 cmp r3, #0 8000edc: d110 bne.n 8000f00 <__aeabi_fsub+0x298> 8000ede: 2e00 cmp r6, #0 8000ee0: d043 beq.n 8000f6a <__aeabi_fsub+0x302> 8000ee2: 2401 movs r4, #1 8000ee4: 0033 movs r3, r6 8000ee6: 400c ands r4, r1 8000ee8: e706 b.n 8000cf8 <__aeabi_fsub+0x90> 8000eea: 2401 movs r4, #1 8000eec: 1af7 subs r7, r6, r3 8000eee: 400c ands r4, r1 8000ef0: e784 b.n 8000dfc <__aeabi_fsub+0x194> 8000ef2: 2b00 cmp r3, #0 8000ef4: d104 bne.n 8000f00 <__aeabi_fsub+0x298> 8000ef6: 0033 movs r3, r6 8000ef8: e6fe b.n 8000cf8 <__aeabi_fsub+0x90> 8000efa: 2501 movs r5, #1 8000efc: 1b9b subs r3, r3, r6 8000efe: e718 b.n 8000d32 <__aeabi_fsub+0xca> 8000f00: 2e00 cmp r6, #0 8000f02: d100 bne.n 8000f06 <__aeabi_fsub+0x29e> 8000f04: e6f8 b.n 8000cf8 <__aeabi_fsub+0x90> 8000f06: 2280 movs r2, #128 @ 0x80 8000f08: 03d2 lsls r2, r2, #15 8000f0a: 4297 cmp r7, r2 8000f0c: d304 bcc.n 8000f18 <__aeabi_fsub+0x2b0> 8000f0e: 4594 cmp ip, r2 8000f10: d202 bcs.n 8000f18 <__aeabi_fsub+0x2b0> 8000f12: 2401 movs r4, #1 8000f14: 0033 movs r3, r6 8000f16: 400c ands r4, r1 8000f18: 08db lsrs r3, r3, #3 8000f1a: e6f1 b.n 8000d00 <__aeabi_fsub+0x98> 8000f1c: 001a movs r2, r3 8000f1e: 2520 movs r5, #32 8000f20: 40ca lsrs r2, r1 8000f22: 1a69 subs r1, r5, r1 8000f24: 408b lsls r3, r1 8000f26: 1e59 subs r1, r3, #1 8000f28: 418b sbcs r3, r1 8000f2a: 4313 orrs r3, r2 8000f2c: 0005 movs r5, r0 8000f2e: 199b adds r3, r3, r6 8000f30: e750 b.n 8000dd4 <__aeabi_fsub+0x16c> 8000f32: 2e00 cmp r6, #0 8000f34: d094 beq.n 8000e60 <__aeabi_fsub+0x1f8> 8000f36: 2401 movs r4, #1 8000f38: 0033 movs r3, r6 8000f3a: 400c ands r4, r1 8000f3c: e73a b.n 8000db4 <__aeabi_fsub+0x14c> 8000f3e: 000c movs r4, r1 8000f40: 2501 movs r5, #1 8000f42: 1af3 subs r3, r6, r3 8000f44: e6f5 b.n 8000d32 <__aeabi_fsub+0xca> 8000f46: 0033 movs r3, r6 8000f48: e734 b.n 8000db4 <__aeabi_fsub+0x14c> 8000f4a: 199b adds r3, r3, r6 8000f4c: 2200 movs r2, #0 8000f4e: 0159 lsls r1, r3, #5 8000f50: d5c1 bpl.n 8000ed6 <__aeabi_fsub+0x26e> 8000f52: 4a15 ldr r2, [pc, #84] @ (8000fa8 <__aeabi_fsub+0x340>) 8000f54: 4013 ands r3, r2 8000f56: 08db lsrs r3, r3, #3 8000f58: 2201 movs r2, #1 8000f5a: e72d b.n 8000db8 <__aeabi_fsub+0x150> 8000f5c: 2a00 cmp r2, #0 8000f5e: d100 bne.n 8000f62 <__aeabi_fsub+0x2fa> 8000f60: e77e b.n 8000e60 <__aeabi_fsub+0x1f8> 8000f62: 0013 movs r3, r2 8000f64: 2200 movs r2, #0 8000f66: 08db lsrs r3, r3, #3 8000f68: e726 b.n 8000db8 <__aeabi_fsub+0x150> 8000f6a: 2380 movs r3, #128 @ 0x80 8000f6c: 2400 movs r4, #0 8000f6e: 20ff movs r0, #255 @ 0xff 8000f70: 03db lsls r3, r3, #15 8000f72: e6f1 b.n 8000d58 <__aeabi_fsub+0xf0> 8000f74: 2a00 cmp r2, #0 8000f76: d100 bne.n 8000f7a <__aeabi_fsub+0x312> 8000f78: e756 b.n 8000e28 <__aeabi_fsub+0x1c0> 8000f7a: 1b47 subs r7, r0, r5 8000f7c: 003a movs r2, r7 8000f7e: 2d00 cmp r5, #0 8000f80: d100 bne.n 8000f84 <__aeabi_fsub+0x31c> 8000f82: e730 b.n 8000de6 <__aeabi_fsub+0x17e> 8000f84: 2280 movs r2, #128 @ 0x80 8000f86: 04d2 lsls r2, r2, #19 8000f88: 000c movs r4, r1 8000f8a: 4313 orrs r3, r2 8000f8c: e77f b.n 8000e8e <__aeabi_fsub+0x226> 8000f8e: 2a00 cmp r2, #0 8000f90: d100 bne.n 8000f94 <__aeabi_fsub+0x32c> 8000f92: e701 b.n 8000d98 <__aeabi_fsub+0x130> 8000f94: 1b41 subs r1, r0, r5 8000f96: 2d00 cmp r5, #0 8000f98: d101 bne.n 8000f9e <__aeabi_fsub+0x336> 8000f9a: 000a movs r2, r1 8000f9c: e788 b.n 8000eb0 <__aeabi_fsub+0x248> 8000f9e: 2280 movs r2, #128 @ 0x80 8000fa0: 04d2 lsls r2, r2, #19 8000fa2: 4313 orrs r3, r2 8000fa4: e78b b.n 8000ebe <__aeabi_fsub+0x256> 8000fa6: 46c0 nop @ (mov r8, r8) 8000fa8: fbffffff .word 0xfbffffff 8000fac: 7dffffff .word 0x7dffffff 08000fb0 <__aeabi_i2f>: 8000fb0: b570 push {r4, r5, r6, lr} 8000fb2: 2800 cmp r0, #0 8000fb4: d013 beq.n 8000fde <__aeabi_i2f+0x2e> 8000fb6: 17c3 asrs r3, r0, #31 8000fb8: 18c5 adds r5, r0, r3 8000fba: 405d eors r5, r3 8000fbc: 0fc4 lsrs r4, r0, #31 8000fbe: 0028 movs r0, r5 8000fc0: f001 ff3c bl 8002e3c <__clzsi2> 8000fc4: 239e movs r3, #158 @ 0x9e 8000fc6: 0001 movs r1, r0 8000fc8: 1a1b subs r3, r3, r0 8000fca: 2b96 cmp r3, #150 @ 0x96 8000fcc: dc0f bgt.n 8000fee <__aeabi_i2f+0x3e> 8000fce: 2808 cmp r0, #8 8000fd0: d034 beq.n 800103c <__aeabi_i2f+0x8c> 8000fd2: 3908 subs r1, #8 8000fd4: 408d lsls r5, r1 8000fd6: 026d lsls r5, r5, #9 8000fd8: 0a6d lsrs r5, r5, #9 8000fda: b2d8 uxtb r0, r3 8000fdc: e002 b.n 8000fe4 <__aeabi_i2f+0x34> 8000fde: 2400 movs r4, #0 8000fe0: 2000 movs r0, #0 8000fe2: 2500 movs r5, #0 8000fe4: 05c0 lsls r0, r0, #23 8000fe6: 4328 orrs r0, r5 8000fe8: 07e4 lsls r4, r4, #31 8000fea: 4320 orrs r0, r4 8000fec: bd70 pop {r4, r5, r6, pc} 8000fee: 2b99 cmp r3, #153 @ 0x99 8000ff0: dc16 bgt.n 8001020 <__aeabi_i2f+0x70> 8000ff2: 1f42 subs r2, r0, #5 8000ff4: 2805 cmp r0, #5 8000ff6: d000 beq.n 8000ffa <__aeabi_i2f+0x4a> 8000ff8: 4095 lsls r5, r2 8000ffa: 002a movs r2, r5 8000ffc: 4811 ldr r0, [pc, #68] @ (8001044 <__aeabi_i2f+0x94>) 8000ffe: 4002 ands r2, r0 8001000: 076e lsls r6, r5, #29 8001002: d009 beq.n 8001018 <__aeabi_i2f+0x68> 8001004: 260f movs r6, #15 8001006: 4035 ands r5, r6 8001008: 2d04 cmp r5, #4 800100a: d005 beq.n 8001018 <__aeabi_i2f+0x68> 800100c: 3204 adds r2, #4 800100e: 0155 lsls r5, r2, #5 8001010: d502 bpl.n 8001018 <__aeabi_i2f+0x68> 8001012: 239f movs r3, #159 @ 0x9f 8001014: 4002 ands r2, r0 8001016: 1a5b subs r3, r3, r1 8001018: 0192 lsls r2, r2, #6 800101a: 0a55 lsrs r5, r2, #9 800101c: b2d8 uxtb r0, r3 800101e: e7e1 b.n 8000fe4 <__aeabi_i2f+0x34> 8001020: 2205 movs r2, #5 8001022: 1a12 subs r2, r2, r0 8001024: 0028 movs r0, r5 8001026: 40d0 lsrs r0, r2 8001028: 0002 movs r2, r0 800102a: 0008 movs r0, r1 800102c: 301b adds r0, #27 800102e: 4085 lsls r5, r0 8001030: 0028 movs r0, r5 8001032: 1e45 subs r5, r0, #1 8001034: 41a8 sbcs r0, r5 8001036: 4302 orrs r2, r0 8001038: 0015 movs r5, r2 800103a: e7de b.n 8000ffa <__aeabi_i2f+0x4a> 800103c: 026d lsls r5, r5, #9 800103e: 2096 movs r0, #150 @ 0x96 8001040: 0a6d lsrs r5, r5, #9 8001042: e7cf b.n 8000fe4 <__aeabi_i2f+0x34> 8001044: fbffffff .word 0xfbffffff 08001048 <__aeabi_dadd>: 8001048: b5f0 push {r4, r5, r6, r7, lr} 800104a: 4657 mov r7, sl 800104c: 464e mov r6, r9 800104e: 4645 mov r5, r8 8001050: 46de mov lr, fp 8001052: b5e0 push {r5, r6, r7, lr} 8001054: b083 sub sp, #12 8001056: 9000 str r0, [sp, #0] 8001058: 9101 str r1, [sp, #4] 800105a: 030c lsls r4, r1, #12 800105c: 004f lsls r7, r1, #1 800105e: 0fce lsrs r6, r1, #31 8001060: 0a61 lsrs r1, r4, #9 8001062: 9c00 ldr r4, [sp, #0] 8001064: 031d lsls r5, r3, #12 8001066: 0f64 lsrs r4, r4, #29 8001068: 430c orrs r4, r1 800106a: 9900 ldr r1, [sp, #0] 800106c: 9200 str r2, [sp, #0] 800106e: 9301 str r3, [sp, #4] 8001070: 00c8 lsls r0, r1, #3 8001072: 0059 lsls r1, r3, #1 8001074: 0d4b lsrs r3, r1, #21 8001076: 4699 mov r9, r3 8001078: 9a00 ldr r2, [sp, #0] 800107a: 9b01 ldr r3, [sp, #4] 800107c: 0a6d lsrs r5, r5, #9 800107e: 0fd9 lsrs r1, r3, #31 8001080: 0f53 lsrs r3, r2, #29 8001082: 432b orrs r3, r5 8001084: 469a mov sl, r3 8001086: 9b00 ldr r3, [sp, #0] 8001088: 0d7f lsrs r7, r7, #21 800108a: 00da lsls r2, r3, #3 800108c: 4694 mov ip, r2 800108e: 464a mov r2, r9 8001090: 46b0 mov r8, r6 8001092: 1aba subs r2, r7, r2 8001094: 428e cmp r6, r1 8001096: d100 bne.n 800109a <__aeabi_dadd+0x52> 8001098: e0b0 b.n 80011fc <__aeabi_dadd+0x1b4> 800109a: 2a00 cmp r2, #0 800109c: dc00 bgt.n 80010a0 <__aeabi_dadd+0x58> 800109e: e078 b.n 8001192 <__aeabi_dadd+0x14a> 80010a0: 4649 mov r1, r9 80010a2: 2900 cmp r1, #0 80010a4: d100 bne.n 80010a8 <__aeabi_dadd+0x60> 80010a6: e0e9 b.n 800127c <__aeabi_dadd+0x234> 80010a8: 49c9 ldr r1, [pc, #804] @ (80013d0 <__aeabi_dadd+0x388>) 80010aa: 428f cmp r7, r1 80010ac: d100 bne.n 80010b0 <__aeabi_dadd+0x68> 80010ae: e195 b.n 80013dc <__aeabi_dadd+0x394> 80010b0: 2501 movs r5, #1 80010b2: 2a38 cmp r2, #56 @ 0x38 80010b4: dc16 bgt.n 80010e4 <__aeabi_dadd+0x9c> 80010b6: 2180 movs r1, #128 @ 0x80 80010b8: 4653 mov r3, sl 80010ba: 0409 lsls r1, r1, #16 80010bc: 430b orrs r3, r1 80010be: 469a mov sl, r3 80010c0: 2a1f cmp r2, #31 80010c2: dd00 ble.n 80010c6 <__aeabi_dadd+0x7e> 80010c4: e1e7 b.n 8001496 <__aeabi_dadd+0x44e> 80010c6: 2120 movs r1, #32 80010c8: 4655 mov r5, sl 80010ca: 1a8b subs r3, r1, r2 80010cc: 4661 mov r1, ip 80010ce: 409d lsls r5, r3 80010d0: 40d1 lsrs r1, r2 80010d2: 430d orrs r5, r1 80010d4: 4661 mov r1, ip 80010d6: 4099 lsls r1, r3 80010d8: 1e4b subs r3, r1, #1 80010da: 4199 sbcs r1, r3 80010dc: 4653 mov r3, sl 80010de: 40d3 lsrs r3, r2 80010e0: 430d orrs r5, r1 80010e2: 1ae4 subs r4, r4, r3 80010e4: 1b45 subs r5, r0, r5 80010e6: 42a8 cmp r0, r5 80010e8: 4180 sbcs r0, r0 80010ea: 4240 negs r0, r0 80010ec: 1a24 subs r4, r4, r0 80010ee: 0223 lsls r3, r4, #8 80010f0: d400 bmi.n 80010f4 <__aeabi_dadd+0xac> 80010f2: e10f b.n 8001314 <__aeabi_dadd+0x2cc> 80010f4: 0264 lsls r4, r4, #9 80010f6: 0a64 lsrs r4, r4, #9 80010f8: 2c00 cmp r4, #0 80010fa: d100 bne.n 80010fe <__aeabi_dadd+0xb6> 80010fc: e139 b.n 8001372 <__aeabi_dadd+0x32a> 80010fe: 0020 movs r0, r4 8001100: f001 fe9c bl 8002e3c <__clzsi2> 8001104: 0003 movs r3, r0 8001106: 3b08 subs r3, #8 8001108: 2120 movs r1, #32 800110a: 0028 movs r0, r5 800110c: 1aca subs r2, r1, r3 800110e: 40d0 lsrs r0, r2 8001110: 409c lsls r4, r3 8001112: 0002 movs r2, r0 8001114: 409d lsls r5, r3 8001116: 4322 orrs r2, r4 8001118: 429f cmp r7, r3 800111a: dd00 ble.n 800111e <__aeabi_dadd+0xd6> 800111c: e173 b.n 8001406 <__aeabi_dadd+0x3be> 800111e: 1bd8 subs r0, r3, r7 8001120: 3001 adds r0, #1 8001122: 1a09 subs r1, r1, r0 8001124: 002c movs r4, r5 8001126: 408d lsls r5, r1 8001128: 40c4 lsrs r4, r0 800112a: 1e6b subs r3, r5, #1 800112c: 419d sbcs r5, r3 800112e: 0013 movs r3, r2 8001130: 40c2 lsrs r2, r0 8001132: 408b lsls r3, r1 8001134: 4325 orrs r5, r4 8001136: 2700 movs r7, #0 8001138: 0014 movs r4, r2 800113a: 431d orrs r5, r3 800113c: 076b lsls r3, r5, #29 800113e: d009 beq.n 8001154 <__aeabi_dadd+0x10c> 8001140: 230f movs r3, #15 8001142: 402b ands r3, r5 8001144: 2b04 cmp r3, #4 8001146: d005 beq.n 8001154 <__aeabi_dadd+0x10c> 8001148: 1d2b adds r3, r5, #4 800114a: 42ab cmp r3, r5 800114c: 41ad sbcs r5, r5 800114e: 426d negs r5, r5 8001150: 1964 adds r4, r4, r5 8001152: 001d movs r5, r3 8001154: 0223 lsls r3, r4, #8 8001156: d400 bmi.n 800115a <__aeabi_dadd+0x112> 8001158: e12d b.n 80013b6 <__aeabi_dadd+0x36e> 800115a: 4a9d ldr r2, [pc, #628] @ (80013d0 <__aeabi_dadd+0x388>) 800115c: 3701 adds r7, #1 800115e: 4297 cmp r7, r2 8001160: d100 bne.n 8001164 <__aeabi_dadd+0x11c> 8001162: e0d3 b.n 800130c <__aeabi_dadd+0x2c4> 8001164: 4646 mov r6, r8 8001166: 499b ldr r1, [pc, #620] @ (80013d4 <__aeabi_dadd+0x38c>) 8001168: 08ed lsrs r5, r5, #3 800116a: 4021 ands r1, r4 800116c: 074a lsls r2, r1, #29 800116e: 432a orrs r2, r5 8001170: 057c lsls r4, r7, #21 8001172: 024d lsls r5, r1, #9 8001174: 0b2d lsrs r5, r5, #12 8001176: 0d64 lsrs r4, r4, #21 8001178: 0524 lsls r4, r4, #20 800117a: 432c orrs r4, r5 800117c: 07f6 lsls r6, r6, #31 800117e: 4334 orrs r4, r6 8001180: 0010 movs r0, r2 8001182: 0021 movs r1, r4 8001184: b003 add sp, #12 8001186: bcf0 pop {r4, r5, r6, r7} 8001188: 46bb mov fp, r7 800118a: 46b2 mov sl, r6 800118c: 46a9 mov r9, r5 800118e: 46a0 mov r8, r4 8001190: bdf0 pop {r4, r5, r6, r7, pc} 8001192: 2a00 cmp r2, #0 8001194: d100 bne.n 8001198 <__aeabi_dadd+0x150> 8001196: e084 b.n 80012a2 <__aeabi_dadd+0x25a> 8001198: 464a mov r2, r9 800119a: 1bd2 subs r2, r2, r7 800119c: 2f00 cmp r7, #0 800119e: d000 beq.n 80011a2 <__aeabi_dadd+0x15a> 80011a0: e16d b.n 800147e <__aeabi_dadd+0x436> 80011a2: 0025 movs r5, r4 80011a4: 4305 orrs r5, r0 80011a6: d100 bne.n 80011aa <__aeabi_dadd+0x162> 80011a8: e127 b.n 80013fa <__aeabi_dadd+0x3b2> 80011aa: 1e56 subs r6, r2, #1 80011ac: 2a01 cmp r2, #1 80011ae: d100 bne.n 80011b2 <__aeabi_dadd+0x16a> 80011b0: e23b b.n 800162a <__aeabi_dadd+0x5e2> 80011b2: 4d87 ldr r5, [pc, #540] @ (80013d0 <__aeabi_dadd+0x388>) 80011b4: 42aa cmp r2, r5 80011b6: d100 bne.n 80011ba <__aeabi_dadd+0x172> 80011b8: e26a b.n 8001690 <__aeabi_dadd+0x648> 80011ba: 2501 movs r5, #1 80011bc: 2e38 cmp r6, #56 @ 0x38 80011be: dc12 bgt.n 80011e6 <__aeabi_dadd+0x19e> 80011c0: 0032 movs r2, r6 80011c2: 2a1f cmp r2, #31 80011c4: dd00 ble.n 80011c8 <__aeabi_dadd+0x180> 80011c6: e1f8 b.n 80015ba <__aeabi_dadd+0x572> 80011c8: 2620 movs r6, #32 80011ca: 0025 movs r5, r4 80011cc: 1ab6 subs r6, r6, r2 80011ce: 0007 movs r7, r0 80011d0: 4653 mov r3, sl 80011d2: 40b0 lsls r0, r6 80011d4: 40d4 lsrs r4, r2 80011d6: 40b5 lsls r5, r6 80011d8: 40d7 lsrs r7, r2 80011da: 1e46 subs r6, r0, #1 80011dc: 41b0 sbcs r0, r6 80011de: 1b1b subs r3, r3, r4 80011e0: 469a mov sl, r3 80011e2: 433d orrs r5, r7 80011e4: 4305 orrs r5, r0 80011e6: 4662 mov r2, ip 80011e8: 1b55 subs r5, r2, r5 80011ea: 45ac cmp ip, r5 80011ec: 4192 sbcs r2, r2 80011ee: 4653 mov r3, sl 80011f0: 4252 negs r2, r2 80011f2: 000e movs r6, r1 80011f4: 464f mov r7, r9 80011f6: 4688 mov r8, r1 80011f8: 1a9c subs r4, r3, r2 80011fa: e778 b.n 80010ee <__aeabi_dadd+0xa6> 80011fc: 2a00 cmp r2, #0 80011fe: dc00 bgt.n 8001202 <__aeabi_dadd+0x1ba> 8001200: e08e b.n 8001320 <__aeabi_dadd+0x2d8> 8001202: 4649 mov r1, r9 8001204: 2900 cmp r1, #0 8001206: d175 bne.n 80012f4 <__aeabi_dadd+0x2ac> 8001208: 4661 mov r1, ip 800120a: 4653 mov r3, sl 800120c: 4319 orrs r1, r3 800120e: d100 bne.n 8001212 <__aeabi_dadd+0x1ca> 8001210: e0f6 b.n 8001400 <__aeabi_dadd+0x3b8> 8001212: 1e51 subs r1, r2, #1 8001214: 2a01 cmp r2, #1 8001216: d100 bne.n 800121a <__aeabi_dadd+0x1d2> 8001218: e191 b.n 800153e <__aeabi_dadd+0x4f6> 800121a: 4d6d ldr r5, [pc, #436] @ (80013d0 <__aeabi_dadd+0x388>) 800121c: 42aa cmp r2, r5 800121e: d100 bne.n 8001222 <__aeabi_dadd+0x1da> 8001220: e0dc b.n 80013dc <__aeabi_dadd+0x394> 8001222: 2501 movs r5, #1 8001224: 2938 cmp r1, #56 @ 0x38 8001226: dc14 bgt.n 8001252 <__aeabi_dadd+0x20a> 8001228: 000a movs r2, r1 800122a: 2a1f cmp r2, #31 800122c: dd00 ble.n 8001230 <__aeabi_dadd+0x1e8> 800122e: e1a2 b.n 8001576 <__aeabi_dadd+0x52e> 8001230: 2120 movs r1, #32 8001232: 4653 mov r3, sl 8001234: 1a89 subs r1, r1, r2 8001236: 408b lsls r3, r1 8001238: 001d movs r5, r3 800123a: 4663 mov r3, ip 800123c: 40d3 lsrs r3, r2 800123e: 431d orrs r5, r3 8001240: 4663 mov r3, ip 8001242: 408b lsls r3, r1 8001244: 0019 movs r1, r3 8001246: 1e4b subs r3, r1, #1 8001248: 4199 sbcs r1, r3 800124a: 4653 mov r3, sl 800124c: 40d3 lsrs r3, r2 800124e: 430d orrs r5, r1 8001250: 18e4 adds r4, r4, r3 8001252: 182d adds r5, r5, r0 8001254: 4285 cmp r5, r0 8001256: 4180 sbcs r0, r0 8001258: 4240 negs r0, r0 800125a: 1824 adds r4, r4, r0 800125c: 0223 lsls r3, r4, #8 800125e: d559 bpl.n 8001314 <__aeabi_dadd+0x2cc> 8001260: 4b5b ldr r3, [pc, #364] @ (80013d0 <__aeabi_dadd+0x388>) 8001262: 3701 adds r7, #1 8001264: 429f cmp r7, r3 8001266: d051 beq.n 800130c <__aeabi_dadd+0x2c4> 8001268: 2101 movs r1, #1 800126a: 4b5a ldr r3, [pc, #360] @ (80013d4 <__aeabi_dadd+0x38c>) 800126c: 086a lsrs r2, r5, #1 800126e: 401c ands r4, r3 8001270: 4029 ands r1, r5 8001272: 430a orrs r2, r1 8001274: 07e5 lsls r5, r4, #31 8001276: 4315 orrs r5, r2 8001278: 0864 lsrs r4, r4, #1 800127a: e75f b.n 800113c <__aeabi_dadd+0xf4> 800127c: 4661 mov r1, ip 800127e: 4653 mov r3, sl 8001280: 4319 orrs r1, r3 8001282: d100 bne.n 8001286 <__aeabi_dadd+0x23e> 8001284: e0bc b.n 8001400 <__aeabi_dadd+0x3b8> 8001286: 1e51 subs r1, r2, #1 8001288: 2a01 cmp r2, #1 800128a: d100 bne.n 800128e <__aeabi_dadd+0x246> 800128c: e164 b.n 8001558 <__aeabi_dadd+0x510> 800128e: 4d50 ldr r5, [pc, #320] @ (80013d0 <__aeabi_dadd+0x388>) 8001290: 42aa cmp r2, r5 8001292: d100 bne.n 8001296 <__aeabi_dadd+0x24e> 8001294: e16a b.n 800156c <__aeabi_dadd+0x524> 8001296: 2501 movs r5, #1 8001298: 2938 cmp r1, #56 @ 0x38 800129a: dd00 ble.n 800129e <__aeabi_dadd+0x256> 800129c: e722 b.n 80010e4 <__aeabi_dadd+0x9c> 800129e: 000a movs r2, r1 80012a0: e70e b.n 80010c0 <__aeabi_dadd+0x78> 80012a2: 4a4d ldr r2, [pc, #308] @ (80013d8 <__aeabi_dadd+0x390>) 80012a4: 1c7d adds r5, r7, #1 80012a6: 4215 tst r5, r2 80012a8: d000 beq.n 80012ac <__aeabi_dadd+0x264> 80012aa: e0d0 b.n 800144e <__aeabi_dadd+0x406> 80012ac: 0025 movs r5, r4 80012ae: 4662 mov r2, ip 80012b0: 4653 mov r3, sl 80012b2: 4305 orrs r5, r0 80012b4: 431a orrs r2, r3 80012b6: 2f00 cmp r7, #0 80012b8: d000 beq.n 80012bc <__aeabi_dadd+0x274> 80012ba: e137 b.n 800152c <__aeabi_dadd+0x4e4> 80012bc: 2d00 cmp r5, #0 80012be: d100 bne.n 80012c2 <__aeabi_dadd+0x27a> 80012c0: e1a8 b.n 8001614 <__aeabi_dadd+0x5cc> 80012c2: 2a00 cmp r2, #0 80012c4: d100 bne.n 80012c8 <__aeabi_dadd+0x280> 80012c6: e16a b.n 800159e <__aeabi_dadd+0x556> 80012c8: 4663 mov r3, ip 80012ca: 1ac5 subs r5, r0, r3 80012cc: 4653 mov r3, sl 80012ce: 1ae2 subs r2, r4, r3 80012d0: 42a8 cmp r0, r5 80012d2: 419b sbcs r3, r3 80012d4: 425b negs r3, r3 80012d6: 1ad3 subs r3, r2, r3 80012d8: 021a lsls r2, r3, #8 80012da: d400 bmi.n 80012de <__aeabi_dadd+0x296> 80012dc: e203 b.n 80016e6 <__aeabi_dadd+0x69e> 80012de: 4663 mov r3, ip 80012e0: 1a1d subs r5, r3, r0 80012e2: 45ac cmp ip, r5 80012e4: 4192 sbcs r2, r2 80012e6: 4653 mov r3, sl 80012e8: 4252 negs r2, r2 80012ea: 1b1c subs r4, r3, r4 80012ec: 000e movs r6, r1 80012ee: 4688 mov r8, r1 80012f0: 1aa4 subs r4, r4, r2 80012f2: e723 b.n 800113c <__aeabi_dadd+0xf4> 80012f4: 4936 ldr r1, [pc, #216] @ (80013d0 <__aeabi_dadd+0x388>) 80012f6: 428f cmp r7, r1 80012f8: d070 beq.n 80013dc <__aeabi_dadd+0x394> 80012fa: 2501 movs r5, #1 80012fc: 2a38 cmp r2, #56 @ 0x38 80012fe: dca8 bgt.n 8001252 <__aeabi_dadd+0x20a> 8001300: 2180 movs r1, #128 @ 0x80 8001302: 4653 mov r3, sl 8001304: 0409 lsls r1, r1, #16 8001306: 430b orrs r3, r1 8001308: 469a mov sl, r3 800130a: e78e b.n 800122a <__aeabi_dadd+0x1e2> 800130c: 003c movs r4, r7 800130e: 2500 movs r5, #0 8001310: 2200 movs r2, #0 8001312: e731 b.n 8001178 <__aeabi_dadd+0x130> 8001314: 2307 movs r3, #7 8001316: 402b ands r3, r5 8001318: 2b00 cmp r3, #0 800131a: d000 beq.n 800131e <__aeabi_dadd+0x2d6> 800131c: e710 b.n 8001140 <__aeabi_dadd+0xf8> 800131e: e093 b.n 8001448 <__aeabi_dadd+0x400> 8001320: 2a00 cmp r2, #0 8001322: d074 beq.n 800140e <__aeabi_dadd+0x3c6> 8001324: 464a mov r2, r9 8001326: 1bd2 subs r2, r2, r7 8001328: 2f00 cmp r7, #0 800132a: d100 bne.n 800132e <__aeabi_dadd+0x2e6> 800132c: e0c7 b.n 80014be <__aeabi_dadd+0x476> 800132e: 4928 ldr r1, [pc, #160] @ (80013d0 <__aeabi_dadd+0x388>) 8001330: 4589 cmp r9, r1 8001332: d100 bne.n 8001336 <__aeabi_dadd+0x2ee> 8001334: e185 b.n 8001642 <__aeabi_dadd+0x5fa> 8001336: 2501 movs r5, #1 8001338: 2a38 cmp r2, #56 @ 0x38 800133a: dc12 bgt.n 8001362 <__aeabi_dadd+0x31a> 800133c: 2180 movs r1, #128 @ 0x80 800133e: 0409 lsls r1, r1, #16 8001340: 430c orrs r4, r1 8001342: 2a1f cmp r2, #31 8001344: dd00 ble.n 8001348 <__aeabi_dadd+0x300> 8001346: e1ab b.n 80016a0 <__aeabi_dadd+0x658> 8001348: 2120 movs r1, #32 800134a: 0025 movs r5, r4 800134c: 1a89 subs r1, r1, r2 800134e: 0007 movs r7, r0 8001350: 4088 lsls r0, r1 8001352: 408d lsls r5, r1 8001354: 40d7 lsrs r7, r2 8001356: 1e41 subs r1, r0, #1 8001358: 4188 sbcs r0, r1 800135a: 40d4 lsrs r4, r2 800135c: 433d orrs r5, r7 800135e: 4305 orrs r5, r0 8001360: 44a2 add sl, r4 8001362: 4465 add r5, ip 8001364: 4565 cmp r5, ip 8001366: 4192 sbcs r2, r2 8001368: 4252 negs r2, r2 800136a: 4452 add r2, sl 800136c: 0014 movs r4, r2 800136e: 464f mov r7, r9 8001370: e774 b.n 800125c <__aeabi_dadd+0x214> 8001372: 0028 movs r0, r5 8001374: f001 fd62 bl 8002e3c <__clzsi2> 8001378: 0003 movs r3, r0 800137a: 3318 adds r3, #24 800137c: 2b1f cmp r3, #31 800137e: dc00 bgt.n 8001382 <__aeabi_dadd+0x33a> 8001380: e6c2 b.n 8001108 <__aeabi_dadd+0xc0> 8001382: 002a movs r2, r5 8001384: 3808 subs r0, #8 8001386: 4082 lsls r2, r0 8001388: 429f cmp r7, r3 800138a: dd00 ble.n 800138e <__aeabi_dadd+0x346> 800138c: e0a9 b.n 80014e2 <__aeabi_dadd+0x49a> 800138e: 1bdb subs r3, r3, r7 8001390: 1c58 adds r0, r3, #1 8001392: 281f cmp r0, #31 8001394: dc00 bgt.n 8001398 <__aeabi_dadd+0x350> 8001396: e1ac b.n 80016f2 <__aeabi_dadd+0x6aa> 8001398: 0015 movs r5, r2 800139a: 3b1f subs r3, #31 800139c: 40dd lsrs r5, r3 800139e: 2820 cmp r0, #32 80013a0: d005 beq.n 80013ae <__aeabi_dadd+0x366> 80013a2: 2340 movs r3, #64 @ 0x40 80013a4: 1a1b subs r3, r3, r0 80013a6: 409a lsls r2, r3 80013a8: 1e53 subs r3, r2, #1 80013aa: 419a sbcs r2, r3 80013ac: 4315 orrs r5, r2 80013ae: 2307 movs r3, #7 80013b0: 2700 movs r7, #0 80013b2: 402b ands r3, r5 80013b4: e7b0 b.n 8001318 <__aeabi_dadd+0x2d0> 80013b6: 08ed lsrs r5, r5, #3 80013b8: 4b05 ldr r3, [pc, #20] @ (80013d0 <__aeabi_dadd+0x388>) 80013ba: 0762 lsls r2, r4, #29 80013bc: 432a orrs r2, r5 80013be: 08e4 lsrs r4, r4, #3 80013c0: 429f cmp r7, r3 80013c2: d00f beq.n 80013e4 <__aeabi_dadd+0x39c> 80013c4: 0324 lsls r4, r4, #12 80013c6: 0b25 lsrs r5, r4, #12 80013c8: 057c lsls r4, r7, #21 80013ca: 0d64 lsrs r4, r4, #21 80013cc: e6d4 b.n 8001178 <__aeabi_dadd+0x130> 80013ce: 46c0 nop @ (mov r8, r8) 80013d0: 000007ff .word 0x000007ff 80013d4: ff7fffff .word 0xff7fffff 80013d8: 000007fe .word 0x000007fe 80013dc: 08c0 lsrs r0, r0, #3 80013de: 0762 lsls r2, r4, #29 80013e0: 4302 orrs r2, r0 80013e2: 08e4 lsrs r4, r4, #3 80013e4: 0013 movs r3, r2 80013e6: 4323 orrs r3, r4 80013e8: d100 bne.n 80013ec <__aeabi_dadd+0x3a4> 80013ea: e186 b.n 80016fa <__aeabi_dadd+0x6b2> 80013ec: 2580 movs r5, #128 @ 0x80 80013ee: 032d lsls r5, r5, #12 80013f0: 4325 orrs r5, r4 80013f2: 032d lsls r5, r5, #12 80013f4: 4cc3 ldr r4, [pc, #780] @ (8001704 <__aeabi_dadd+0x6bc>) 80013f6: 0b2d lsrs r5, r5, #12 80013f8: e6be b.n 8001178 <__aeabi_dadd+0x130> 80013fa: 4660 mov r0, ip 80013fc: 4654 mov r4, sl 80013fe: 000e movs r6, r1 8001400: 0017 movs r7, r2 8001402: 08c5 lsrs r5, r0, #3 8001404: e7d8 b.n 80013b8 <__aeabi_dadd+0x370> 8001406: 4cc0 ldr r4, [pc, #768] @ (8001708 <__aeabi_dadd+0x6c0>) 8001408: 1aff subs r7, r7, r3 800140a: 4014 ands r4, r2 800140c: e696 b.n 800113c <__aeabi_dadd+0xf4> 800140e: 4abf ldr r2, [pc, #764] @ (800170c <__aeabi_dadd+0x6c4>) 8001410: 1c79 adds r1, r7, #1 8001412: 4211 tst r1, r2 8001414: d16b bne.n 80014ee <__aeabi_dadd+0x4a6> 8001416: 0022 movs r2, r4 8001418: 4302 orrs r2, r0 800141a: 2f00 cmp r7, #0 800141c: d000 beq.n 8001420 <__aeabi_dadd+0x3d8> 800141e: e0db b.n 80015d8 <__aeabi_dadd+0x590> 8001420: 2a00 cmp r2, #0 8001422: d100 bne.n 8001426 <__aeabi_dadd+0x3de> 8001424: e12d b.n 8001682 <__aeabi_dadd+0x63a> 8001426: 4662 mov r2, ip 8001428: 4653 mov r3, sl 800142a: 431a orrs r2, r3 800142c: d100 bne.n 8001430 <__aeabi_dadd+0x3e8> 800142e: e0b6 b.n 800159e <__aeabi_dadd+0x556> 8001430: 4663 mov r3, ip 8001432: 18c5 adds r5, r0, r3 8001434: 4285 cmp r5, r0 8001436: 4180 sbcs r0, r0 8001438: 4454 add r4, sl 800143a: 4240 negs r0, r0 800143c: 1824 adds r4, r4, r0 800143e: 0223 lsls r3, r4, #8 8001440: d502 bpl.n 8001448 <__aeabi_dadd+0x400> 8001442: 000f movs r7, r1 8001444: 4bb0 ldr r3, [pc, #704] @ (8001708 <__aeabi_dadd+0x6c0>) 8001446: 401c ands r4, r3 8001448: 003a movs r2, r7 800144a: 0028 movs r0, r5 800144c: e7d8 b.n 8001400 <__aeabi_dadd+0x3b8> 800144e: 4662 mov r2, ip 8001450: 1a85 subs r5, r0, r2 8001452: 42a8 cmp r0, r5 8001454: 4192 sbcs r2, r2 8001456: 4653 mov r3, sl 8001458: 4252 negs r2, r2 800145a: 4691 mov r9, r2 800145c: 1ae3 subs r3, r4, r3 800145e: 001a movs r2, r3 8001460: 464b mov r3, r9 8001462: 1ad2 subs r2, r2, r3 8001464: 0013 movs r3, r2 8001466: 4691 mov r9, r2 8001468: 021a lsls r2, r3, #8 800146a: d454 bmi.n 8001516 <__aeabi_dadd+0x4ce> 800146c: 464a mov r2, r9 800146e: 464c mov r4, r9 8001470: 432a orrs r2, r5 8001472: d000 beq.n 8001476 <__aeabi_dadd+0x42e> 8001474: e640 b.n 80010f8 <__aeabi_dadd+0xb0> 8001476: 2600 movs r6, #0 8001478: 2400 movs r4, #0 800147a: 2500 movs r5, #0 800147c: e67c b.n 8001178 <__aeabi_dadd+0x130> 800147e: 4da1 ldr r5, [pc, #644] @ (8001704 <__aeabi_dadd+0x6bc>) 8001480: 45a9 cmp r9, r5 8001482: d100 bne.n 8001486 <__aeabi_dadd+0x43e> 8001484: e090 b.n 80015a8 <__aeabi_dadd+0x560> 8001486: 2501 movs r5, #1 8001488: 2a38 cmp r2, #56 @ 0x38 800148a: dd00 ble.n 800148e <__aeabi_dadd+0x446> 800148c: e6ab b.n 80011e6 <__aeabi_dadd+0x19e> 800148e: 2580 movs r5, #128 @ 0x80 8001490: 042d lsls r5, r5, #16 8001492: 432c orrs r4, r5 8001494: e695 b.n 80011c2 <__aeabi_dadd+0x17a> 8001496: 0011 movs r1, r2 8001498: 4655 mov r5, sl 800149a: 3920 subs r1, #32 800149c: 40cd lsrs r5, r1 800149e: 46a9 mov r9, r5 80014a0: 2a20 cmp r2, #32 80014a2: d006 beq.n 80014b2 <__aeabi_dadd+0x46a> 80014a4: 2140 movs r1, #64 @ 0x40 80014a6: 4653 mov r3, sl 80014a8: 1a8a subs r2, r1, r2 80014aa: 4093 lsls r3, r2 80014ac: 4662 mov r2, ip 80014ae: 431a orrs r2, r3 80014b0: 4694 mov ip, r2 80014b2: 4665 mov r5, ip 80014b4: 1e6b subs r3, r5, #1 80014b6: 419d sbcs r5, r3 80014b8: 464b mov r3, r9 80014ba: 431d orrs r5, r3 80014bc: e612 b.n 80010e4 <__aeabi_dadd+0x9c> 80014be: 0021 movs r1, r4 80014c0: 4301 orrs r1, r0 80014c2: d100 bne.n 80014c6 <__aeabi_dadd+0x47e> 80014c4: e0c4 b.n 8001650 <__aeabi_dadd+0x608> 80014c6: 1e51 subs r1, r2, #1 80014c8: 2a01 cmp r2, #1 80014ca: d100 bne.n 80014ce <__aeabi_dadd+0x486> 80014cc: e0fb b.n 80016c6 <__aeabi_dadd+0x67e> 80014ce: 4d8d ldr r5, [pc, #564] @ (8001704 <__aeabi_dadd+0x6bc>) 80014d0: 42aa cmp r2, r5 80014d2: d100 bne.n 80014d6 <__aeabi_dadd+0x48e> 80014d4: e0b5 b.n 8001642 <__aeabi_dadd+0x5fa> 80014d6: 2501 movs r5, #1 80014d8: 2938 cmp r1, #56 @ 0x38 80014da: dd00 ble.n 80014de <__aeabi_dadd+0x496> 80014dc: e741 b.n 8001362 <__aeabi_dadd+0x31a> 80014de: 000a movs r2, r1 80014e0: e72f b.n 8001342 <__aeabi_dadd+0x2fa> 80014e2: 4c89 ldr r4, [pc, #548] @ (8001708 <__aeabi_dadd+0x6c0>) 80014e4: 1aff subs r7, r7, r3 80014e6: 4014 ands r4, r2 80014e8: 0762 lsls r2, r4, #29 80014ea: 08e4 lsrs r4, r4, #3 80014ec: e76a b.n 80013c4 <__aeabi_dadd+0x37c> 80014ee: 4a85 ldr r2, [pc, #532] @ (8001704 <__aeabi_dadd+0x6bc>) 80014f0: 4291 cmp r1, r2 80014f2: d100 bne.n 80014f6 <__aeabi_dadd+0x4ae> 80014f4: e0e3 b.n 80016be <__aeabi_dadd+0x676> 80014f6: 4663 mov r3, ip 80014f8: 18c2 adds r2, r0, r3 80014fa: 4282 cmp r2, r0 80014fc: 4180 sbcs r0, r0 80014fe: 0023 movs r3, r4 8001500: 4240 negs r0, r0 8001502: 4453 add r3, sl 8001504: 181b adds r3, r3, r0 8001506: 07dd lsls r5, r3, #31 8001508: 085c lsrs r4, r3, #1 800150a: 2307 movs r3, #7 800150c: 0852 lsrs r2, r2, #1 800150e: 4315 orrs r5, r2 8001510: 000f movs r7, r1 8001512: 402b ands r3, r5 8001514: e700 b.n 8001318 <__aeabi_dadd+0x2d0> 8001516: 4663 mov r3, ip 8001518: 1a1d subs r5, r3, r0 800151a: 45ac cmp ip, r5 800151c: 4192 sbcs r2, r2 800151e: 4653 mov r3, sl 8001520: 4252 negs r2, r2 8001522: 1b1c subs r4, r3, r4 8001524: 000e movs r6, r1 8001526: 4688 mov r8, r1 8001528: 1aa4 subs r4, r4, r2 800152a: e5e5 b.n 80010f8 <__aeabi_dadd+0xb0> 800152c: 2d00 cmp r5, #0 800152e: d000 beq.n 8001532 <__aeabi_dadd+0x4ea> 8001530: e091 b.n 8001656 <__aeabi_dadd+0x60e> 8001532: 2a00 cmp r2, #0 8001534: d138 bne.n 80015a8 <__aeabi_dadd+0x560> 8001536: 2480 movs r4, #128 @ 0x80 8001538: 2600 movs r6, #0 800153a: 0324 lsls r4, r4, #12 800153c: e756 b.n 80013ec <__aeabi_dadd+0x3a4> 800153e: 4663 mov r3, ip 8001540: 18c5 adds r5, r0, r3 8001542: 4285 cmp r5, r0 8001544: 4180 sbcs r0, r0 8001546: 4454 add r4, sl 8001548: 4240 negs r0, r0 800154a: 1824 adds r4, r4, r0 800154c: 2701 movs r7, #1 800154e: 0223 lsls r3, r4, #8 8001550: d400 bmi.n 8001554 <__aeabi_dadd+0x50c> 8001552: e6df b.n 8001314 <__aeabi_dadd+0x2cc> 8001554: 2702 movs r7, #2 8001556: e687 b.n 8001268 <__aeabi_dadd+0x220> 8001558: 4663 mov r3, ip 800155a: 1ac5 subs r5, r0, r3 800155c: 42a8 cmp r0, r5 800155e: 4180 sbcs r0, r0 8001560: 4653 mov r3, sl 8001562: 4240 negs r0, r0 8001564: 1ae4 subs r4, r4, r3 8001566: 2701 movs r7, #1 8001568: 1a24 subs r4, r4, r0 800156a: e5c0 b.n 80010ee <__aeabi_dadd+0xa6> 800156c: 0762 lsls r2, r4, #29 800156e: 08c0 lsrs r0, r0, #3 8001570: 4302 orrs r2, r0 8001572: 08e4 lsrs r4, r4, #3 8001574: e736 b.n 80013e4 <__aeabi_dadd+0x39c> 8001576: 0011 movs r1, r2 8001578: 4653 mov r3, sl 800157a: 3920 subs r1, #32 800157c: 40cb lsrs r3, r1 800157e: 4699 mov r9, r3 8001580: 2a20 cmp r2, #32 8001582: d006 beq.n 8001592 <__aeabi_dadd+0x54a> 8001584: 2140 movs r1, #64 @ 0x40 8001586: 4653 mov r3, sl 8001588: 1a8a subs r2, r1, r2 800158a: 4093 lsls r3, r2 800158c: 4662 mov r2, ip 800158e: 431a orrs r2, r3 8001590: 4694 mov ip, r2 8001592: 4665 mov r5, ip 8001594: 1e6b subs r3, r5, #1 8001596: 419d sbcs r5, r3 8001598: 464b mov r3, r9 800159a: 431d orrs r5, r3 800159c: e659 b.n 8001252 <__aeabi_dadd+0x20a> 800159e: 0762 lsls r2, r4, #29 80015a0: 08c0 lsrs r0, r0, #3 80015a2: 4302 orrs r2, r0 80015a4: 08e4 lsrs r4, r4, #3 80015a6: e70d b.n 80013c4 <__aeabi_dadd+0x37c> 80015a8: 4653 mov r3, sl 80015aa: 075a lsls r2, r3, #29 80015ac: 4663 mov r3, ip 80015ae: 08d8 lsrs r0, r3, #3 80015b0: 4653 mov r3, sl 80015b2: 000e movs r6, r1 80015b4: 4302 orrs r2, r0 80015b6: 08dc lsrs r4, r3, #3 80015b8: e714 b.n 80013e4 <__aeabi_dadd+0x39c> 80015ba: 0015 movs r5, r2 80015bc: 0026 movs r6, r4 80015be: 3d20 subs r5, #32 80015c0: 40ee lsrs r6, r5 80015c2: 2a20 cmp r2, #32 80015c4: d003 beq.n 80015ce <__aeabi_dadd+0x586> 80015c6: 2540 movs r5, #64 @ 0x40 80015c8: 1aaa subs r2, r5, r2 80015ca: 4094 lsls r4, r2 80015cc: 4320 orrs r0, r4 80015ce: 1e42 subs r2, r0, #1 80015d0: 4190 sbcs r0, r2 80015d2: 0005 movs r5, r0 80015d4: 4335 orrs r5, r6 80015d6: e606 b.n 80011e6 <__aeabi_dadd+0x19e> 80015d8: 2a00 cmp r2, #0 80015da: d07c beq.n 80016d6 <__aeabi_dadd+0x68e> 80015dc: 4662 mov r2, ip 80015de: 4653 mov r3, sl 80015e0: 08c0 lsrs r0, r0, #3 80015e2: 431a orrs r2, r3 80015e4: d100 bne.n 80015e8 <__aeabi_dadd+0x5a0> 80015e6: e6fa b.n 80013de <__aeabi_dadd+0x396> 80015e8: 0762 lsls r2, r4, #29 80015ea: 4310 orrs r0, r2 80015ec: 2280 movs r2, #128 @ 0x80 80015ee: 08e4 lsrs r4, r4, #3 80015f0: 0312 lsls r2, r2, #12 80015f2: 4214 tst r4, r2 80015f4: d008 beq.n 8001608 <__aeabi_dadd+0x5c0> 80015f6: 08d9 lsrs r1, r3, #3 80015f8: 4211 tst r1, r2 80015fa: d105 bne.n 8001608 <__aeabi_dadd+0x5c0> 80015fc: 4663 mov r3, ip 80015fe: 08d8 lsrs r0, r3, #3 8001600: 4653 mov r3, sl 8001602: 000c movs r4, r1 8001604: 075b lsls r3, r3, #29 8001606: 4318 orrs r0, r3 8001608: 0f42 lsrs r2, r0, #29 800160a: 00c0 lsls r0, r0, #3 800160c: 08c0 lsrs r0, r0, #3 800160e: 0752 lsls r2, r2, #29 8001610: 4302 orrs r2, r0 8001612: e6e7 b.n 80013e4 <__aeabi_dadd+0x39c> 8001614: 2a00 cmp r2, #0 8001616: d100 bne.n 800161a <__aeabi_dadd+0x5d2> 8001618: e72d b.n 8001476 <__aeabi_dadd+0x42e> 800161a: 4663 mov r3, ip 800161c: 08d8 lsrs r0, r3, #3 800161e: 4653 mov r3, sl 8001620: 075a lsls r2, r3, #29 8001622: 000e movs r6, r1 8001624: 4302 orrs r2, r0 8001626: 08dc lsrs r4, r3, #3 8001628: e6cc b.n 80013c4 <__aeabi_dadd+0x37c> 800162a: 4663 mov r3, ip 800162c: 1a1d subs r5, r3, r0 800162e: 45ac cmp ip, r5 8001630: 4192 sbcs r2, r2 8001632: 4653 mov r3, sl 8001634: 4252 negs r2, r2 8001636: 1b1c subs r4, r3, r4 8001638: 000e movs r6, r1 800163a: 4688 mov r8, r1 800163c: 1aa4 subs r4, r4, r2 800163e: 3701 adds r7, #1 8001640: e555 b.n 80010ee <__aeabi_dadd+0xa6> 8001642: 4663 mov r3, ip 8001644: 08d9 lsrs r1, r3, #3 8001646: 4653 mov r3, sl 8001648: 075a lsls r2, r3, #29 800164a: 430a orrs r2, r1 800164c: 08dc lsrs r4, r3, #3 800164e: e6c9 b.n 80013e4 <__aeabi_dadd+0x39c> 8001650: 4660 mov r0, ip 8001652: 4654 mov r4, sl 8001654: e6d4 b.n 8001400 <__aeabi_dadd+0x3b8> 8001656: 08c0 lsrs r0, r0, #3 8001658: 2a00 cmp r2, #0 800165a: d100 bne.n 800165e <__aeabi_dadd+0x616> 800165c: e6bf b.n 80013de <__aeabi_dadd+0x396> 800165e: 0762 lsls r2, r4, #29 8001660: 4310 orrs r0, r2 8001662: 2280 movs r2, #128 @ 0x80 8001664: 08e4 lsrs r4, r4, #3 8001666: 0312 lsls r2, r2, #12 8001668: 4214 tst r4, r2 800166a: d0cd beq.n 8001608 <__aeabi_dadd+0x5c0> 800166c: 08dd lsrs r5, r3, #3 800166e: 4215 tst r5, r2 8001670: d1ca bne.n 8001608 <__aeabi_dadd+0x5c0> 8001672: 4663 mov r3, ip 8001674: 08d8 lsrs r0, r3, #3 8001676: 4653 mov r3, sl 8001678: 075b lsls r3, r3, #29 800167a: 000e movs r6, r1 800167c: 002c movs r4, r5 800167e: 4318 orrs r0, r3 8001680: e7c2 b.n 8001608 <__aeabi_dadd+0x5c0> 8001682: 4663 mov r3, ip 8001684: 08d9 lsrs r1, r3, #3 8001686: 4653 mov r3, sl 8001688: 075a lsls r2, r3, #29 800168a: 430a orrs r2, r1 800168c: 08dc lsrs r4, r3, #3 800168e: e699 b.n 80013c4 <__aeabi_dadd+0x37c> 8001690: 4663 mov r3, ip 8001692: 08d8 lsrs r0, r3, #3 8001694: 4653 mov r3, sl 8001696: 075a lsls r2, r3, #29 8001698: 000e movs r6, r1 800169a: 4302 orrs r2, r0 800169c: 08dc lsrs r4, r3, #3 800169e: e6a1 b.n 80013e4 <__aeabi_dadd+0x39c> 80016a0: 0011 movs r1, r2 80016a2: 0027 movs r7, r4 80016a4: 3920 subs r1, #32 80016a6: 40cf lsrs r7, r1 80016a8: 2a20 cmp r2, #32 80016aa: d003 beq.n 80016b4 <__aeabi_dadd+0x66c> 80016ac: 2140 movs r1, #64 @ 0x40 80016ae: 1a8a subs r2, r1, r2 80016b0: 4094 lsls r4, r2 80016b2: 4320 orrs r0, r4 80016b4: 1e42 subs r2, r0, #1 80016b6: 4190 sbcs r0, r2 80016b8: 0005 movs r5, r0 80016ba: 433d orrs r5, r7 80016bc: e651 b.n 8001362 <__aeabi_dadd+0x31a> 80016be: 000c movs r4, r1 80016c0: 2500 movs r5, #0 80016c2: 2200 movs r2, #0 80016c4: e558 b.n 8001178 <__aeabi_dadd+0x130> 80016c6: 4460 add r0, ip 80016c8: 4560 cmp r0, ip 80016ca: 4192 sbcs r2, r2 80016cc: 4454 add r4, sl 80016ce: 4252 negs r2, r2 80016d0: 0005 movs r5, r0 80016d2: 18a4 adds r4, r4, r2 80016d4: e73a b.n 800154c <__aeabi_dadd+0x504> 80016d6: 4653 mov r3, sl 80016d8: 075a lsls r2, r3, #29 80016da: 4663 mov r3, ip 80016dc: 08d9 lsrs r1, r3, #3 80016de: 4653 mov r3, sl 80016e0: 430a orrs r2, r1 80016e2: 08dc lsrs r4, r3, #3 80016e4: e67e b.n 80013e4 <__aeabi_dadd+0x39c> 80016e6: 001a movs r2, r3 80016e8: 001c movs r4, r3 80016ea: 432a orrs r2, r5 80016ec: d000 beq.n 80016f0 <__aeabi_dadd+0x6a8> 80016ee: e6ab b.n 8001448 <__aeabi_dadd+0x400> 80016f0: e6c1 b.n 8001476 <__aeabi_dadd+0x42e> 80016f2: 2120 movs r1, #32 80016f4: 2500 movs r5, #0 80016f6: 1a09 subs r1, r1, r0 80016f8: e519 b.n 800112e <__aeabi_dadd+0xe6> 80016fa: 2200 movs r2, #0 80016fc: 2500 movs r5, #0 80016fe: 4c01 ldr r4, [pc, #4] @ (8001704 <__aeabi_dadd+0x6bc>) 8001700: e53a b.n 8001178 <__aeabi_dadd+0x130> 8001702: 46c0 nop @ (mov r8, r8) 8001704: 000007ff .word 0x000007ff 8001708: ff7fffff .word 0xff7fffff 800170c: 000007fe .word 0x000007fe 08001710 <__aeabi_ddiv>: 8001710: b5f0 push {r4, r5, r6, r7, lr} 8001712: 46de mov lr, fp 8001714: 4645 mov r5, r8 8001716: 4657 mov r7, sl 8001718: 464e mov r6, r9 800171a: b5e0 push {r5, r6, r7, lr} 800171c: b087 sub sp, #28 800171e: 9200 str r2, [sp, #0] 8001720: 9301 str r3, [sp, #4] 8001722: 030b lsls r3, r1, #12 8001724: 0b1b lsrs r3, r3, #12 8001726: 469b mov fp, r3 8001728: 0fca lsrs r2, r1, #31 800172a: 004b lsls r3, r1, #1 800172c: 0004 movs r4, r0 800172e: 4680 mov r8, r0 8001730: 0d5b lsrs r3, r3, #21 8001732: 9202 str r2, [sp, #8] 8001734: d100 bne.n 8001738 <__aeabi_ddiv+0x28> 8001736: e16a b.n 8001a0e <__aeabi_ddiv+0x2fe> 8001738: 4ad4 ldr r2, [pc, #848] @ (8001a8c <__aeabi_ddiv+0x37c>) 800173a: 4293 cmp r3, r2 800173c: d100 bne.n 8001740 <__aeabi_ddiv+0x30> 800173e: e18c b.n 8001a5a <__aeabi_ddiv+0x34a> 8001740: 4659 mov r1, fp 8001742: 0f42 lsrs r2, r0, #29 8001744: 00c9 lsls r1, r1, #3 8001746: 430a orrs r2, r1 8001748: 2180 movs r1, #128 @ 0x80 800174a: 0409 lsls r1, r1, #16 800174c: 4311 orrs r1, r2 800174e: 00c2 lsls r2, r0, #3 8001750: 4690 mov r8, r2 8001752: 4acf ldr r2, [pc, #828] @ (8001a90 <__aeabi_ddiv+0x380>) 8001754: 4689 mov r9, r1 8001756: 4692 mov sl, r2 8001758: 449a add sl, r3 800175a: 2300 movs r3, #0 800175c: 2400 movs r4, #0 800175e: 9303 str r3, [sp, #12] 8001760: 9e00 ldr r6, [sp, #0] 8001762: 9f01 ldr r7, [sp, #4] 8001764: 033b lsls r3, r7, #12 8001766: 0b1b lsrs r3, r3, #12 8001768: 469b mov fp, r3 800176a: 007b lsls r3, r7, #1 800176c: 0030 movs r0, r6 800176e: 0d5b lsrs r3, r3, #21 8001770: 0ffd lsrs r5, r7, #31 8001772: 2b00 cmp r3, #0 8001774: d100 bne.n 8001778 <__aeabi_ddiv+0x68> 8001776: e128 b.n 80019ca <__aeabi_ddiv+0x2ba> 8001778: 4ac4 ldr r2, [pc, #784] @ (8001a8c <__aeabi_ddiv+0x37c>) 800177a: 4293 cmp r3, r2 800177c: d100 bne.n 8001780 <__aeabi_ddiv+0x70> 800177e: e177 b.n 8001a70 <__aeabi_ddiv+0x360> 8001780: 4659 mov r1, fp 8001782: 0f72 lsrs r2, r6, #29 8001784: 00c9 lsls r1, r1, #3 8001786: 430a orrs r2, r1 8001788: 2180 movs r1, #128 @ 0x80 800178a: 0409 lsls r1, r1, #16 800178c: 4311 orrs r1, r2 800178e: 468b mov fp, r1 8001790: 49bf ldr r1, [pc, #764] @ (8001a90 <__aeabi_ddiv+0x380>) 8001792: 00f2 lsls r2, r6, #3 8001794: 468c mov ip, r1 8001796: 4651 mov r1, sl 8001798: 4463 add r3, ip 800179a: 1acb subs r3, r1, r3 800179c: 469a mov sl, r3 800179e: 2300 movs r3, #0 80017a0: 9e02 ldr r6, [sp, #8] 80017a2: 406e eors r6, r5 80017a4: 2c0f cmp r4, #15 80017a6: d827 bhi.n 80017f8 <__aeabi_ddiv+0xe8> 80017a8: 49ba ldr r1, [pc, #744] @ (8001a94 <__aeabi_ddiv+0x384>) 80017aa: 00a4 lsls r4, r4, #2 80017ac: 5909 ldr r1, [r1, r4] 80017ae: 468f mov pc, r1 80017b0: 46cb mov fp, r9 80017b2: 4642 mov r2, r8 80017b4: 9e02 ldr r6, [sp, #8] 80017b6: 9b03 ldr r3, [sp, #12] 80017b8: 2b02 cmp r3, #2 80017ba: d016 beq.n 80017ea <__aeabi_ddiv+0xda> 80017bc: 2b03 cmp r3, #3 80017be: d100 bne.n 80017c2 <__aeabi_ddiv+0xb2> 80017c0: e2a6 b.n 8001d10 <__aeabi_ddiv+0x600> 80017c2: 2b01 cmp r3, #1 80017c4: d000 beq.n 80017c8 <__aeabi_ddiv+0xb8> 80017c6: e0df b.n 8001988 <__aeabi_ddiv+0x278> 80017c8: 2200 movs r2, #0 80017ca: 2300 movs r3, #0 80017cc: 2400 movs r4, #0 80017ce: 4690 mov r8, r2 80017d0: 051b lsls r3, r3, #20 80017d2: 4323 orrs r3, r4 80017d4: 07f6 lsls r6, r6, #31 80017d6: 4333 orrs r3, r6 80017d8: 4640 mov r0, r8 80017da: 0019 movs r1, r3 80017dc: b007 add sp, #28 80017de: bcf0 pop {r4, r5, r6, r7} 80017e0: 46bb mov fp, r7 80017e2: 46b2 mov sl, r6 80017e4: 46a9 mov r9, r5 80017e6: 46a0 mov r8, r4 80017e8: bdf0 pop {r4, r5, r6, r7, pc} 80017ea: 2200 movs r2, #0 80017ec: 2400 movs r4, #0 80017ee: 4690 mov r8, r2 80017f0: 4ba6 ldr r3, [pc, #664] @ (8001a8c <__aeabi_ddiv+0x37c>) 80017f2: e7ed b.n 80017d0 <__aeabi_ddiv+0xc0> 80017f4: 002e movs r6, r5 80017f6: e7df b.n 80017b8 <__aeabi_ddiv+0xa8> 80017f8: 45cb cmp fp, r9 80017fa: d200 bcs.n 80017fe <__aeabi_ddiv+0xee> 80017fc: e1d4 b.n 8001ba8 <__aeabi_ddiv+0x498> 80017fe: d100 bne.n 8001802 <__aeabi_ddiv+0xf2> 8001800: e1cf b.n 8001ba2 <__aeabi_ddiv+0x492> 8001802: 2301 movs r3, #1 8001804: 425b negs r3, r3 8001806: 469c mov ip, r3 8001808: 4644 mov r4, r8 800180a: 4648 mov r0, r9 800180c: 2700 movs r7, #0 800180e: 44e2 add sl, ip 8001810: 465b mov r3, fp 8001812: 0e15 lsrs r5, r2, #24 8001814: 021b lsls r3, r3, #8 8001816: 431d orrs r5, r3 8001818: 0c19 lsrs r1, r3, #16 800181a: 042b lsls r3, r5, #16 800181c: 0212 lsls r2, r2, #8 800181e: 9500 str r5, [sp, #0] 8001820: 0c1d lsrs r5, r3, #16 8001822: 4691 mov r9, r2 8001824: 9102 str r1, [sp, #8] 8001826: 9503 str r5, [sp, #12] 8001828: f7fe fcf2 bl 8000210 <__aeabi_uidivmod> 800182c: 0002 movs r2, r0 800182e: 436a muls r2, r5 8001830: 040b lsls r3, r1, #16 8001832: 0c21 lsrs r1, r4, #16 8001834: 4680 mov r8, r0 8001836: 4319 orrs r1, r3 8001838: 428a cmp r2, r1 800183a: d909 bls.n 8001850 <__aeabi_ddiv+0x140> 800183c: 9d00 ldr r5, [sp, #0] 800183e: 2301 movs r3, #1 8001840: 46ac mov ip, r5 8001842: 425b negs r3, r3 8001844: 4461 add r1, ip 8001846: 469c mov ip, r3 8001848: 44e0 add r8, ip 800184a: 428d cmp r5, r1 800184c: d800 bhi.n 8001850 <__aeabi_ddiv+0x140> 800184e: e1fb b.n 8001c48 <__aeabi_ddiv+0x538> 8001850: 1a88 subs r0, r1, r2 8001852: 9902 ldr r1, [sp, #8] 8001854: f7fe fcdc bl 8000210 <__aeabi_uidivmod> 8001858: 9a03 ldr r2, [sp, #12] 800185a: 0424 lsls r4, r4, #16 800185c: 4342 muls r2, r0 800185e: 0409 lsls r1, r1, #16 8001860: 0c24 lsrs r4, r4, #16 8001862: 0003 movs r3, r0 8001864: 430c orrs r4, r1 8001866: 42a2 cmp r2, r4 8001868: d906 bls.n 8001878 <__aeabi_ddiv+0x168> 800186a: 9900 ldr r1, [sp, #0] 800186c: 3b01 subs r3, #1 800186e: 468c mov ip, r1 8001870: 4464 add r4, ip 8001872: 42a1 cmp r1, r4 8001874: d800 bhi.n 8001878 <__aeabi_ddiv+0x168> 8001876: e1e1 b.n 8001c3c <__aeabi_ddiv+0x52c> 8001878: 1aa0 subs r0, r4, r2 800187a: 4642 mov r2, r8 800187c: 0412 lsls r2, r2, #16 800187e: 431a orrs r2, r3 8001880: 4693 mov fp, r2 8001882: 464b mov r3, r9 8001884: 4659 mov r1, fp 8001886: 0c1b lsrs r3, r3, #16 8001888: 001d movs r5, r3 800188a: 9304 str r3, [sp, #16] 800188c: 040b lsls r3, r1, #16 800188e: 4649 mov r1, r9 8001890: 0409 lsls r1, r1, #16 8001892: 0c09 lsrs r1, r1, #16 8001894: 000c movs r4, r1 8001896: 0c1b lsrs r3, r3, #16 8001898: 435c muls r4, r3 800189a: 0c12 lsrs r2, r2, #16 800189c: 436b muls r3, r5 800189e: 4688 mov r8, r1 80018a0: 4351 muls r1, r2 80018a2: 436a muls r2, r5 80018a4: 0c25 lsrs r5, r4, #16 80018a6: 46ac mov ip, r5 80018a8: 185b adds r3, r3, r1 80018aa: 4463 add r3, ip 80018ac: 4299 cmp r1, r3 80018ae: d903 bls.n 80018b8 <__aeabi_ddiv+0x1a8> 80018b0: 2180 movs r1, #128 @ 0x80 80018b2: 0249 lsls r1, r1, #9 80018b4: 468c mov ip, r1 80018b6: 4462 add r2, ip 80018b8: 0c19 lsrs r1, r3, #16 80018ba: 0424 lsls r4, r4, #16 80018bc: 041b lsls r3, r3, #16 80018be: 0c24 lsrs r4, r4, #16 80018c0: 188a adds r2, r1, r2 80018c2: 191c adds r4, r3, r4 80018c4: 4290 cmp r0, r2 80018c6: d302 bcc.n 80018ce <__aeabi_ddiv+0x1be> 80018c8: d116 bne.n 80018f8 <__aeabi_ddiv+0x1e8> 80018ca: 42a7 cmp r7, r4 80018cc: d214 bcs.n 80018f8 <__aeabi_ddiv+0x1e8> 80018ce: 465b mov r3, fp 80018d0: 9d00 ldr r5, [sp, #0] 80018d2: 3b01 subs r3, #1 80018d4: 444f add r7, r9 80018d6: 9305 str r3, [sp, #20] 80018d8: 454f cmp r7, r9 80018da: 419b sbcs r3, r3 80018dc: 46ac mov ip, r5 80018de: 425b negs r3, r3 80018e0: 4463 add r3, ip 80018e2: 18c0 adds r0, r0, r3 80018e4: 4285 cmp r5, r0 80018e6: d300 bcc.n 80018ea <__aeabi_ddiv+0x1da> 80018e8: e1a1 b.n 8001c2e <__aeabi_ddiv+0x51e> 80018ea: 4282 cmp r2, r0 80018ec: d900 bls.n 80018f0 <__aeabi_ddiv+0x1e0> 80018ee: e1f6 b.n 8001cde <__aeabi_ddiv+0x5ce> 80018f0: d100 bne.n 80018f4 <__aeabi_ddiv+0x1e4> 80018f2: e1f1 b.n 8001cd8 <__aeabi_ddiv+0x5c8> 80018f4: 9b05 ldr r3, [sp, #20] 80018f6: 469b mov fp, r3 80018f8: 1b3c subs r4, r7, r4 80018fa: 42a7 cmp r7, r4 80018fc: 41bf sbcs r7, r7 80018fe: 9d00 ldr r5, [sp, #0] 8001900: 1a80 subs r0, r0, r2 8001902: 427f negs r7, r7 8001904: 1bc0 subs r0, r0, r7 8001906: 4285 cmp r5, r0 8001908: d100 bne.n 800190c <__aeabi_ddiv+0x1fc> 800190a: e1d0 b.n 8001cae <__aeabi_ddiv+0x59e> 800190c: 9902 ldr r1, [sp, #8] 800190e: f7fe fc7f bl 8000210 <__aeabi_uidivmod> 8001912: 9a03 ldr r2, [sp, #12] 8001914: 040b lsls r3, r1, #16 8001916: 4342 muls r2, r0 8001918: 0c21 lsrs r1, r4, #16 800191a: 0007 movs r7, r0 800191c: 4319 orrs r1, r3 800191e: 428a cmp r2, r1 8001920: d900 bls.n 8001924 <__aeabi_ddiv+0x214> 8001922: e178 b.n 8001c16 <__aeabi_ddiv+0x506> 8001924: 1a88 subs r0, r1, r2 8001926: 9902 ldr r1, [sp, #8] 8001928: f7fe fc72 bl 8000210 <__aeabi_uidivmod> 800192c: 9a03 ldr r2, [sp, #12] 800192e: 0424 lsls r4, r4, #16 8001930: 4342 muls r2, r0 8001932: 0409 lsls r1, r1, #16 8001934: 0c24 lsrs r4, r4, #16 8001936: 0003 movs r3, r0 8001938: 430c orrs r4, r1 800193a: 42a2 cmp r2, r4 800193c: d900 bls.n 8001940 <__aeabi_ddiv+0x230> 800193e: e15d b.n 8001bfc <__aeabi_ddiv+0x4ec> 8001940: 4641 mov r1, r8 8001942: 1aa4 subs r4, r4, r2 8001944: 043a lsls r2, r7, #16 8001946: 431a orrs r2, r3 8001948: 9d04 ldr r5, [sp, #16] 800194a: 0413 lsls r3, r2, #16 800194c: 0c1b lsrs r3, r3, #16 800194e: 4359 muls r1, r3 8001950: 4647 mov r7, r8 8001952: 436b muls r3, r5 8001954: 469c mov ip, r3 8001956: 0c10 lsrs r0, r2, #16 8001958: 4347 muls r7, r0 800195a: 0c0b lsrs r3, r1, #16 800195c: 44bc add ip, r7 800195e: 4463 add r3, ip 8001960: 4368 muls r0, r5 8001962: 429f cmp r7, r3 8001964: d903 bls.n 800196e <__aeabi_ddiv+0x25e> 8001966: 2580 movs r5, #128 @ 0x80 8001968: 026d lsls r5, r5, #9 800196a: 46ac mov ip, r5 800196c: 4460 add r0, ip 800196e: 0c1f lsrs r7, r3, #16 8001970: 0409 lsls r1, r1, #16 8001972: 041b lsls r3, r3, #16 8001974: 0c09 lsrs r1, r1, #16 8001976: 183f adds r7, r7, r0 8001978: 185b adds r3, r3, r1 800197a: 42bc cmp r4, r7 800197c: d200 bcs.n 8001980 <__aeabi_ddiv+0x270> 800197e: e102 b.n 8001b86 <__aeabi_ddiv+0x476> 8001980: d100 bne.n 8001984 <__aeabi_ddiv+0x274> 8001982: e0fd b.n 8001b80 <__aeabi_ddiv+0x470> 8001984: 2301 movs r3, #1 8001986: 431a orrs r2, r3 8001988: 4b43 ldr r3, [pc, #268] @ (8001a98 <__aeabi_ddiv+0x388>) 800198a: 4453 add r3, sl 800198c: 2b00 cmp r3, #0 800198e: dc00 bgt.n 8001992 <__aeabi_ddiv+0x282> 8001990: e0ae b.n 8001af0 <__aeabi_ddiv+0x3e0> 8001992: 0751 lsls r1, r2, #29 8001994: d000 beq.n 8001998 <__aeabi_ddiv+0x288> 8001996: e198 b.n 8001cca <__aeabi_ddiv+0x5ba> 8001998: 4659 mov r1, fp 800199a: 01c9 lsls r1, r1, #7 800199c: d506 bpl.n 80019ac <__aeabi_ddiv+0x29c> 800199e: 4659 mov r1, fp 80019a0: 4b3e ldr r3, [pc, #248] @ (8001a9c <__aeabi_ddiv+0x38c>) 80019a2: 4019 ands r1, r3 80019a4: 2380 movs r3, #128 @ 0x80 80019a6: 468b mov fp, r1 80019a8: 00db lsls r3, r3, #3 80019aa: 4453 add r3, sl 80019ac: 493c ldr r1, [pc, #240] @ (8001aa0 <__aeabi_ddiv+0x390>) 80019ae: 428b cmp r3, r1 80019b0: dd00 ble.n 80019b4 <__aeabi_ddiv+0x2a4> 80019b2: e71a b.n 80017ea <__aeabi_ddiv+0xda> 80019b4: 4659 mov r1, fp 80019b6: 08d2 lsrs r2, r2, #3 80019b8: 0749 lsls r1, r1, #29 80019ba: 4311 orrs r1, r2 80019bc: 465a mov r2, fp 80019be: 055b lsls r3, r3, #21 80019c0: 0254 lsls r4, r2, #9 80019c2: 4688 mov r8, r1 80019c4: 0b24 lsrs r4, r4, #12 80019c6: 0d5b lsrs r3, r3, #21 80019c8: e702 b.n 80017d0 <__aeabi_ddiv+0xc0> 80019ca: 465a mov r2, fp 80019cc: 9b00 ldr r3, [sp, #0] 80019ce: 431a orrs r2, r3 80019d0: d100 bne.n 80019d4 <__aeabi_ddiv+0x2c4> 80019d2: e07e b.n 8001ad2 <__aeabi_ddiv+0x3c2> 80019d4: 465b mov r3, fp 80019d6: 2b00 cmp r3, #0 80019d8: d100 bne.n 80019dc <__aeabi_ddiv+0x2cc> 80019da: e100 b.n 8001bde <__aeabi_ddiv+0x4ce> 80019dc: 4658 mov r0, fp 80019de: f001 fa2d bl 8002e3c <__clzsi2> 80019e2: 0002 movs r2, r0 80019e4: 0003 movs r3, r0 80019e6: 3a0b subs r2, #11 80019e8: 271d movs r7, #29 80019ea: 9e00 ldr r6, [sp, #0] 80019ec: 1aba subs r2, r7, r2 80019ee: 0019 movs r1, r3 80019f0: 4658 mov r0, fp 80019f2: 40d6 lsrs r6, r2 80019f4: 3908 subs r1, #8 80019f6: 4088 lsls r0, r1 80019f8: 0032 movs r2, r6 80019fa: 4302 orrs r2, r0 80019fc: 4693 mov fp, r2 80019fe: 9a00 ldr r2, [sp, #0] 8001a00: 408a lsls r2, r1 8001a02: 4928 ldr r1, [pc, #160] @ (8001aa4 <__aeabi_ddiv+0x394>) 8001a04: 4453 add r3, sl 8001a06: 468a mov sl, r1 8001a08: 449a add sl, r3 8001a0a: 2300 movs r3, #0 8001a0c: e6c8 b.n 80017a0 <__aeabi_ddiv+0x90> 8001a0e: 465b mov r3, fp 8001a10: 4303 orrs r3, r0 8001a12: 4699 mov r9, r3 8001a14: d056 beq.n 8001ac4 <__aeabi_ddiv+0x3b4> 8001a16: 465b mov r3, fp 8001a18: 2b00 cmp r3, #0 8001a1a: d100 bne.n 8001a1e <__aeabi_ddiv+0x30e> 8001a1c: e0cd b.n 8001bba <__aeabi_ddiv+0x4aa> 8001a1e: 4658 mov r0, fp 8001a20: f001 fa0c bl 8002e3c <__clzsi2> 8001a24: 230b movs r3, #11 8001a26: 425b negs r3, r3 8001a28: 469c mov ip, r3 8001a2a: 0002 movs r2, r0 8001a2c: 4484 add ip, r0 8001a2e: 4666 mov r6, ip 8001a30: 231d movs r3, #29 8001a32: 1b9b subs r3, r3, r6 8001a34: 0026 movs r6, r4 8001a36: 0011 movs r1, r2 8001a38: 4658 mov r0, fp 8001a3a: 40de lsrs r6, r3 8001a3c: 3908 subs r1, #8 8001a3e: 4088 lsls r0, r1 8001a40: 0033 movs r3, r6 8001a42: 4303 orrs r3, r0 8001a44: 4699 mov r9, r3 8001a46: 0023 movs r3, r4 8001a48: 408b lsls r3, r1 8001a4a: 4698 mov r8, r3 8001a4c: 4b16 ldr r3, [pc, #88] @ (8001aa8 <__aeabi_ddiv+0x398>) 8001a4e: 2400 movs r4, #0 8001a50: 1a9b subs r3, r3, r2 8001a52: 469a mov sl, r3 8001a54: 2300 movs r3, #0 8001a56: 9303 str r3, [sp, #12] 8001a58: e682 b.n 8001760 <__aeabi_ddiv+0x50> 8001a5a: 465a mov r2, fp 8001a5c: 4302 orrs r2, r0 8001a5e: 4691 mov r9, r2 8001a60: d12a bne.n 8001ab8 <__aeabi_ddiv+0x3a8> 8001a62: 2200 movs r2, #0 8001a64: 469a mov sl, r3 8001a66: 2302 movs r3, #2 8001a68: 4690 mov r8, r2 8001a6a: 2408 movs r4, #8 8001a6c: 9303 str r3, [sp, #12] 8001a6e: e677 b.n 8001760 <__aeabi_ddiv+0x50> 8001a70: 465a mov r2, fp 8001a72: 9b00 ldr r3, [sp, #0] 8001a74: 431a orrs r2, r3 8001a76: 4b0d ldr r3, [pc, #52] @ (8001aac <__aeabi_ddiv+0x39c>) 8001a78: 469c mov ip, r3 8001a7a: 44e2 add sl, ip 8001a7c: 2a00 cmp r2, #0 8001a7e: d117 bne.n 8001ab0 <__aeabi_ddiv+0x3a0> 8001a80: 2302 movs r3, #2 8001a82: 431c orrs r4, r3 8001a84: 2300 movs r3, #0 8001a86: 469b mov fp, r3 8001a88: 3302 adds r3, #2 8001a8a: e689 b.n 80017a0 <__aeabi_ddiv+0x90> 8001a8c: 000007ff .word 0x000007ff 8001a90: fffffc01 .word 0xfffffc01 8001a94: 08009e5c .word 0x08009e5c 8001a98: 000003ff .word 0x000003ff 8001a9c: feffffff .word 0xfeffffff 8001aa0: 000007fe .word 0x000007fe 8001aa4: 000003f3 .word 0x000003f3 8001aa8: fffffc0d .word 0xfffffc0d 8001aac: fffff801 .word 0xfffff801 8001ab0: 2303 movs r3, #3 8001ab2: 0032 movs r2, r6 8001ab4: 431c orrs r4, r3 8001ab6: e673 b.n 80017a0 <__aeabi_ddiv+0x90> 8001ab8: 469a mov sl, r3 8001aba: 2303 movs r3, #3 8001abc: 46d9 mov r9, fp 8001abe: 240c movs r4, #12 8001ac0: 9303 str r3, [sp, #12] 8001ac2: e64d b.n 8001760 <__aeabi_ddiv+0x50> 8001ac4: 2300 movs r3, #0 8001ac6: 4698 mov r8, r3 8001ac8: 469a mov sl, r3 8001aca: 3301 adds r3, #1 8001acc: 2404 movs r4, #4 8001ace: 9303 str r3, [sp, #12] 8001ad0: e646 b.n 8001760 <__aeabi_ddiv+0x50> 8001ad2: 2301 movs r3, #1 8001ad4: 431c orrs r4, r3 8001ad6: 2300 movs r3, #0 8001ad8: 469b mov fp, r3 8001ada: 3301 adds r3, #1 8001adc: e660 b.n 80017a0 <__aeabi_ddiv+0x90> 8001ade: 2300 movs r3, #0 8001ae0: 2480 movs r4, #128 @ 0x80 8001ae2: 4698 mov r8, r3 8001ae4: 2600 movs r6, #0 8001ae6: 4b92 ldr r3, [pc, #584] @ (8001d30 <__aeabi_ddiv+0x620>) 8001ae8: 0324 lsls r4, r4, #12 8001aea: e671 b.n 80017d0 <__aeabi_ddiv+0xc0> 8001aec: 2201 movs r2, #1 8001aee: 4252 negs r2, r2 8001af0: 2101 movs r1, #1 8001af2: 1ac9 subs r1, r1, r3 8001af4: 2938 cmp r1, #56 @ 0x38 8001af6: dd00 ble.n 8001afa <__aeabi_ddiv+0x3ea> 8001af8: e666 b.n 80017c8 <__aeabi_ddiv+0xb8> 8001afa: 291f cmp r1, #31 8001afc: dc00 bgt.n 8001b00 <__aeabi_ddiv+0x3f0> 8001afe: e0ab b.n 8001c58 <__aeabi_ddiv+0x548> 8001b00: 201f movs r0, #31 8001b02: 4240 negs r0, r0 8001b04: 1ac3 subs r3, r0, r3 8001b06: 4658 mov r0, fp 8001b08: 40d8 lsrs r0, r3 8001b0a: 0003 movs r3, r0 8001b0c: 2920 cmp r1, #32 8001b0e: d004 beq.n 8001b1a <__aeabi_ddiv+0x40a> 8001b10: 4658 mov r0, fp 8001b12: 4988 ldr r1, [pc, #544] @ (8001d34 <__aeabi_ddiv+0x624>) 8001b14: 4451 add r1, sl 8001b16: 4088 lsls r0, r1 8001b18: 4302 orrs r2, r0 8001b1a: 1e51 subs r1, r2, #1 8001b1c: 418a sbcs r2, r1 8001b1e: 431a orrs r2, r3 8001b20: 2307 movs r3, #7 8001b22: 0019 movs r1, r3 8001b24: 2400 movs r4, #0 8001b26: 4011 ands r1, r2 8001b28: 4213 tst r3, r2 8001b2a: d00c beq.n 8001b46 <__aeabi_ddiv+0x436> 8001b2c: 230f movs r3, #15 8001b2e: 4013 ands r3, r2 8001b30: 2b04 cmp r3, #4 8001b32: d100 bne.n 8001b36 <__aeabi_ddiv+0x426> 8001b34: e0f9 b.n 8001d2a <__aeabi_ddiv+0x61a> 8001b36: 1d11 adds r1, r2, #4 8001b38: 4291 cmp r1, r2 8001b3a: 419b sbcs r3, r3 8001b3c: 000a movs r2, r1 8001b3e: 425b negs r3, r3 8001b40: 0759 lsls r1, r3, #29 8001b42: 025b lsls r3, r3, #9 8001b44: 0b1c lsrs r4, r3, #12 8001b46: 08d2 lsrs r2, r2, #3 8001b48: 430a orrs r2, r1 8001b4a: 4690 mov r8, r2 8001b4c: 2300 movs r3, #0 8001b4e: e63f b.n 80017d0 <__aeabi_ddiv+0xc0> 8001b50: 2480 movs r4, #128 @ 0x80 8001b52: 464b mov r3, r9 8001b54: 0324 lsls r4, r4, #12 8001b56: 4223 tst r3, r4 8001b58: d009 beq.n 8001b6e <__aeabi_ddiv+0x45e> 8001b5a: 465b mov r3, fp 8001b5c: 4223 tst r3, r4 8001b5e: d106 bne.n 8001b6e <__aeabi_ddiv+0x45e> 8001b60: 431c orrs r4, r3 8001b62: 0324 lsls r4, r4, #12 8001b64: 002e movs r6, r5 8001b66: 4690 mov r8, r2 8001b68: 4b71 ldr r3, [pc, #452] @ (8001d30 <__aeabi_ddiv+0x620>) 8001b6a: 0b24 lsrs r4, r4, #12 8001b6c: e630 b.n 80017d0 <__aeabi_ddiv+0xc0> 8001b6e: 2480 movs r4, #128 @ 0x80 8001b70: 464b mov r3, r9 8001b72: 0324 lsls r4, r4, #12 8001b74: 431c orrs r4, r3 8001b76: 0324 lsls r4, r4, #12 8001b78: 9e02 ldr r6, [sp, #8] 8001b7a: 4b6d ldr r3, [pc, #436] @ (8001d30 <__aeabi_ddiv+0x620>) 8001b7c: 0b24 lsrs r4, r4, #12 8001b7e: e627 b.n 80017d0 <__aeabi_ddiv+0xc0> 8001b80: 2b00 cmp r3, #0 8001b82: d100 bne.n 8001b86 <__aeabi_ddiv+0x476> 8001b84: e700 b.n 8001988 <__aeabi_ddiv+0x278> 8001b86: 9800 ldr r0, [sp, #0] 8001b88: 1e51 subs r1, r2, #1 8001b8a: 4684 mov ip, r0 8001b8c: 4464 add r4, ip 8001b8e: 4284 cmp r4, r0 8001b90: d200 bcs.n 8001b94 <__aeabi_ddiv+0x484> 8001b92: e084 b.n 8001c9e <__aeabi_ddiv+0x58e> 8001b94: 42bc cmp r4, r7 8001b96: d200 bcs.n 8001b9a <__aeabi_ddiv+0x48a> 8001b98: e0ae b.n 8001cf8 <__aeabi_ddiv+0x5e8> 8001b9a: d100 bne.n 8001b9e <__aeabi_ddiv+0x48e> 8001b9c: e0c1 b.n 8001d22 <__aeabi_ddiv+0x612> 8001b9e: 000a movs r2, r1 8001ba0: e6f0 b.n 8001984 <__aeabi_ddiv+0x274> 8001ba2: 4542 cmp r2, r8 8001ba4: d900 bls.n 8001ba8 <__aeabi_ddiv+0x498> 8001ba6: e62c b.n 8001802 <__aeabi_ddiv+0xf2> 8001ba8: 464b mov r3, r9 8001baa: 07dc lsls r4, r3, #31 8001bac: 0858 lsrs r0, r3, #1 8001bae: 4643 mov r3, r8 8001bb0: 085b lsrs r3, r3, #1 8001bb2: 431c orrs r4, r3 8001bb4: 4643 mov r3, r8 8001bb6: 07df lsls r7, r3, #31 8001bb8: e62a b.n 8001810 <__aeabi_ddiv+0x100> 8001bba: f001 f93f bl 8002e3c <__clzsi2> 8001bbe: 2315 movs r3, #21 8001bc0: 469c mov ip, r3 8001bc2: 4484 add ip, r0 8001bc4: 0002 movs r2, r0 8001bc6: 4663 mov r3, ip 8001bc8: 3220 adds r2, #32 8001bca: 2b1c cmp r3, #28 8001bcc: dc00 bgt.n 8001bd0 <__aeabi_ddiv+0x4c0> 8001bce: e72e b.n 8001a2e <__aeabi_ddiv+0x31e> 8001bd0: 0023 movs r3, r4 8001bd2: 3808 subs r0, #8 8001bd4: 4083 lsls r3, r0 8001bd6: 4699 mov r9, r3 8001bd8: 2300 movs r3, #0 8001bda: 4698 mov r8, r3 8001bdc: e736 b.n 8001a4c <__aeabi_ddiv+0x33c> 8001bde: f001 f92d bl 8002e3c <__clzsi2> 8001be2: 0002 movs r2, r0 8001be4: 0003 movs r3, r0 8001be6: 3215 adds r2, #21 8001be8: 3320 adds r3, #32 8001bea: 2a1c cmp r2, #28 8001bec: dc00 bgt.n 8001bf0 <__aeabi_ddiv+0x4e0> 8001bee: e6fb b.n 80019e8 <__aeabi_ddiv+0x2d8> 8001bf0: 9900 ldr r1, [sp, #0] 8001bf2: 3808 subs r0, #8 8001bf4: 4081 lsls r1, r0 8001bf6: 2200 movs r2, #0 8001bf8: 468b mov fp, r1 8001bfa: e702 b.n 8001a02 <__aeabi_ddiv+0x2f2> 8001bfc: 9900 ldr r1, [sp, #0] 8001bfe: 3b01 subs r3, #1 8001c00: 468c mov ip, r1 8001c02: 4464 add r4, ip 8001c04: 42a1 cmp r1, r4 8001c06: d900 bls.n 8001c0a <__aeabi_ddiv+0x4fa> 8001c08: e69a b.n 8001940 <__aeabi_ddiv+0x230> 8001c0a: 42a2 cmp r2, r4 8001c0c: d800 bhi.n 8001c10 <__aeabi_ddiv+0x500> 8001c0e: e697 b.n 8001940 <__aeabi_ddiv+0x230> 8001c10: 1e83 subs r3, r0, #2 8001c12: 4464 add r4, ip 8001c14: e694 b.n 8001940 <__aeabi_ddiv+0x230> 8001c16: 46ac mov ip, r5 8001c18: 4461 add r1, ip 8001c1a: 3f01 subs r7, #1 8001c1c: 428d cmp r5, r1 8001c1e: d900 bls.n 8001c22 <__aeabi_ddiv+0x512> 8001c20: e680 b.n 8001924 <__aeabi_ddiv+0x214> 8001c22: 428a cmp r2, r1 8001c24: d800 bhi.n 8001c28 <__aeabi_ddiv+0x518> 8001c26: e67d b.n 8001924 <__aeabi_ddiv+0x214> 8001c28: 1e87 subs r7, r0, #2 8001c2a: 4461 add r1, ip 8001c2c: e67a b.n 8001924 <__aeabi_ddiv+0x214> 8001c2e: 4285 cmp r5, r0 8001c30: d000 beq.n 8001c34 <__aeabi_ddiv+0x524> 8001c32: e65f b.n 80018f4 <__aeabi_ddiv+0x1e4> 8001c34: 45b9 cmp r9, r7 8001c36: d900 bls.n 8001c3a <__aeabi_ddiv+0x52a> 8001c38: e65c b.n 80018f4 <__aeabi_ddiv+0x1e4> 8001c3a: e656 b.n 80018ea <__aeabi_ddiv+0x1da> 8001c3c: 42a2 cmp r2, r4 8001c3e: d800 bhi.n 8001c42 <__aeabi_ddiv+0x532> 8001c40: e61a b.n 8001878 <__aeabi_ddiv+0x168> 8001c42: 1e83 subs r3, r0, #2 8001c44: 4464 add r4, ip 8001c46: e617 b.n 8001878 <__aeabi_ddiv+0x168> 8001c48: 428a cmp r2, r1 8001c4a: d800 bhi.n 8001c4e <__aeabi_ddiv+0x53e> 8001c4c: e600 b.n 8001850 <__aeabi_ddiv+0x140> 8001c4e: 46ac mov ip, r5 8001c50: 1e83 subs r3, r0, #2 8001c52: 4698 mov r8, r3 8001c54: 4461 add r1, ip 8001c56: e5fb b.n 8001850 <__aeabi_ddiv+0x140> 8001c58: 4837 ldr r0, [pc, #220] @ (8001d38 <__aeabi_ddiv+0x628>) 8001c5a: 0014 movs r4, r2 8001c5c: 4450 add r0, sl 8001c5e: 4082 lsls r2, r0 8001c60: 465b mov r3, fp 8001c62: 0017 movs r7, r2 8001c64: 4083 lsls r3, r0 8001c66: 40cc lsrs r4, r1 8001c68: 1e7a subs r2, r7, #1 8001c6a: 4197 sbcs r7, r2 8001c6c: 4323 orrs r3, r4 8001c6e: 433b orrs r3, r7 8001c70: 001a movs r2, r3 8001c72: 465b mov r3, fp 8001c74: 40cb lsrs r3, r1 8001c76: 0751 lsls r1, r2, #29 8001c78: d009 beq.n 8001c8e <__aeabi_ddiv+0x57e> 8001c7a: 210f movs r1, #15 8001c7c: 4011 ands r1, r2 8001c7e: 2904 cmp r1, #4 8001c80: d005 beq.n 8001c8e <__aeabi_ddiv+0x57e> 8001c82: 1d11 adds r1, r2, #4 8001c84: 4291 cmp r1, r2 8001c86: 4192 sbcs r2, r2 8001c88: 4252 negs r2, r2 8001c8a: 189b adds r3, r3, r2 8001c8c: 000a movs r2, r1 8001c8e: 0219 lsls r1, r3, #8 8001c90: d400 bmi.n 8001c94 <__aeabi_ddiv+0x584> 8001c92: e755 b.n 8001b40 <__aeabi_ddiv+0x430> 8001c94: 2200 movs r2, #0 8001c96: 2301 movs r3, #1 8001c98: 2400 movs r4, #0 8001c9a: 4690 mov r8, r2 8001c9c: e598 b.n 80017d0 <__aeabi_ddiv+0xc0> 8001c9e: 000a movs r2, r1 8001ca0: 42bc cmp r4, r7 8001ca2: d000 beq.n 8001ca6 <__aeabi_ddiv+0x596> 8001ca4: e66e b.n 8001984 <__aeabi_ddiv+0x274> 8001ca6: 454b cmp r3, r9 8001ca8: d000 beq.n 8001cac <__aeabi_ddiv+0x59c> 8001caa: e66b b.n 8001984 <__aeabi_ddiv+0x274> 8001cac: e66c b.n 8001988 <__aeabi_ddiv+0x278> 8001cae: 4b23 ldr r3, [pc, #140] @ (8001d3c <__aeabi_ddiv+0x62c>) 8001cb0: 4a23 ldr r2, [pc, #140] @ (8001d40 <__aeabi_ddiv+0x630>) 8001cb2: 4453 add r3, sl 8001cb4: 4592 cmp sl, r2 8001cb6: da00 bge.n 8001cba <__aeabi_ddiv+0x5aa> 8001cb8: e718 b.n 8001aec <__aeabi_ddiv+0x3dc> 8001cba: 2101 movs r1, #1 8001cbc: 4249 negs r1, r1 8001cbe: 1d0a adds r2, r1, #4 8001cc0: 428a cmp r2, r1 8001cc2: 4189 sbcs r1, r1 8001cc4: 4249 negs r1, r1 8001cc6: 448b add fp, r1 8001cc8: e666 b.n 8001998 <__aeabi_ddiv+0x288> 8001cca: 210f movs r1, #15 8001ccc: 4011 ands r1, r2 8001cce: 2904 cmp r1, #4 8001cd0: d100 bne.n 8001cd4 <__aeabi_ddiv+0x5c4> 8001cd2: e661 b.n 8001998 <__aeabi_ddiv+0x288> 8001cd4: 0011 movs r1, r2 8001cd6: e7f2 b.n 8001cbe <__aeabi_ddiv+0x5ae> 8001cd8: 42bc cmp r4, r7 8001cda: d800 bhi.n 8001cde <__aeabi_ddiv+0x5ce> 8001cdc: e60a b.n 80018f4 <__aeabi_ddiv+0x1e4> 8001cde: 2302 movs r3, #2 8001ce0: 425b negs r3, r3 8001ce2: 469c mov ip, r3 8001ce4: 9900 ldr r1, [sp, #0] 8001ce6: 444f add r7, r9 8001ce8: 454f cmp r7, r9 8001cea: 419b sbcs r3, r3 8001cec: 44e3 add fp, ip 8001cee: 468c mov ip, r1 8001cf0: 425b negs r3, r3 8001cf2: 4463 add r3, ip 8001cf4: 18c0 adds r0, r0, r3 8001cf6: e5ff b.n 80018f8 <__aeabi_ddiv+0x1e8> 8001cf8: 4649 mov r1, r9 8001cfa: 9d00 ldr r5, [sp, #0] 8001cfc: 0048 lsls r0, r1, #1 8001cfe: 4548 cmp r0, r9 8001d00: 4189 sbcs r1, r1 8001d02: 46ac mov ip, r5 8001d04: 4249 negs r1, r1 8001d06: 4461 add r1, ip 8001d08: 4681 mov r9, r0 8001d0a: 3a02 subs r2, #2 8001d0c: 1864 adds r4, r4, r1 8001d0e: e7c7 b.n 8001ca0 <__aeabi_ddiv+0x590> 8001d10: 2480 movs r4, #128 @ 0x80 8001d12: 465b mov r3, fp 8001d14: 0324 lsls r4, r4, #12 8001d16: 431c orrs r4, r3 8001d18: 0324 lsls r4, r4, #12 8001d1a: 4690 mov r8, r2 8001d1c: 4b04 ldr r3, [pc, #16] @ (8001d30 <__aeabi_ddiv+0x620>) 8001d1e: 0b24 lsrs r4, r4, #12 8001d20: e556 b.n 80017d0 <__aeabi_ddiv+0xc0> 8001d22: 4599 cmp r9, r3 8001d24: d3e8 bcc.n 8001cf8 <__aeabi_ddiv+0x5e8> 8001d26: 000a movs r2, r1 8001d28: e7bd b.n 8001ca6 <__aeabi_ddiv+0x596> 8001d2a: 2300 movs r3, #0 8001d2c: e708 b.n 8001b40 <__aeabi_ddiv+0x430> 8001d2e: 46c0 nop @ (mov r8, r8) 8001d30: 000007ff .word 0x000007ff 8001d34: 0000043e .word 0x0000043e 8001d38: 0000041e .word 0x0000041e 8001d3c: 000003ff .word 0x000003ff 8001d40: fffffc02 .word 0xfffffc02 08001d44 <__eqdf2>: 8001d44: b5f0 push {r4, r5, r6, r7, lr} 8001d46: 4657 mov r7, sl 8001d48: 46de mov lr, fp 8001d4a: 464e mov r6, r9 8001d4c: 4645 mov r5, r8 8001d4e: b5e0 push {r5, r6, r7, lr} 8001d50: 000d movs r5, r1 8001d52: 0004 movs r4, r0 8001d54: 0fe8 lsrs r0, r5, #31 8001d56: 4683 mov fp, r0 8001d58: 0309 lsls r1, r1, #12 8001d5a: 0fd8 lsrs r0, r3, #31 8001d5c: 0b09 lsrs r1, r1, #12 8001d5e: 4682 mov sl, r0 8001d60: 4819 ldr r0, [pc, #100] @ (8001dc8 <__eqdf2+0x84>) 8001d62: 468c mov ip, r1 8001d64: 031f lsls r7, r3, #12 8001d66: 0069 lsls r1, r5, #1 8001d68: 005e lsls r6, r3, #1 8001d6a: 0d49 lsrs r1, r1, #21 8001d6c: 0b3f lsrs r7, r7, #12 8001d6e: 0d76 lsrs r6, r6, #21 8001d70: 4281 cmp r1, r0 8001d72: d018 beq.n 8001da6 <__eqdf2+0x62> 8001d74: 4286 cmp r6, r0 8001d76: d00f beq.n 8001d98 <__eqdf2+0x54> 8001d78: 2001 movs r0, #1 8001d7a: 42b1 cmp r1, r6 8001d7c: d10d bne.n 8001d9a <__eqdf2+0x56> 8001d7e: 45bc cmp ip, r7 8001d80: d10b bne.n 8001d9a <__eqdf2+0x56> 8001d82: 4294 cmp r4, r2 8001d84: d109 bne.n 8001d9a <__eqdf2+0x56> 8001d86: 45d3 cmp fp, sl 8001d88: d01c beq.n 8001dc4 <__eqdf2+0x80> 8001d8a: 2900 cmp r1, #0 8001d8c: d105 bne.n 8001d9a <__eqdf2+0x56> 8001d8e: 4660 mov r0, ip 8001d90: 4320 orrs r0, r4 8001d92: 1e43 subs r3, r0, #1 8001d94: 4198 sbcs r0, r3 8001d96: e000 b.n 8001d9a <__eqdf2+0x56> 8001d98: 2001 movs r0, #1 8001d9a: bcf0 pop {r4, r5, r6, r7} 8001d9c: 46bb mov fp, r7 8001d9e: 46b2 mov sl, r6 8001da0: 46a9 mov r9, r5 8001da2: 46a0 mov r8, r4 8001da4: bdf0 pop {r4, r5, r6, r7, pc} 8001da6: 2001 movs r0, #1 8001da8: 428e cmp r6, r1 8001daa: d1f6 bne.n 8001d9a <__eqdf2+0x56> 8001dac: 4661 mov r1, ip 8001dae: 4339 orrs r1, r7 8001db0: 000f movs r7, r1 8001db2: 4317 orrs r7, r2 8001db4: 4327 orrs r7, r4 8001db6: d1f0 bne.n 8001d9a <__eqdf2+0x56> 8001db8: 465b mov r3, fp 8001dba: 4652 mov r2, sl 8001dbc: 1a98 subs r0, r3, r2 8001dbe: 1e43 subs r3, r0, #1 8001dc0: 4198 sbcs r0, r3 8001dc2: e7ea b.n 8001d9a <__eqdf2+0x56> 8001dc4: 2000 movs r0, #0 8001dc6: e7e8 b.n 8001d9a <__eqdf2+0x56> 8001dc8: 000007ff .word 0x000007ff 08001dcc <__gedf2>: 8001dcc: b5f0 push {r4, r5, r6, r7, lr} 8001dce: 4657 mov r7, sl 8001dd0: 464e mov r6, r9 8001dd2: 4645 mov r5, r8 8001dd4: 46de mov lr, fp 8001dd6: b5e0 push {r5, r6, r7, lr} 8001dd8: 000d movs r5, r1 8001dda: 030f lsls r7, r1, #12 8001ddc: 0b39 lsrs r1, r7, #12 8001dde: b083 sub sp, #12 8001de0: 0004 movs r4, r0 8001de2: 4680 mov r8, r0 8001de4: 9101 str r1, [sp, #4] 8001de6: 0058 lsls r0, r3, #1 8001de8: 0fe9 lsrs r1, r5, #31 8001dea: 4f31 ldr r7, [pc, #196] @ (8001eb0 <__gedf2+0xe4>) 8001dec: 0d40 lsrs r0, r0, #21 8001dee: 468c mov ip, r1 8001df0: 006e lsls r6, r5, #1 8001df2: 0319 lsls r1, r3, #12 8001df4: 4682 mov sl, r0 8001df6: 4691 mov r9, r2 8001df8: 0d76 lsrs r6, r6, #21 8001dfa: 0b09 lsrs r1, r1, #12 8001dfc: 0fd8 lsrs r0, r3, #31 8001dfe: 42be cmp r6, r7 8001e00: d01f beq.n 8001e42 <__gedf2+0x76> 8001e02: 45ba cmp sl, r7 8001e04: d00f beq.n 8001e26 <__gedf2+0x5a> 8001e06: 2e00 cmp r6, #0 8001e08: d12f bne.n 8001e6a <__gedf2+0x9e> 8001e0a: 4655 mov r5, sl 8001e0c: 9e01 ldr r6, [sp, #4] 8001e0e: 4334 orrs r4, r6 8001e10: 2d00 cmp r5, #0 8001e12: d127 bne.n 8001e64 <__gedf2+0x98> 8001e14: 430a orrs r2, r1 8001e16: d03a beq.n 8001e8e <__gedf2+0xc2> 8001e18: 2c00 cmp r4, #0 8001e1a: d145 bne.n 8001ea8 <__gedf2+0xdc> 8001e1c: 2800 cmp r0, #0 8001e1e: d11a bne.n 8001e56 <__gedf2+0x8a> 8001e20: 2001 movs r0, #1 8001e22: 4240 negs r0, r0 8001e24: e017 b.n 8001e56 <__gedf2+0x8a> 8001e26: 4311 orrs r1, r2 8001e28: d13b bne.n 8001ea2 <__gedf2+0xd6> 8001e2a: 2e00 cmp r6, #0 8001e2c: d102 bne.n 8001e34 <__gedf2+0x68> 8001e2e: 9f01 ldr r7, [sp, #4] 8001e30: 4327 orrs r7, r4 8001e32: d0f3 beq.n 8001e1c <__gedf2+0x50> 8001e34: 4584 cmp ip, r0 8001e36: d109 bne.n 8001e4c <__gedf2+0x80> 8001e38: 4663 mov r3, ip 8001e3a: 2b00 cmp r3, #0 8001e3c: d0f0 beq.n 8001e20 <__gedf2+0x54> 8001e3e: 4660 mov r0, ip 8001e40: e009 b.n 8001e56 <__gedf2+0x8a> 8001e42: 9f01 ldr r7, [sp, #4] 8001e44: 4327 orrs r7, r4 8001e46: d12c bne.n 8001ea2 <__gedf2+0xd6> 8001e48: 45b2 cmp sl, r6 8001e4a: d024 beq.n 8001e96 <__gedf2+0xca> 8001e4c: 4663 mov r3, ip 8001e4e: 2002 movs r0, #2 8001e50: 3b01 subs r3, #1 8001e52: 4018 ands r0, r3 8001e54: 3801 subs r0, #1 8001e56: b003 add sp, #12 8001e58: bcf0 pop {r4, r5, r6, r7} 8001e5a: 46bb mov fp, r7 8001e5c: 46b2 mov sl, r6 8001e5e: 46a9 mov r9, r5 8001e60: 46a0 mov r8, r4 8001e62: bdf0 pop {r4, r5, r6, r7, pc} 8001e64: 2c00 cmp r4, #0 8001e66: d0d9 beq.n 8001e1c <__gedf2+0x50> 8001e68: e7e4 b.n 8001e34 <__gedf2+0x68> 8001e6a: 4654 mov r4, sl 8001e6c: 2c00 cmp r4, #0 8001e6e: d0ed beq.n 8001e4c <__gedf2+0x80> 8001e70: 4584 cmp ip, r0 8001e72: d1eb bne.n 8001e4c <__gedf2+0x80> 8001e74: 4556 cmp r6, sl 8001e76: dce9 bgt.n 8001e4c <__gedf2+0x80> 8001e78: dbde blt.n 8001e38 <__gedf2+0x6c> 8001e7a: 9b01 ldr r3, [sp, #4] 8001e7c: 428b cmp r3, r1 8001e7e: d8e5 bhi.n 8001e4c <__gedf2+0x80> 8001e80: d1da bne.n 8001e38 <__gedf2+0x6c> 8001e82: 45c8 cmp r8, r9 8001e84: d8e2 bhi.n 8001e4c <__gedf2+0x80> 8001e86: 2000 movs r0, #0 8001e88: 45c8 cmp r8, r9 8001e8a: d2e4 bcs.n 8001e56 <__gedf2+0x8a> 8001e8c: e7d4 b.n 8001e38 <__gedf2+0x6c> 8001e8e: 2000 movs r0, #0 8001e90: 2c00 cmp r4, #0 8001e92: d0e0 beq.n 8001e56 <__gedf2+0x8a> 8001e94: e7da b.n 8001e4c <__gedf2+0x80> 8001e96: 4311 orrs r1, r2 8001e98: d103 bne.n 8001ea2 <__gedf2+0xd6> 8001e9a: 4584 cmp ip, r0 8001e9c: d1d6 bne.n 8001e4c <__gedf2+0x80> 8001e9e: 2000 movs r0, #0 8001ea0: e7d9 b.n 8001e56 <__gedf2+0x8a> 8001ea2: 2002 movs r0, #2 8001ea4: 4240 negs r0, r0 8001ea6: e7d6 b.n 8001e56 <__gedf2+0x8a> 8001ea8: 4584 cmp ip, r0 8001eaa: d0e6 beq.n 8001e7a <__gedf2+0xae> 8001eac: e7ce b.n 8001e4c <__gedf2+0x80> 8001eae: 46c0 nop @ (mov r8, r8) 8001eb0: 000007ff .word 0x000007ff 08001eb4 <__ledf2>: 8001eb4: b5f0 push {r4, r5, r6, r7, lr} 8001eb6: 4657 mov r7, sl 8001eb8: 464e mov r6, r9 8001eba: 4645 mov r5, r8 8001ebc: 46de mov lr, fp 8001ebe: b5e0 push {r5, r6, r7, lr} 8001ec0: 000d movs r5, r1 8001ec2: 030f lsls r7, r1, #12 8001ec4: 0004 movs r4, r0 8001ec6: 4680 mov r8, r0 8001ec8: 0fe8 lsrs r0, r5, #31 8001eca: 0b39 lsrs r1, r7, #12 8001ecc: 4684 mov ip, r0 8001ece: b083 sub sp, #12 8001ed0: 0058 lsls r0, r3, #1 8001ed2: 4f30 ldr r7, [pc, #192] @ (8001f94 <__ledf2+0xe0>) 8001ed4: 0d40 lsrs r0, r0, #21 8001ed6: 9101 str r1, [sp, #4] 8001ed8: 031e lsls r6, r3, #12 8001eda: 0069 lsls r1, r5, #1 8001edc: 4682 mov sl, r0 8001ede: 4691 mov r9, r2 8001ee0: 0d49 lsrs r1, r1, #21 8001ee2: 0b36 lsrs r6, r6, #12 8001ee4: 0fd8 lsrs r0, r3, #31 8001ee6: 42b9 cmp r1, r7 8001ee8: d020 beq.n 8001f2c <__ledf2+0x78> 8001eea: 45ba cmp sl, r7 8001eec: d00f beq.n 8001f0e <__ledf2+0x5a> 8001eee: 2900 cmp r1, #0 8001ef0: d12b bne.n 8001f4a <__ledf2+0x96> 8001ef2: 9901 ldr r1, [sp, #4] 8001ef4: 430c orrs r4, r1 8001ef6: 4651 mov r1, sl 8001ef8: 2900 cmp r1, #0 8001efa: d137 bne.n 8001f6c <__ledf2+0xb8> 8001efc: 4332 orrs r2, r6 8001efe: d038 beq.n 8001f72 <__ledf2+0xbe> 8001f00: 2c00 cmp r4, #0 8001f02: d144 bne.n 8001f8e <__ledf2+0xda> 8001f04: 2800 cmp r0, #0 8001f06: d119 bne.n 8001f3c <__ledf2+0x88> 8001f08: 2001 movs r0, #1 8001f0a: 4240 negs r0, r0 8001f0c: e016 b.n 8001f3c <__ledf2+0x88> 8001f0e: 4316 orrs r6, r2 8001f10: d113 bne.n 8001f3a <__ledf2+0x86> 8001f12: 2900 cmp r1, #0 8001f14: d102 bne.n 8001f1c <__ledf2+0x68> 8001f16: 9f01 ldr r7, [sp, #4] 8001f18: 4327 orrs r7, r4 8001f1a: d0f3 beq.n 8001f04 <__ledf2+0x50> 8001f1c: 4584 cmp ip, r0 8001f1e: d020 beq.n 8001f62 <__ledf2+0xae> 8001f20: 4663 mov r3, ip 8001f22: 2002 movs r0, #2 8001f24: 3b01 subs r3, #1 8001f26: 4018 ands r0, r3 8001f28: 3801 subs r0, #1 8001f2a: e007 b.n 8001f3c <__ledf2+0x88> 8001f2c: 9f01 ldr r7, [sp, #4] 8001f2e: 4327 orrs r7, r4 8001f30: d103 bne.n 8001f3a <__ledf2+0x86> 8001f32: 458a cmp sl, r1 8001f34: d1f4 bne.n 8001f20 <__ledf2+0x6c> 8001f36: 4316 orrs r6, r2 8001f38: d01f beq.n 8001f7a <__ledf2+0xc6> 8001f3a: 2002 movs r0, #2 8001f3c: b003 add sp, #12 8001f3e: bcf0 pop {r4, r5, r6, r7} 8001f40: 46bb mov fp, r7 8001f42: 46b2 mov sl, r6 8001f44: 46a9 mov r9, r5 8001f46: 46a0 mov r8, r4 8001f48: bdf0 pop {r4, r5, r6, r7, pc} 8001f4a: 4654 mov r4, sl 8001f4c: 2c00 cmp r4, #0 8001f4e: d0e7 beq.n 8001f20 <__ledf2+0x6c> 8001f50: 4584 cmp ip, r0 8001f52: d1e5 bne.n 8001f20 <__ledf2+0x6c> 8001f54: 4551 cmp r1, sl 8001f56: dce3 bgt.n 8001f20 <__ledf2+0x6c> 8001f58: db03 blt.n 8001f62 <__ledf2+0xae> 8001f5a: 9b01 ldr r3, [sp, #4] 8001f5c: 42b3 cmp r3, r6 8001f5e: d8df bhi.n 8001f20 <__ledf2+0x6c> 8001f60: d00f beq.n 8001f82 <__ledf2+0xce> 8001f62: 4663 mov r3, ip 8001f64: 2b00 cmp r3, #0 8001f66: d0cf beq.n 8001f08 <__ledf2+0x54> 8001f68: 4660 mov r0, ip 8001f6a: e7e7 b.n 8001f3c <__ledf2+0x88> 8001f6c: 2c00 cmp r4, #0 8001f6e: d0c9 beq.n 8001f04 <__ledf2+0x50> 8001f70: e7d4 b.n 8001f1c <__ledf2+0x68> 8001f72: 2000 movs r0, #0 8001f74: 2c00 cmp r4, #0 8001f76: d0e1 beq.n 8001f3c <__ledf2+0x88> 8001f78: e7d2 b.n 8001f20 <__ledf2+0x6c> 8001f7a: 4584 cmp ip, r0 8001f7c: d1d0 bne.n 8001f20 <__ledf2+0x6c> 8001f7e: 2000 movs r0, #0 8001f80: e7dc b.n 8001f3c <__ledf2+0x88> 8001f82: 45c8 cmp r8, r9 8001f84: d8cc bhi.n 8001f20 <__ledf2+0x6c> 8001f86: 2000 movs r0, #0 8001f88: 45c8 cmp r8, r9 8001f8a: d2d7 bcs.n 8001f3c <__ledf2+0x88> 8001f8c: e7e9 b.n 8001f62 <__ledf2+0xae> 8001f8e: 4584 cmp ip, r0 8001f90: d0e3 beq.n 8001f5a <__ledf2+0xa6> 8001f92: e7c5 b.n 8001f20 <__ledf2+0x6c> 8001f94: 000007ff .word 0x000007ff 08001f98 <__aeabi_dmul>: 8001f98: b5f0 push {r4, r5, r6, r7, lr} 8001f9a: 4657 mov r7, sl 8001f9c: 46de mov lr, fp 8001f9e: 464e mov r6, r9 8001fa0: 4645 mov r5, r8 8001fa2: b5e0 push {r5, r6, r7, lr} 8001fa4: 001f movs r7, r3 8001fa6: 030b lsls r3, r1, #12 8001fa8: 0b1b lsrs r3, r3, #12 8001faa: 0016 movs r6, r2 8001fac: 469a mov sl, r3 8001fae: 0fca lsrs r2, r1, #31 8001fb0: 004b lsls r3, r1, #1 8001fb2: 0004 movs r4, r0 8001fb4: 4693 mov fp, r2 8001fb6: b087 sub sp, #28 8001fb8: 0d5b lsrs r3, r3, #21 8001fba: d100 bne.n 8001fbe <__aeabi_dmul+0x26> 8001fbc: e0d5 b.n 800216a <__aeabi_dmul+0x1d2> 8001fbe: 4abb ldr r2, [pc, #748] @ (80022ac <__aeabi_dmul+0x314>) 8001fc0: 4293 cmp r3, r2 8001fc2: d100 bne.n 8001fc6 <__aeabi_dmul+0x2e> 8001fc4: e0f8 b.n 80021b8 <__aeabi_dmul+0x220> 8001fc6: 4651 mov r1, sl 8001fc8: 0f42 lsrs r2, r0, #29 8001fca: 00c9 lsls r1, r1, #3 8001fcc: 430a orrs r2, r1 8001fce: 2180 movs r1, #128 @ 0x80 8001fd0: 0409 lsls r1, r1, #16 8001fd2: 4311 orrs r1, r2 8001fd4: 00c2 lsls r2, r0, #3 8001fd6: 4691 mov r9, r2 8001fd8: 4ab5 ldr r2, [pc, #724] @ (80022b0 <__aeabi_dmul+0x318>) 8001fda: 468a mov sl, r1 8001fdc: 189d adds r5, r3, r2 8001fde: 2300 movs r3, #0 8001fe0: 4698 mov r8, r3 8001fe2: 9302 str r3, [sp, #8] 8001fe4: 033c lsls r4, r7, #12 8001fe6: 007b lsls r3, r7, #1 8001fe8: 0ffa lsrs r2, r7, #31 8001fea: 0030 movs r0, r6 8001fec: 0b24 lsrs r4, r4, #12 8001fee: 0d5b lsrs r3, r3, #21 8001ff0: 9200 str r2, [sp, #0] 8001ff2: d100 bne.n 8001ff6 <__aeabi_dmul+0x5e> 8001ff4: e096 b.n 8002124 <__aeabi_dmul+0x18c> 8001ff6: 4aad ldr r2, [pc, #692] @ (80022ac <__aeabi_dmul+0x314>) 8001ff8: 4293 cmp r3, r2 8001ffa: d031 beq.n 8002060 <__aeabi_dmul+0xc8> 8001ffc: 0f72 lsrs r2, r6, #29 8001ffe: 00e4 lsls r4, r4, #3 8002000: 4322 orrs r2, r4 8002002: 2480 movs r4, #128 @ 0x80 8002004: 0424 lsls r4, r4, #16 8002006: 4314 orrs r4, r2 8002008: 4aa9 ldr r2, [pc, #676] @ (80022b0 <__aeabi_dmul+0x318>) 800200a: 00f0 lsls r0, r6, #3 800200c: 4694 mov ip, r2 800200e: 4463 add r3, ip 8002010: 195b adds r3, r3, r5 8002012: 1c5a adds r2, r3, #1 8002014: 9201 str r2, [sp, #4] 8002016: 4642 mov r2, r8 8002018: 2600 movs r6, #0 800201a: 2a0a cmp r2, #10 800201c: dc42 bgt.n 80020a4 <__aeabi_dmul+0x10c> 800201e: 465a mov r2, fp 8002020: 9900 ldr r1, [sp, #0] 8002022: 404a eors r2, r1 8002024: 4693 mov fp, r2 8002026: 4642 mov r2, r8 8002028: 2a02 cmp r2, #2 800202a: dc32 bgt.n 8002092 <__aeabi_dmul+0xfa> 800202c: 3a01 subs r2, #1 800202e: 2a01 cmp r2, #1 8002030: d900 bls.n 8002034 <__aeabi_dmul+0x9c> 8002032: e149 b.n 80022c8 <__aeabi_dmul+0x330> 8002034: 2e02 cmp r6, #2 8002036: d100 bne.n 800203a <__aeabi_dmul+0xa2> 8002038: e0ca b.n 80021d0 <__aeabi_dmul+0x238> 800203a: 2e01 cmp r6, #1 800203c: d13d bne.n 80020ba <__aeabi_dmul+0x122> 800203e: 2300 movs r3, #0 8002040: 2400 movs r4, #0 8002042: 2200 movs r2, #0 8002044: 0010 movs r0, r2 8002046: 465a mov r2, fp 8002048: 051b lsls r3, r3, #20 800204a: 4323 orrs r3, r4 800204c: 07d2 lsls r2, r2, #31 800204e: 4313 orrs r3, r2 8002050: 0019 movs r1, r3 8002052: b007 add sp, #28 8002054: bcf0 pop {r4, r5, r6, r7} 8002056: 46bb mov fp, r7 8002058: 46b2 mov sl, r6 800205a: 46a9 mov r9, r5 800205c: 46a0 mov r8, r4 800205e: bdf0 pop {r4, r5, r6, r7, pc} 8002060: 4b92 ldr r3, [pc, #584] @ (80022ac <__aeabi_dmul+0x314>) 8002062: 4326 orrs r6, r4 8002064: 18eb adds r3, r5, r3 8002066: 2e00 cmp r6, #0 8002068: d100 bne.n 800206c <__aeabi_dmul+0xd4> 800206a: e0bb b.n 80021e4 <__aeabi_dmul+0x24c> 800206c: 2203 movs r2, #3 800206e: 4641 mov r1, r8 8002070: 4311 orrs r1, r2 8002072: 465a mov r2, fp 8002074: 4688 mov r8, r1 8002076: 9900 ldr r1, [sp, #0] 8002078: 404a eors r2, r1 800207a: 2180 movs r1, #128 @ 0x80 800207c: 0109 lsls r1, r1, #4 800207e: 468c mov ip, r1 8002080: 0029 movs r1, r5 8002082: 4461 add r1, ip 8002084: 9101 str r1, [sp, #4] 8002086: 4641 mov r1, r8 8002088: 290a cmp r1, #10 800208a: dd00 ble.n 800208e <__aeabi_dmul+0xf6> 800208c: e233 b.n 80024f6 <__aeabi_dmul+0x55e> 800208e: 4693 mov fp, r2 8002090: 2603 movs r6, #3 8002092: 4642 mov r2, r8 8002094: 2701 movs r7, #1 8002096: 4097 lsls r7, r2 8002098: 21a6 movs r1, #166 @ 0xa6 800209a: 003a movs r2, r7 800209c: 00c9 lsls r1, r1, #3 800209e: 400a ands r2, r1 80020a0: 420f tst r7, r1 80020a2: d031 beq.n 8002108 <__aeabi_dmul+0x170> 80020a4: 9e02 ldr r6, [sp, #8] 80020a6: 2e02 cmp r6, #2 80020a8: d100 bne.n 80020ac <__aeabi_dmul+0x114> 80020aa: e235 b.n 8002518 <__aeabi_dmul+0x580> 80020ac: 2e03 cmp r6, #3 80020ae: d100 bne.n 80020b2 <__aeabi_dmul+0x11a> 80020b0: e1d2 b.n 8002458 <__aeabi_dmul+0x4c0> 80020b2: 4654 mov r4, sl 80020b4: 4648 mov r0, r9 80020b6: 2e01 cmp r6, #1 80020b8: d0c1 beq.n 800203e <__aeabi_dmul+0xa6> 80020ba: 9a01 ldr r2, [sp, #4] 80020bc: 4b7d ldr r3, [pc, #500] @ (80022b4 <__aeabi_dmul+0x31c>) 80020be: 4694 mov ip, r2 80020c0: 4463 add r3, ip 80020c2: 2b00 cmp r3, #0 80020c4: dc00 bgt.n 80020c8 <__aeabi_dmul+0x130> 80020c6: e0c0 b.n 800224a <__aeabi_dmul+0x2b2> 80020c8: 0742 lsls r2, r0, #29 80020ca: d009 beq.n 80020e0 <__aeabi_dmul+0x148> 80020cc: 220f movs r2, #15 80020ce: 4002 ands r2, r0 80020d0: 2a04 cmp r2, #4 80020d2: d005 beq.n 80020e0 <__aeabi_dmul+0x148> 80020d4: 1d02 adds r2, r0, #4 80020d6: 4282 cmp r2, r0 80020d8: 4180 sbcs r0, r0 80020da: 4240 negs r0, r0 80020dc: 1824 adds r4, r4, r0 80020de: 0010 movs r0, r2 80020e0: 01e2 lsls r2, r4, #7 80020e2: d506 bpl.n 80020f2 <__aeabi_dmul+0x15a> 80020e4: 4b74 ldr r3, [pc, #464] @ (80022b8 <__aeabi_dmul+0x320>) 80020e6: 9a01 ldr r2, [sp, #4] 80020e8: 401c ands r4, r3 80020ea: 2380 movs r3, #128 @ 0x80 80020ec: 4694 mov ip, r2 80020ee: 00db lsls r3, r3, #3 80020f0: 4463 add r3, ip 80020f2: 4a72 ldr r2, [pc, #456] @ (80022bc <__aeabi_dmul+0x324>) 80020f4: 4293 cmp r3, r2 80020f6: dc6b bgt.n 80021d0 <__aeabi_dmul+0x238> 80020f8: 0762 lsls r2, r4, #29 80020fa: 08c0 lsrs r0, r0, #3 80020fc: 0264 lsls r4, r4, #9 80020fe: 055b lsls r3, r3, #21 8002100: 4302 orrs r2, r0 8002102: 0b24 lsrs r4, r4, #12 8002104: 0d5b lsrs r3, r3, #21 8002106: e79d b.n 8002044 <__aeabi_dmul+0xac> 8002108: 2190 movs r1, #144 @ 0x90 800210a: 0089 lsls r1, r1, #2 800210c: 420f tst r7, r1 800210e: d163 bne.n 80021d8 <__aeabi_dmul+0x240> 8002110: 2288 movs r2, #136 @ 0x88 8002112: 423a tst r2, r7 8002114: d100 bne.n 8002118 <__aeabi_dmul+0x180> 8002116: e0d7 b.n 80022c8 <__aeabi_dmul+0x330> 8002118: 9b00 ldr r3, [sp, #0] 800211a: 46a2 mov sl, r4 800211c: 469b mov fp, r3 800211e: 4681 mov r9, r0 8002120: 9602 str r6, [sp, #8] 8002122: e7bf b.n 80020a4 <__aeabi_dmul+0x10c> 8002124: 0023 movs r3, r4 8002126: 4333 orrs r3, r6 8002128: d100 bne.n 800212c <__aeabi_dmul+0x194> 800212a: e07f b.n 800222c <__aeabi_dmul+0x294> 800212c: 2c00 cmp r4, #0 800212e: d100 bne.n 8002132 <__aeabi_dmul+0x19a> 8002130: e1ad b.n 800248e <__aeabi_dmul+0x4f6> 8002132: 0020 movs r0, r4 8002134: f000 fe82 bl 8002e3c <__clzsi2> 8002138: 0002 movs r2, r0 800213a: 0003 movs r3, r0 800213c: 3a0b subs r2, #11 800213e: 201d movs r0, #29 8002140: 0019 movs r1, r3 8002142: 1a82 subs r2, r0, r2 8002144: 0030 movs r0, r6 8002146: 3908 subs r1, #8 8002148: 40d0 lsrs r0, r2 800214a: 408c lsls r4, r1 800214c: 4304 orrs r4, r0 800214e: 0030 movs r0, r6 8002150: 4088 lsls r0, r1 8002152: 4a5b ldr r2, [pc, #364] @ (80022c0 <__aeabi_dmul+0x328>) 8002154: 1aeb subs r3, r5, r3 8002156: 4694 mov ip, r2 8002158: 4463 add r3, ip 800215a: 1c5a adds r2, r3, #1 800215c: 9201 str r2, [sp, #4] 800215e: 4642 mov r2, r8 8002160: 2600 movs r6, #0 8002162: 2a0a cmp r2, #10 8002164: dc00 bgt.n 8002168 <__aeabi_dmul+0x1d0> 8002166: e75a b.n 800201e <__aeabi_dmul+0x86> 8002168: e79c b.n 80020a4 <__aeabi_dmul+0x10c> 800216a: 4653 mov r3, sl 800216c: 4303 orrs r3, r0 800216e: 4699 mov r9, r3 8002170: d054 beq.n 800221c <__aeabi_dmul+0x284> 8002172: 4653 mov r3, sl 8002174: 2b00 cmp r3, #0 8002176: d100 bne.n 800217a <__aeabi_dmul+0x1e2> 8002178: e177 b.n 800246a <__aeabi_dmul+0x4d2> 800217a: 4650 mov r0, sl 800217c: f000 fe5e bl 8002e3c <__clzsi2> 8002180: 230b movs r3, #11 8002182: 425b negs r3, r3 8002184: 469c mov ip, r3 8002186: 0002 movs r2, r0 8002188: 4484 add ip, r0 800218a: 0011 movs r1, r2 800218c: 4650 mov r0, sl 800218e: 3908 subs r1, #8 8002190: 4088 lsls r0, r1 8002192: 231d movs r3, #29 8002194: 4680 mov r8, r0 8002196: 4660 mov r0, ip 8002198: 1a1b subs r3, r3, r0 800219a: 0020 movs r0, r4 800219c: 40d8 lsrs r0, r3 800219e: 0003 movs r3, r0 80021a0: 4640 mov r0, r8 80021a2: 4303 orrs r3, r0 80021a4: 469a mov sl, r3 80021a6: 0023 movs r3, r4 80021a8: 408b lsls r3, r1 80021aa: 4699 mov r9, r3 80021ac: 2300 movs r3, #0 80021ae: 4d44 ldr r5, [pc, #272] @ (80022c0 <__aeabi_dmul+0x328>) 80021b0: 4698 mov r8, r3 80021b2: 1aad subs r5, r5, r2 80021b4: 9302 str r3, [sp, #8] 80021b6: e715 b.n 8001fe4 <__aeabi_dmul+0x4c> 80021b8: 4652 mov r2, sl 80021ba: 4302 orrs r2, r0 80021bc: 4691 mov r9, r2 80021be: d126 bne.n 800220e <__aeabi_dmul+0x276> 80021c0: 2200 movs r2, #0 80021c2: 001d movs r5, r3 80021c4: 2302 movs r3, #2 80021c6: 4692 mov sl, r2 80021c8: 3208 adds r2, #8 80021ca: 4690 mov r8, r2 80021cc: 9302 str r3, [sp, #8] 80021ce: e709 b.n 8001fe4 <__aeabi_dmul+0x4c> 80021d0: 2400 movs r4, #0 80021d2: 2200 movs r2, #0 80021d4: 4b35 ldr r3, [pc, #212] @ (80022ac <__aeabi_dmul+0x314>) 80021d6: e735 b.n 8002044 <__aeabi_dmul+0xac> 80021d8: 2300 movs r3, #0 80021da: 2480 movs r4, #128 @ 0x80 80021dc: 469b mov fp, r3 80021de: 0324 lsls r4, r4, #12 80021e0: 4b32 ldr r3, [pc, #200] @ (80022ac <__aeabi_dmul+0x314>) 80021e2: e72f b.n 8002044 <__aeabi_dmul+0xac> 80021e4: 2202 movs r2, #2 80021e6: 4641 mov r1, r8 80021e8: 4311 orrs r1, r2 80021ea: 2280 movs r2, #128 @ 0x80 80021ec: 0112 lsls r2, r2, #4 80021ee: 4694 mov ip, r2 80021f0: 002a movs r2, r5 80021f2: 4462 add r2, ip 80021f4: 4688 mov r8, r1 80021f6: 9201 str r2, [sp, #4] 80021f8: 290a cmp r1, #10 80021fa: dd00 ble.n 80021fe <__aeabi_dmul+0x266> 80021fc: e752 b.n 80020a4 <__aeabi_dmul+0x10c> 80021fe: 465a mov r2, fp 8002200: 2000 movs r0, #0 8002202: 9900 ldr r1, [sp, #0] 8002204: 0004 movs r4, r0 8002206: 404a eors r2, r1 8002208: 4693 mov fp, r2 800220a: 2602 movs r6, #2 800220c: e70b b.n 8002026 <__aeabi_dmul+0x8e> 800220e: 220c movs r2, #12 8002210: 001d movs r5, r3 8002212: 2303 movs r3, #3 8002214: 4681 mov r9, r0 8002216: 4690 mov r8, r2 8002218: 9302 str r3, [sp, #8] 800221a: e6e3 b.n 8001fe4 <__aeabi_dmul+0x4c> 800221c: 2300 movs r3, #0 800221e: 469a mov sl, r3 8002220: 3304 adds r3, #4 8002222: 4698 mov r8, r3 8002224: 3b03 subs r3, #3 8002226: 2500 movs r5, #0 8002228: 9302 str r3, [sp, #8] 800222a: e6db b.n 8001fe4 <__aeabi_dmul+0x4c> 800222c: 4642 mov r2, r8 800222e: 3301 adds r3, #1 8002230: 431a orrs r2, r3 8002232: 002b movs r3, r5 8002234: 4690 mov r8, r2 8002236: 1c5a adds r2, r3, #1 8002238: 9201 str r2, [sp, #4] 800223a: 4642 mov r2, r8 800223c: 2400 movs r4, #0 800223e: 2000 movs r0, #0 8002240: 2601 movs r6, #1 8002242: 2a0a cmp r2, #10 8002244: dc00 bgt.n 8002248 <__aeabi_dmul+0x2b0> 8002246: e6ea b.n 800201e <__aeabi_dmul+0x86> 8002248: e72c b.n 80020a4 <__aeabi_dmul+0x10c> 800224a: 2201 movs r2, #1 800224c: 1ad2 subs r2, r2, r3 800224e: 2a38 cmp r2, #56 @ 0x38 8002250: dd00 ble.n 8002254 <__aeabi_dmul+0x2bc> 8002252: e6f4 b.n 800203e <__aeabi_dmul+0xa6> 8002254: 2a1f cmp r2, #31 8002256: dc00 bgt.n 800225a <__aeabi_dmul+0x2c2> 8002258: e12a b.n 80024b0 <__aeabi_dmul+0x518> 800225a: 211f movs r1, #31 800225c: 4249 negs r1, r1 800225e: 1acb subs r3, r1, r3 8002260: 0021 movs r1, r4 8002262: 40d9 lsrs r1, r3 8002264: 000b movs r3, r1 8002266: 2a20 cmp r2, #32 8002268: d005 beq.n 8002276 <__aeabi_dmul+0x2de> 800226a: 4a16 ldr r2, [pc, #88] @ (80022c4 <__aeabi_dmul+0x32c>) 800226c: 9d01 ldr r5, [sp, #4] 800226e: 4694 mov ip, r2 8002270: 4465 add r5, ip 8002272: 40ac lsls r4, r5 8002274: 4320 orrs r0, r4 8002276: 1e42 subs r2, r0, #1 8002278: 4190 sbcs r0, r2 800227a: 4318 orrs r0, r3 800227c: 2307 movs r3, #7 800227e: 0019 movs r1, r3 8002280: 2400 movs r4, #0 8002282: 4001 ands r1, r0 8002284: 4203 tst r3, r0 8002286: d00c beq.n 80022a2 <__aeabi_dmul+0x30a> 8002288: 230f movs r3, #15 800228a: 4003 ands r3, r0 800228c: 2b04 cmp r3, #4 800228e: d100 bne.n 8002292 <__aeabi_dmul+0x2fa> 8002290: e140 b.n 8002514 <__aeabi_dmul+0x57c> 8002292: 1d03 adds r3, r0, #4 8002294: 4283 cmp r3, r0 8002296: 41a4 sbcs r4, r4 8002298: 0018 movs r0, r3 800229a: 4264 negs r4, r4 800229c: 0761 lsls r1, r4, #29 800229e: 0264 lsls r4, r4, #9 80022a0: 0b24 lsrs r4, r4, #12 80022a2: 08c2 lsrs r2, r0, #3 80022a4: 2300 movs r3, #0 80022a6: 430a orrs r2, r1 80022a8: e6cc b.n 8002044 <__aeabi_dmul+0xac> 80022aa: 46c0 nop @ (mov r8, r8) 80022ac: 000007ff .word 0x000007ff 80022b0: fffffc01 .word 0xfffffc01 80022b4: 000003ff .word 0x000003ff 80022b8: feffffff .word 0xfeffffff 80022bc: 000007fe .word 0x000007fe 80022c0: fffffc0d .word 0xfffffc0d 80022c4: 0000043e .word 0x0000043e 80022c8: 4649 mov r1, r9 80022ca: 464a mov r2, r9 80022cc: 0409 lsls r1, r1, #16 80022ce: 0c09 lsrs r1, r1, #16 80022d0: 000d movs r5, r1 80022d2: 0c16 lsrs r6, r2, #16 80022d4: 0c02 lsrs r2, r0, #16 80022d6: 0400 lsls r0, r0, #16 80022d8: 0c00 lsrs r0, r0, #16 80022da: 4345 muls r5, r0 80022dc: 46ac mov ip, r5 80022de: 0005 movs r5, r0 80022e0: 4375 muls r5, r6 80022e2: 46a8 mov r8, r5 80022e4: 0015 movs r5, r2 80022e6: 000f movs r7, r1 80022e8: 4375 muls r5, r6 80022ea: 9200 str r2, [sp, #0] 80022ec: 9502 str r5, [sp, #8] 80022ee: 002a movs r2, r5 80022f0: 9d00 ldr r5, [sp, #0] 80022f2: 436f muls r7, r5 80022f4: 4665 mov r5, ip 80022f6: 0c2d lsrs r5, r5, #16 80022f8: 46a9 mov r9, r5 80022fa: 4447 add r7, r8 80022fc: 444f add r7, r9 80022fe: 45b8 cmp r8, r7 8002300: d905 bls.n 800230e <__aeabi_dmul+0x376> 8002302: 0015 movs r5, r2 8002304: 2280 movs r2, #128 @ 0x80 8002306: 0252 lsls r2, r2, #9 8002308: 4690 mov r8, r2 800230a: 4445 add r5, r8 800230c: 9502 str r5, [sp, #8] 800230e: 0c3d lsrs r5, r7, #16 8002310: 9503 str r5, [sp, #12] 8002312: 4665 mov r5, ip 8002314: 042d lsls r5, r5, #16 8002316: 043f lsls r7, r7, #16 8002318: 0c2d lsrs r5, r5, #16 800231a: 46ac mov ip, r5 800231c: 003d movs r5, r7 800231e: 4465 add r5, ip 8002320: 9504 str r5, [sp, #16] 8002322: 0c25 lsrs r5, r4, #16 8002324: 0424 lsls r4, r4, #16 8002326: 0c24 lsrs r4, r4, #16 8002328: 46ac mov ip, r5 800232a: 0025 movs r5, r4 800232c: 4375 muls r5, r6 800232e: 46a8 mov r8, r5 8002330: 4665 mov r5, ip 8002332: 000f movs r7, r1 8002334: 4369 muls r1, r5 8002336: 4441 add r1, r8 8002338: 4689 mov r9, r1 800233a: 4367 muls r7, r4 800233c: 0c39 lsrs r1, r7, #16 800233e: 4449 add r1, r9 8002340: 436e muls r6, r5 8002342: 4588 cmp r8, r1 8002344: d903 bls.n 800234e <__aeabi_dmul+0x3b6> 8002346: 2280 movs r2, #128 @ 0x80 8002348: 0252 lsls r2, r2, #9 800234a: 4690 mov r8, r2 800234c: 4446 add r6, r8 800234e: 0c0d lsrs r5, r1, #16 8002350: 46a8 mov r8, r5 8002352: 0035 movs r5, r6 8002354: 4445 add r5, r8 8002356: 9505 str r5, [sp, #20] 8002358: 9d03 ldr r5, [sp, #12] 800235a: 043f lsls r7, r7, #16 800235c: 46a8 mov r8, r5 800235e: 0c3f lsrs r7, r7, #16 8002360: 0409 lsls r1, r1, #16 8002362: 19c9 adds r1, r1, r7 8002364: 4488 add r8, r1 8002366: 4645 mov r5, r8 8002368: 9503 str r5, [sp, #12] 800236a: 4655 mov r5, sl 800236c: 042e lsls r6, r5, #16 800236e: 0c36 lsrs r6, r6, #16 8002370: 0c2f lsrs r7, r5, #16 8002372: 0035 movs r5, r6 8002374: 4345 muls r5, r0 8002376: 4378 muls r0, r7 8002378: 4681 mov r9, r0 800237a: 0038 movs r0, r7 800237c: 46a8 mov r8, r5 800237e: 0c2d lsrs r5, r5, #16 8002380: 46aa mov sl, r5 8002382: 9a00 ldr r2, [sp, #0] 8002384: 4350 muls r0, r2 8002386: 4372 muls r2, r6 8002388: 444a add r2, r9 800238a: 4452 add r2, sl 800238c: 4591 cmp r9, r2 800238e: d903 bls.n 8002398 <__aeabi_dmul+0x400> 8002390: 2580 movs r5, #128 @ 0x80 8002392: 026d lsls r5, r5, #9 8002394: 46a9 mov r9, r5 8002396: 4448 add r0, r9 8002398: 0c15 lsrs r5, r2, #16 800239a: 46a9 mov r9, r5 800239c: 4645 mov r5, r8 800239e: 042d lsls r5, r5, #16 80023a0: 0c2d lsrs r5, r5, #16 80023a2: 46a8 mov r8, r5 80023a4: 4665 mov r5, ip 80023a6: 437d muls r5, r7 80023a8: 0412 lsls r2, r2, #16 80023aa: 4448 add r0, r9 80023ac: 4490 add r8, r2 80023ae: 46a9 mov r9, r5 80023b0: 0032 movs r2, r6 80023b2: 4665 mov r5, ip 80023b4: 4362 muls r2, r4 80023b6: 436e muls r6, r5 80023b8: 437c muls r4, r7 80023ba: 0c17 lsrs r7, r2, #16 80023bc: 1936 adds r6, r6, r4 80023be: 19bf adds r7, r7, r6 80023c0: 42bc cmp r4, r7 80023c2: d903 bls.n 80023cc <__aeabi_dmul+0x434> 80023c4: 2480 movs r4, #128 @ 0x80 80023c6: 0264 lsls r4, r4, #9 80023c8: 46a4 mov ip, r4 80023ca: 44e1 add r9, ip 80023cc: 9c02 ldr r4, [sp, #8] 80023ce: 9e03 ldr r6, [sp, #12] 80023d0: 46a4 mov ip, r4 80023d2: 9d05 ldr r5, [sp, #20] 80023d4: 4466 add r6, ip 80023d6: 428e cmp r6, r1 80023d8: 4189 sbcs r1, r1 80023da: 46ac mov ip, r5 80023dc: 0412 lsls r2, r2, #16 80023de: 043c lsls r4, r7, #16 80023e0: 0c12 lsrs r2, r2, #16 80023e2: 18a2 adds r2, r4, r2 80023e4: 4462 add r2, ip 80023e6: 4249 negs r1, r1 80023e8: 1854 adds r4, r2, r1 80023ea: 4446 add r6, r8 80023ec: 46a4 mov ip, r4 80023ee: 4546 cmp r6, r8 80023f0: 41a4 sbcs r4, r4 80023f2: 4682 mov sl, r0 80023f4: 4264 negs r4, r4 80023f6: 46a0 mov r8, r4 80023f8: 42aa cmp r2, r5 80023fa: 4192 sbcs r2, r2 80023fc: 458c cmp ip, r1 80023fe: 4189 sbcs r1, r1 8002400: 44e2 add sl, ip 8002402: 44d0 add r8, sl 8002404: 4249 negs r1, r1 8002406: 4252 negs r2, r2 8002408: 430a orrs r2, r1 800240a: 45a0 cmp r8, r4 800240c: 41a4 sbcs r4, r4 800240e: 4582 cmp sl, r0 8002410: 4189 sbcs r1, r1 8002412: 4264 negs r4, r4 8002414: 4249 negs r1, r1 8002416: 430c orrs r4, r1 8002418: 4641 mov r1, r8 800241a: 0c3f lsrs r7, r7, #16 800241c: 19d2 adds r2, r2, r7 800241e: 1912 adds r2, r2, r4 8002420: 0dcc lsrs r4, r1, #23 8002422: 9904 ldr r1, [sp, #16] 8002424: 0270 lsls r0, r6, #9 8002426: 4308 orrs r0, r1 8002428: 1e41 subs r1, r0, #1 800242a: 4188 sbcs r0, r1 800242c: 4641 mov r1, r8 800242e: 444a add r2, r9 8002430: 0df6 lsrs r6, r6, #23 8002432: 0252 lsls r2, r2, #9 8002434: 4330 orrs r0, r6 8002436: 0249 lsls r1, r1, #9 8002438: 4314 orrs r4, r2 800243a: 4308 orrs r0, r1 800243c: 01d2 lsls r2, r2, #7 800243e: d535 bpl.n 80024ac <__aeabi_dmul+0x514> 8002440: 2201 movs r2, #1 8002442: 0843 lsrs r3, r0, #1 8002444: 4002 ands r2, r0 8002446: 4313 orrs r3, r2 8002448: 07e0 lsls r0, r4, #31 800244a: 4318 orrs r0, r3 800244c: 0864 lsrs r4, r4, #1 800244e: e634 b.n 80020ba <__aeabi_dmul+0x122> 8002450: 9b00 ldr r3, [sp, #0] 8002452: 46a2 mov sl, r4 8002454: 469b mov fp, r3 8002456: 4681 mov r9, r0 8002458: 2480 movs r4, #128 @ 0x80 800245a: 4653 mov r3, sl 800245c: 0324 lsls r4, r4, #12 800245e: 431c orrs r4, r3 8002460: 0324 lsls r4, r4, #12 8002462: 464a mov r2, r9 8002464: 4b2e ldr r3, [pc, #184] @ (8002520 <__aeabi_dmul+0x588>) 8002466: 0b24 lsrs r4, r4, #12 8002468: e5ec b.n 8002044 <__aeabi_dmul+0xac> 800246a: f000 fce7 bl 8002e3c <__clzsi2> 800246e: 2315 movs r3, #21 8002470: 469c mov ip, r3 8002472: 4484 add ip, r0 8002474: 0002 movs r2, r0 8002476: 4663 mov r3, ip 8002478: 3220 adds r2, #32 800247a: 2b1c cmp r3, #28 800247c: dc00 bgt.n 8002480 <__aeabi_dmul+0x4e8> 800247e: e684 b.n 800218a <__aeabi_dmul+0x1f2> 8002480: 2300 movs r3, #0 8002482: 4699 mov r9, r3 8002484: 0023 movs r3, r4 8002486: 3808 subs r0, #8 8002488: 4083 lsls r3, r0 800248a: 469a mov sl, r3 800248c: e68e b.n 80021ac <__aeabi_dmul+0x214> 800248e: f000 fcd5 bl 8002e3c <__clzsi2> 8002492: 0002 movs r2, r0 8002494: 0003 movs r3, r0 8002496: 3215 adds r2, #21 8002498: 3320 adds r3, #32 800249a: 2a1c cmp r2, #28 800249c: dc00 bgt.n 80024a0 <__aeabi_dmul+0x508> 800249e: e64e b.n 800213e <__aeabi_dmul+0x1a6> 80024a0: 0002 movs r2, r0 80024a2: 0034 movs r4, r6 80024a4: 3a08 subs r2, #8 80024a6: 2000 movs r0, #0 80024a8: 4094 lsls r4, r2 80024aa: e652 b.n 8002152 <__aeabi_dmul+0x1ba> 80024ac: 9301 str r3, [sp, #4] 80024ae: e604 b.n 80020ba <__aeabi_dmul+0x122> 80024b0: 4b1c ldr r3, [pc, #112] @ (8002524 <__aeabi_dmul+0x58c>) 80024b2: 0021 movs r1, r4 80024b4: 469c mov ip, r3 80024b6: 0003 movs r3, r0 80024b8: 9d01 ldr r5, [sp, #4] 80024ba: 40d3 lsrs r3, r2 80024bc: 4465 add r5, ip 80024be: 40a9 lsls r1, r5 80024c0: 4319 orrs r1, r3 80024c2: 0003 movs r3, r0 80024c4: 40ab lsls r3, r5 80024c6: 1e58 subs r0, r3, #1 80024c8: 4183 sbcs r3, r0 80024ca: 4319 orrs r1, r3 80024cc: 0008 movs r0, r1 80024ce: 40d4 lsrs r4, r2 80024d0: 074b lsls r3, r1, #29 80024d2: d009 beq.n 80024e8 <__aeabi_dmul+0x550> 80024d4: 230f movs r3, #15 80024d6: 400b ands r3, r1 80024d8: 2b04 cmp r3, #4 80024da: d005 beq.n 80024e8 <__aeabi_dmul+0x550> 80024dc: 1d0b adds r3, r1, #4 80024de: 428b cmp r3, r1 80024e0: 4180 sbcs r0, r0 80024e2: 4240 negs r0, r0 80024e4: 1824 adds r4, r4, r0 80024e6: 0018 movs r0, r3 80024e8: 0223 lsls r3, r4, #8 80024ea: d400 bmi.n 80024ee <__aeabi_dmul+0x556> 80024ec: e6d6 b.n 800229c <__aeabi_dmul+0x304> 80024ee: 2301 movs r3, #1 80024f0: 2400 movs r4, #0 80024f2: 2200 movs r2, #0 80024f4: e5a6 b.n 8002044 <__aeabi_dmul+0xac> 80024f6: 290f cmp r1, #15 80024f8: d1aa bne.n 8002450 <__aeabi_dmul+0x4b8> 80024fa: 2380 movs r3, #128 @ 0x80 80024fc: 4652 mov r2, sl 80024fe: 031b lsls r3, r3, #12 8002500: 421a tst r2, r3 8002502: d0a9 beq.n 8002458 <__aeabi_dmul+0x4c0> 8002504: 421c tst r4, r3 8002506: d1a7 bne.n 8002458 <__aeabi_dmul+0x4c0> 8002508: 431c orrs r4, r3 800250a: 9b00 ldr r3, [sp, #0] 800250c: 0002 movs r2, r0 800250e: 469b mov fp, r3 8002510: 4b03 ldr r3, [pc, #12] @ (8002520 <__aeabi_dmul+0x588>) 8002512: e597 b.n 8002044 <__aeabi_dmul+0xac> 8002514: 2400 movs r4, #0 8002516: e6c1 b.n 800229c <__aeabi_dmul+0x304> 8002518: 2400 movs r4, #0 800251a: 4b01 ldr r3, [pc, #4] @ (8002520 <__aeabi_dmul+0x588>) 800251c: 0022 movs r2, r4 800251e: e591 b.n 8002044 <__aeabi_dmul+0xac> 8002520: 000007ff .word 0x000007ff 8002524: 0000041e .word 0x0000041e 08002528 <__aeabi_dsub>: 8002528: b5f0 push {r4, r5, r6, r7, lr} 800252a: 464e mov r6, r9 800252c: 4645 mov r5, r8 800252e: 46de mov lr, fp 8002530: 4657 mov r7, sl 8002532: b5e0 push {r5, r6, r7, lr} 8002534: b085 sub sp, #20 8002536: 9000 str r0, [sp, #0] 8002538: 9101 str r1, [sp, #4] 800253a: 030c lsls r4, r1, #12 800253c: 004f lsls r7, r1, #1 800253e: 0fce lsrs r6, r1, #31 8002540: 0a61 lsrs r1, r4, #9 8002542: 9c00 ldr r4, [sp, #0] 8002544: 46b0 mov r8, r6 8002546: 0f64 lsrs r4, r4, #29 8002548: 430c orrs r4, r1 800254a: 9900 ldr r1, [sp, #0] 800254c: 0d7f lsrs r7, r7, #21 800254e: 00c8 lsls r0, r1, #3 8002550: 0011 movs r1, r2 8002552: 001a movs r2, r3 8002554: 031b lsls r3, r3, #12 8002556: 469c mov ip, r3 8002558: 9100 str r1, [sp, #0] 800255a: 9201 str r2, [sp, #4] 800255c: 0051 lsls r1, r2, #1 800255e: 0d4b lsrs r3, r1, #21 8002560: 4699 mov r9, r3 8002562: 9b01 ldr r3, [sp, #4] 8002564: 9d00 ldr r5, [sp, #0] 8002566: 0fd9 lsrs r1, r3, #31 8002568: 4663 mov r3, ip 800256a: 0f6a lsrs r2, r5, #29 800256c: 0a5b lsrs r3, r3, #9 800256e: 4313 orrs r3, r2 8002570: 00ea lsls r2, r5, #3 8002572: 4694 mov ip, r2 8002574: 4693 mov fp, r2 8002576: 4ac1 ldr r2, [pc, #772] @ (800287c <__aeabi_dsub+0x354>) 8002578: 9003 str r0, [sp, #12] 800257a: 9302 str r3, [sp, #8] 800257c: 4591 cmp r9, r2 800257e: d100 bne.n 8002582 <__aeabi_dsub+0x5a> 8002580: e0cd b.n 800271e <__aeabi_dsub+0x1f6> 8002582: 2501 movs r5, #1 8002584: 4069 eors r1, r5 8002586: 464d mov r5, r9 8002588: 1b7d subs r5, r7, r5 800258a: 46aa mov sl, r5 800258c: 428e cmp r6, r1 800258e: d100 bne.n 8002592 <__aeabi_dsub+0x6a> 8002590: e080 b.n 8002694 <__aeabi_dsub+0x16c> 8002592: 2d00 cmp r5, #0 8002594: dc00 bgt.n 8002598 <__aeabi_dsub+0x70> 8002596: e335 b.n 8002c04 <__aeabi_dsub+0x6dc> 8002598: 4649 mov r1, r9 800259a: 2900 cmp r1, #0 800259c: d100 bne.n 80025a0 <__aeabi_dsub+0x78> 800259e: e0df b.n 8002760 <__aeabi_dsub+0x238> 80025a0: 4297 cmp r7, r2 80025a2: d100 bne.n 80025a6 <__aeabi_dsub+0x7e> 80025a4: e194 b.n 80028d0 <__aeabi_dsub+0x3a8> 80025a6: 4652 mov r2, sl 80025a8: 2501 movs r5, #1 80025aa: 2a38 cmp r2, #56 @ 0x38 80025ac: dc19 bgt.n 80025e2 <__aeabi_dsub+0xba> 80025ae: 2280 movs r2, #128 @ 0x80 80025b0: 9b02 ldr r3, [sp, #8] 80025b2: 0412 lsls r2, r2, #16 80025b4: 4313 orrs r3, r2 80025b6: 9302 str r3, [sp, #8] 80025b8: 4652 mov r2, sl 80025ba: 2a1f cmp r2, #31 80025bc: dd00 ble.n 80025c0 <__aeabi_dsub+0x98> 80025be: e1e3 b.n 8002988 <__aeabi_dsub+0x460> 80025c0: 4653 mov r3, sl 80025c2: 2220 movs r2, #32 80025c4: 4661 mov r1, ip 80025c6: 9d02 ldr r5, [sp, #8] 80025c8: 1ad2 subs r2, r2, r3 80025ca: 4095 lsls r5, r2 80025cc: 40d9 lsrs r1, r3 80025ce: 430d orrs r5, r1 80025d0: 4661 mov r1, ip 80025d2: 4091 lsls r1, r2 80025d4: 000a movs r2, r1 80025d6: 1e51 subs r1, r2, #1 80025d8: 418a sbcs r2, r1 80025da: 4315 orrs r5, r2 80025dc: 9a02 ldr r2, [sp, #8] 80025de: 40da lsrs r2, r3 80025e0: 1aa4 subs r4, r4, r2 80025e2: 1b45 subs r5, r0, r5 80025e4: 42a8 cmp r0, r5 80025e6: 4180 sbcs r0, r0 80025e8: 4240 negs r0, r0 80025ea: 1a24 subs r4, r4, r0 80025ec: 0223 lsls r3, r4, #8 80025ee: d400 bmi.n 80025f2 <__aeabi_dsub+0xca> 80025f0: e13d b.n 800286e <__aeabi_dsub+0x346> 80025f2: 0264 lsls r4, r4, #9 80025f4: 0a64 lsrs r4, r4, #9 80025f6: 2c00 cmp r4, #0 80025f8: d100 bne.n 80025fc <__aeabi_dsub+0xd4> 80025fa: e147 b.n 800288c <__aeabi_dsub+0x364> 80025fc: 0020 movs r0, r4 80025fe: f000 fc1d bl 8002e3c <__clzsi2> 8002602: 0003 movs r3, r0 8002604: 3b08 subs r3, #8 8002606: 2120 movs r1, #32 8002608: 0028 movs r0, r5 800260a: 1aca subs r2, r1, r3 800260c: 40d0 lsrs r0, r2 800260e: 409c lsls r4, r3 8002610: 0002 movs r2, r0 8002612: 409d lsls r5, r3 8002614: 4322 orrs r2, r4 8002616: 429f cmp r7, r3 8002618: dd00 ble.n 800261c <__aeabi_dsub+0xf4> 800261a: e177 b.n 800290c <__aeabi_dsub+0x3e4> 800261c: 1bd8 subs r0, r3, r7 800261e: 3001 adds r0, #1 8002620: 1a09 subs r1, r1, r0 8002622: 002c movs r4, r5 8002624: 408d lsls r5, r1 8002626: 40c4 lsrs r4, r0 8002628: 1e6b subs r3, r5, #1 800262a: 419d sbcs r5, r3 800262c: 0013 movs r3, r2 800262e: 40c2 lsrs r2, r0 8002630: 408b lsls r3, r1 8002632: 4325 orrs r5, r4 8002634: 2700 movs r7, #0 8002636: 0014 movs r4, r2 8002638: 431d orrs r5, r3 800263a: 076b lsls r3, r5, #29 800263c: d009 beq.n 8002652 <__aeabi_dsub+0x12a> 800263e: 230f movs r3, #15 8002640: 402b ands r3, r5 8002642: 2b04 cmp r3, #4 8002644: d005 beq.n 8002652 <__aeabi_dsub+0x12a> 8002646: 1d2b adds r3, r5, #4 8002648: 42ab cmp r3, r5 800264a: 41ad sbcs r5, r5 800264c: 426d negs r5, r5 800264e: 1964 adds r4, r4, r5 8002650: 001d movs r5, r3 8002652: 0223 lsls r3, r4, #8 8002654: d400 bmi.n 8002658 <__aeabi_dsub+0x130> 8002656: e140 b.n 80028da <__aeabi_dsub+0x3b2> 8002658: 4a88 ldr r2, [pc, #544] @ (800287c <__aeabi_dsub+0x354>) 800265a: 3701 adds r7, #1 800265c: 4297 cmp r7, r2 800265e: d100 bne.n 8002662 <__aeabi_dsub+0x13a> 8002660: e101 b.n 8002866 <__aeabi_dsub+0x33e> 8002662: 2601 movs r6, #1 8002664: 4643 mov r3, r8 8002666: 4986 ldr r1, [pc, #536] @ (8002880 <__aeabi_dsub+0x358>) 8002668: 08ed lsrs r5, r5, #3 800266a: 4021 ands r1, r4 800266c: 074a lsls r2, r1, #29 800266e: 432a orrs r2, r5 8002670: 057c lsls r4, r7, #21 8002672: 024d lsls r5, r1, #9 8002674: 0b2d lsrs r5, r5, #12 8002676: 0d64 lsrs r4, r4, #21 8002678: 401e ands r6, r3 800267a: 0524 lsls r4, r4, #20 800267c: 432c orrs r4, r5 800267e: 07f6 lsls r6, r6, #31 8002680: 4334 orrs r4, r6 8002682: 0010 movs r0, r2 8002684: 0021 movs r1, r4 8002686: b005 add sp, #20 8002688: bcf0 pop {r4, r5, r6, r7} 800268a: 46bb mov fp, r7 800268c: 46b2 mov sl, r6 800268e: 46a9 mov r9, r5 8002690: 46a0 mov r8, r4 8002692: bdf0 pop {r4, r5, r6, r7, pc} 8002694: 2d00 cmp r5, #0 8002696: dc00 bgt.n 800269a <__aeabi_dsub+0x172> 8002698: e2d0 b.n 8002c3c <__aeabi_dsub+0x714> 800269a: 4649 mov r1, r9 800269c: 2900 cmp r1, #0 800269e: d000 beq.n 80026a2 <__aeabi_dsub+0x17a> 80026a0: e0d4 b.n 800284c <__aeabi_dsub+0x324> 80026a2: 4661 mov r1, ip 80026a4: 9b02 ldr r3, [sp, #8] 80026a6: 4319 orrs r1, r3 80026a8: d100 bne.n 80026ac <__aeabi_dsub+0x184> 80026aa: e12b b.n 8002904 <__aeabi_dsub+0x3dc> 80026ac: 1e69 subs r1, r5, #1 80026ae: 2d01 cmp r5, #1 80026b0: d100 bne.n 80026b4 <__aeabi_dsub+0x18c> 80026b2: e1d9 b.n 8002a68 <__aeabi_dsub+0x540> 80026b4: 4295 cmp r5, r2 80026b6: d100 bne.n 80026ba <__aeabi_dsub+0x192> 80026b8: e10a b.n 80028d0 <__aeabi_dsub+0x3a8> 80026ba: 2501 movs r5, #1 80026bc: 2938 cmp r1, #56 @ 0x38 80026be: dc17 bgt.n 80026f0 <__aeabi_dsub+0x1c8> 80026c0: 468a mov sl, r1 80026c2: 4653 mov r3, sl 80026c4: 2b1f cmp r3, #31 80026c6: dd00 ble.n 80026ca <__aeabi_dsub+0x1a2> 80026c8: e1e7 b.n 8002a9a <__aeabi_dsub+0x572> 80026ca: 2220 movs r2, #32 80026cc: 1ad2 subs r2, r2, r3 80026ce: 9b02 ldr r3, [sp, #8] 80026d0: 4661 mov r1, ip 80026d2: 4093 lsls r3, r2 80026d4: 001d movs r5, r3 80026d6: 4653 mov r3, sl 80026d8: 40d9 lsrs r1, r3 80026da: 4663 mov r3, ip 80026dc: 4093 lsls r3, r2 80026de: 001a movs r2, r3 80026e0: 430d orrs r5, r1 80026e2: 1e51 subs r1, r2, #1 80026e4: 418a sbcs r2, r1 80026e6: 4653 mov r3, sl 80026e8: 4315 orrs r5, r2 80026ea: 9a02 ldr r2, [sp, #8] 80026ec: 40da lsrs r2, r3 80026ee: 18a4 adds r4, r4, r2 80026f0: 182d adds r5, r5, r0 80026f2: 4285 cmp r5, r0 80026f4: 4180 sbcs r0, r0 80026f6: 4240 negs r0, r0 80026f8: 1824 adds r4, r4, r0 80026fa: 0223 lsls r3, r4, #8 80026fc: d400 bmi.n 8002700 <__aeabi_dsub+0x1d8> 80026fe: e0b6 b.n 800286e <__aeabi_dsub+0x346> 8002700: 4b5e ldr r3, [pc, #376] @ (800287c <__aeabi_dsub+0x354>) 8002702: 3701 adds r7, #1 8002704: 429f cmp r7, r3 8002706: d100 bne.n 800270a <__aeabi_dsub+0x1e2> 8002708: e0ad b.n 8002866 <__aeabi_dsub+0x33e> 800270a: 2101 movs r1, #1 800270c: 4b5c ldr r3, [pc, #368] @ (8002880 <__aeabi_dsub+0x358>) 800270e: 086a lsrs r2, r5, #1 8002710: 401c ands r4, r3 8002712: 4029 ands r1, r5 8002714: 430a orrs r2, r1 8002716: 07e5 lsls r5, r4, #31 8002718: 4315 orrs r5, r2 800271a: 0864 lsrs r4, r4, #1 800271c: e78d b.n 800263a <__aeabi_dsub+0x112> 800271e: 4a59 ldr r2, [pc, #356] @ (8002884 <__aeabi_dsub+0x35c>) 8002720: 9b02 ldr r3, [sp, #8] 8002722: 4692 mov sl, r2 8002724: 4662 mov r2, ip 8002726: 44ba add sl, r7 8002728: 431a orrs r2, r3 800272a: d02c beq.n 8002786 <__aeabi_dsub+0x25e> 800272c: 428e cmp r6, r1 800272e: d02e beq.n 800278e <__aeabi_dsub+0x266> 8002730: 4652 mov r2, sl 8002732: 2a00 cmp r2, #0 8002734: d060 beq.n 80027f8 <__aeabi_dsub+0x2d0> 8002736: 2f00 cmp r7, #0 8002738: d100 bne.n 800273c <__aeabi_dsub+0x214> 800273a: e0db b.n 80028f4 <__aeabi_dsub+0x3cc> 800273c: 4663 mov r3, ip 800273e: 000e movs r6, r1 8002740: 9c02 ldr r4, [sp, #8] 8002742: 08d8 lsrs r0, r3, #3 8002744: 0762 lsls r2, r4, #29 8002746: 4302 orrs r2, r0 8002748: 08e4 lsrs r4, r4, #3 800274a: 0013 movs r3, r2 800274c: 4323 orrs r3, r4 800274e: d100 bne.n 8002752 <__aeabi_dsub+0x22a> 8002750: e254 b.n 8002bfc <__aeabi_dsub+0x6d4> 8002752: 2580 movs r5, #128 @ 0x80 8002754: 032d lsls r5, r5, #12 8002756: 4325 orrs r5, r4 8002758: 032d lsls r5, r5, #12 800275a: 4c48 ldr r4, [pc, #288] @ (800287c <__aeabi_dsub+0x354>) 800275c: 0b2d lsrs r5, r5, #12 800275e: e78c b.n 800267a <__aeabi_dsub+0x152> 8002760: 4661 mov r1, ip 8002762: 9b02 ldr r3, [sp, #8] 8002764: 4319 orrs r1, r3 8002766: d100 bne.n 800276a <__aeabi_dsub+0x242> 8002768: e0cc b.n 8002904 <__aeabi_dsub+0x3dc> 800276a: 0029 movs r1, r5 800276c: 3901 subs r1, #1 800276e: 2d01 cmp r5, #1 8002770: d100 bne.n 8002774 <__aeabi_dsub+0x24c> 8002772: e188 b.n 8002a86 <__aeabi_dsub+0x55e> 8002774: 4295 cmp r5, r2 8002776: d100 bne.n 800277a <__aeabi_dsub+0x252> 8002778: e0aa b.n 80028d0 <__aeabi_dsub+0x3a8> 800277a: 2501 movs r5, #1 800277c: 2938 cmp r1, #56 @ 0x38 800277e: dd00 ble.n 8002782 <__aeabi_dsub+0x25a> 8002780: e72f b.n 80025e2 <__aeabi_dsub+0xba> 8002782: 468a mov sl, r1 8002784: e718 b.n 80025b8 <__aeabi_dsub+0x90> 8002786: 2201 movs r2, #1 8002788: 4051 eors r1, r2 800278a: 428e cmp r6, r1 800278c: d1d0 bne.n 8002730 <__aeabi_dsub+0x208> 800278e: 4653 mov r3, sl 8002790: 2b00 cmp r3, #0 8002792: d100 bne.n 8002796 <__aeabi_dsub+0x26e> 8002794: e0be b.n 8002914 <__aeabi_dsub+0x3ec> 8002796: 2f00 cmp r7, #0 8002798: d000 beq.n 800279c <__aeabi_dsub+0x274> 800279a: e138 b.n 8002a0e <__aeabi_dsub+0x4e6> 800279c: 46ca mov sl, r9 800279e: 0022 movs r2, r4 80027a0: 4302 orrs r2, r0 80027a2: d100 bne.n 80027a6 <__aeabi_dsub+0x27e> 80027a4: e1e2 b.n 8002b6c <__aeabi_dsub+0x644> 80027a6: 4653 mov r3, sl 80027a8: 1e59 subs r1, r3, #1 80027aa: 2b01 cmp r3, #1 80027ac: d100 bne.n 80027b0 <__aeabi_dsub+0x288> 80027ae: e20d b.n 8002bcc <__aeabi_dsub+0x6a4> 80027b0: 4a32 ldr r2, [pc, #200] @ (800287c <__aeabi_dsub+0x354>) 80027b2: 4592 cmp sl, r2 80027b4: d100 bne.n 80027b8 <__aeabi_dsub+0x290> 80027b6: e1d2 b.n 8002b5e <__aeabi_dsub+0x636> 80027b8: 2701 movs r7, #1 80027ba: 2938 cmp r1, #56 @ 0x38 80027bc: dc13 bgt.n 80027e6 <__aeabi_dsub+0x2be> 80027be: 291f cmp r1, #31 80027c0: dd00 ble.n 80027c4 <__aeabi_dsub+0x29c> 80027c2: e1ee b.n 8002ba2 <__aeabi_dsub+0x67a> 80027c4: 2220 movs r2, #32 80027c6: 9b02 ldr r3, [sp, #8] 80027c8: 1a52 subs r2, r2, r1 80027ca: 0025 movs r5, r4 80027cc: 0007 movs r7, r0 80027ce: 469a mov sl, r3 80027d0: 40cc lsrs r4, r1 80027d2: 4090 lsls r0, r2 80027d4: 4095 lsls r5, r2 80027d6: 40cf lsrs r7, r1 80027d8: 44a2 add sl, r4 80027da: 1e42 subs r2, r0, #1 80027dc: 4190 sbcs r0, r2 80027de: 4653 mov r3, sl 80027e0: 432f orrs r7, r5 80027e2: 4307 orrs r7, r0 80027e4: 9302 str r3, [sp, #8] 80027e6: 003d movs r5, r7 80027e8: 4465 add r5, ip 80027ea: 4565 cmp r5, ip 80027ec: 4192 sbcs r2, r2 80027ee: 9b02 ldr r3, [sp, #8] 80027f0: 4252 negs r2, r2 80027f2: 464f mov r7, r9 80027f4: 18d4 adds r4, r2, r3 80027f6: e780 b.n 80026fa <__aeabi_dsub+0x1d2> 80027f8: 4a23 ldr r2, [pc, #140] @ (8002888 <__aeabi_dsub+0x360>) 80027fa: 1c7d adds r5, r7, #1 80027fc: 4215 tst r5, r2 80027fe: d000 beq.n 8002802 <__aeabi_dsub+0x2da> 8002800: e0aa b.n 8002958 <__aeabi_dsub+0x430> 8002802: 4662 mov r2, ip 8002804: 0025 movs r5, r4 8002806: 9b02 ldr r3, [sp, #8] 8002808: 4305 orrs r5, r0 800280a: 431a orrs r2, r3 800280c: 2f00 cmp r7, #0 800280e: d000 beq.n 8002812 <__aeabi_dsub+0x2ea> 8002810: e0f5 b.n 80029fe <__aeabi_dsub+0x4d6> 8002812: 2d00 cmp r5, #0 8002814: d100 bne.n 8002818 <__aeabi_dsub+0x2f0> 8002816: e16b b.n 8002af0 <__aeabi_dsub+0x5c8> 8002818: 2a00 cmp r2, #0 800281a: d100 bne.n 800281e <__aeabi_dsub+0x2f6> 800281c: e152 b.n 8002ac4 <__aeabi_dsub+0x59c> 800281e: 4663 mov r3, ip 8002820: 1ac5 subs r5, r0, r3 8002822: 9b02 ldr r3, [sp, #8] 8002824: 1ae2 subs r2, r4, r3 8002826: 42a8 cmp r0, r5 8002828: 419b sbcs r3, r3 800282a: 425b negs r3, r3 800282c: 1ad3 subs r3, r2, r3 800282e: 021a lsls r2, r3, #8 8002830: d400 bmi.n 8002834 <__aeabi_dsub+0x30c> 8002832: e1d5 b.n 8002be0 <__aeabi_dsub+0x6b8> 8002834: 4663 mov r3, ip 8002836: 1a1d subs r5, r3, r0 8002838: 45ac cmp ip, r5 800283a: 4192 sbcs r2, r2 800283c: 2601 movs r6, #1 800283e: 9b02 ldr r3, [sp, #8] 8002840: 4252 negs r2, r2 8002842: 1b1c subs r4, r3, r4 8002844: 4688 mov r8, r1 8002846: 1aa4 subs r4, r4, r2 8002848: 400e ands r6, r1 800284a: e6f6 b.n 800263a <__aeabi_dsub+0x112> 800284c: 4297 cmp r7, r2 800284e: d03f beq.n 80028d0 <__aeabi_dsub+0x3a8> 8002850: 4652 mov r2, sl 8002852: 2501 movs r5, #1 8002854: 2a38 cmp r2, #56 @ 0x38 8002856: dd00 ble.n 800285a <__aeabi_dsub+0x332> 8002858: e74a b.n 80026f0 <__aeabi_dsub+0x1c8> 800285a: 2280 movs r2, #128 @ 0x80 800285c: 9b02 ldr r3, [sp, #8] 800285e: 0412 lsls r2, r2, #16 8002860: 4313 orrs r3, r2 8002862: 9302 str r3, [sp, #8] 8002864: e72d b.n 80026c2 <__aeabi_dsub+0x19a> 8002866: 003c movs r4, r7 8002868: 2500 movs r5, #0 800286a: 2200 movs r2, #0 800286c: e705 b.n 800267a <__aeabi_dsub+0x152> 800286e: 2307 movs r3, #7 8002870: 402b ands r3, r5 8002872: 2b00 cmp r3, #0 8002874: d000 beq.n 8002878 <__aeabi_dsub+0x350> 8002876: e6e2 b.n 800263e <__aeabi_dsub+0x116> 8002878: e06b b.n 8002952 <__aeabi_dsub+0x42a> 800287a: 46c0 nop @ (mov r8, r8) 800287c: 000007ff .word 0x000007ff 8002880: ff7fffff .word 0xff7fffff 8002884: fffff801 .word 0xfffff801 8002888: 000007fe .word 0x000007fe 800288c: 0028 movs r0, r5 800288e: f000 fad5 bl 8002e3c <__clzsi2> 8002892: 0003 movs r3, r0 8002894: 3318 adds r3, #24 8002896: 2b1f cmp r3, #31 8002898: dc00 bgt.n 800289c <__aeabi_dsub+0x374> 800289a: e6b4 b.n 8002606 <__aeabi_dsub+0xde> 800289c: 002a movs r2, r5 800289e: 3808 subs r0, #8 80028a0: 4082 lsls r2, r0 80028a2: 429f cmp r7, r3 80028a4: dd00 ble.n 80028a8 <__aeabi_dsub+0x380> 80028a6: e0b9 b.n 8002a1c <__aeabi_dsub+0x4f4> 80028a8: 1bdb subs r3, r3, r7 80028aa: 1c58 adds r0, r3, #1 80028ac: 281f cmp r0, #31 80028ae: dc00 bgt.n 80028b2 <__aeabi_dsub+0x38a> 80028b0: e1a0 b.n 8002bf4 <__aeabi_dsub+0x6cc> 80028b2: 0015 movs r5, r2 80028b4: 3b1f subs r3, #31 80028b6: 40dd lsrs r5, r3 80028b8: 2820 cmp r0, #32 80028ba: d005 beq.n 80028c8 <__aeabi_dsub+0x3a0> 80028bc: 2340 movs r3, #64 @ 0x40 80028be: 1a1b subs r3, r3, r0 80028c0: 409a lsls r2, r3 80028c2: 1e53 subs r3, r2, #1 80028c4: 419a sbcs r2, r3 80028c6: 4315 orrs r5, r2 80028c8: 2307 movs r3, #7 80028ca: 2700 movs r7, #0 80028cc: 402b ands r3, r5 80028ce: e7d0 b.n 8002872 <__aeabi_dsub+0x34a> 80028d0: 08c0 lsrs r0, r0, #3 80028d2: 0762 lsls r2, r4, #29 80028d4: 4302 orrs r2, r0 80028d6: 08e4 lsrs r4, r4, #3 80028d8: e737 b.n 800274a <__aeabi_dsub+0x222> 80028da: 08ea lsrs r2, r5, #3 80028dc: 0763 lsls r3, r4, #29 80028de: 431a orrs r2, r3 80028e0: 4bd3 ldr r3, [pc, #844] @ (8002c30 <__aeabi_dsub+0x708>) 80028e2: 08e4 lsrs r4, r4, #3 80028e4: 429f cmp r7, r3 80028e6: d100 bne.n 80028ea <__aeabi_dsub+0x3c2> 80028e8: e72f b.n 800274a <__aeabi_dsub+0x222> 80028ea: 0324 lsls r4, r4, #12 80028ec: 0b25 lsrs r5, r4, #12 80028ee: 057c lsls r4, r7, #21 80028f0: 0d64 lsrs r4, r4, #21 80028f2: e6c2 b.n 800267a <__aeabi_dsub+0x152> 80028f4: 46ca mov sl, r9 80028f6: 0022 movs r2, r4 80028f8: 4302 orrs r2, r0 80028fa: d158 bne.n 80029ae <__aeabi_dsub+0x486> 80028fc: 4663 mov r3, ip 80028fe: 000e movs r6, r1 8002900: 9c02 ldr r4, [sp, #8] 8002902: 9303 str r3, [sp, #12] 8002904: 9b03 ldr r3, [sp, #12] 8002906: 4657 mov r7, sl 8002908: 08da lsrs r2, r3, #3 800290a: e7e7 b.n 80028dc <__aeabi_dsub+0x3b4> 800290c: 4cc9 ldr r4, [pc, #804] @ (8002c34 <__aeabi_dsub+0x70c>) 800290e: 1aff subs r7, r7, r3 8002910: 4014 ands r4, r2 8002912: e692 b.n 800263a <__aeabi_dsub+0x112> 8002914: 4dc8 ldr r5, [pc, #800] @ (8002c38 <__aeabi_dsub+0x710>) 8002916: 1c7a adds r2, r7, #1 8002918: 422a tst r2, r5 800291a: d000 beq.n 800291e <__aeabi_dsub+0x3f6> 800291c: e084 b.n 8002a28 <__aeabi_dsub+0x500> 800291e: 0022 movs r2, r4 8002920: 4302 orrs r2, r0 8002922: 2f00 cmp r7, #0 8002924: d000 beq.n 8002928 <__aeabi_dsub+0x400> 8002926: e0ef b.n 8002b08 <__aeabi_dsub+0x5e0> 8002928: 2a00 cmp r2, #0 800292a: d100 bne.n 800292e <__aeabi_dsub+0x406> 800292c: e0e5 b.n 8002afa <__aeabi_dsub+0x5d2> 800292e: 4662 mov r2, ip 8002930: 9902 ldr r1, [sp, #8] 8002932: 430a orrs r2, r1 8002934: d100 bne.n 8002938 <__aeabi_dsub+0x410> 8002936: e0c5 b.n 8002ac4 <__aeabi_dsub+0x59c> 8002938: 4663 mov r3, ip 800293a: 18c5 adds r5, r0, r3 800293c: 468c mov ip, r1 800293e: 4285 cmp r5, r0 8002940: 4180 sbcs r0, r0 8002942: 4464 add r4, ip 8002944: 4240 negs r0, r0 8002946: 1824 adds r4, r4, r0 8002948: 0223 lsls r3, r4, #8 800294a: d502 bpl.n 8002952 <__aeabi_dsub+0x42a> 800294c: 4bb9 ldr r3, [pc, #740] @ (8002c34 <__aeabi_dsub+0x70c>) 800294e: 3701 adds r7, #1 8002950: 401c ands r4, r3 8002952: 46ba mov sl, r7 8002954: 9503 str r5, [sp, #12] 8002956: e7d5 b.n 8002904 <__aeabi_dsub+0x3dc> 8002958: 4662 mov r2, ip 800295a: 1a85 subs r5, r0, r2 800295c: 42a8 cmp r0, r5 800295e: 4192 sbcs r2, r2 8002960: 4252 negs r2, r2 8002962: 4691 mov r9, r2 8002964: 9b02 ldr r3, [sp, #8] 8002966: 1ae3 subs r3, r4, r3 8002968: 001a movs r2, r3 800296a: 464b mov r3, r9 800296c: 1ad2 subs r2, r2, r3 800296e: 0013 movs r3, r2 8002970: 4691 mov r9, r2 8002972: 021a lsls r2, r3, #8 8002974: d46c bmi.n 8002a50 <__aeabi_dsub+0x528> 8002976: 464a mov r2, r9 8002978: 464c mov r4, r9 800297a: 432a orrs r2, r5 800297c: d000 beq.n 8002980 <__aeabi_dsub+0x458> 800297e: e63a b.n 80025f6 <__aeabi_dsub+0xce> 8002980: 2600 movs r6, #0 8002982: 2400 movs r4, #0 8002984: 2500 movs r5, #0 8002986: e678 b.n 800267a <__aeabi_dsub+0x152> 8002988: 9902 ldr r1, [sp, #8] 800298a: 4653 mov r3, sl 800298c: 000d movs r5, r1 800298e: 3a20 subs r2, #32 8002990: 40d5 lsrs r5, r2 8002992: 2b20 cmp r3, #32 8002994: d006 beq.n 80029a4 <__aeabi_dsub+0x47c> 8002996: 2240 movs r2, #64 @ 0x40 8002998: 1ad2 subs r2, r2, r3 800299a: 000b movs r3, r1 800299c: 4093 lsls r3, r2 800299e: 4662 mov r2, ip 80029a0: 431a orrs r2, r3 80029a2: 4693 mov fp, r2 80029a4: 465b mov r3, fp 80029a6: 1e5a subs r2, r3, #1 80029a8: 4193 sbcs r3, r2 80029aa: 431d orrs r5, r3 80029ac: e619 b.n 80025e2 <__aeabi_dsub+0xba> 80029ae: 4653 mov r3, sl 80029b0: 1e5a subs r2, r3, #1 80029b2: 2b01 cmp r3, #1 80029b4: d100 bne.n 80029b8 <__aeabi_dsub+0x490> 80029b6: e0c6 b.n 8002b46 <__aeabi_dsub+0x61e> 80029b8: 4e9d ldr r6, [pc, #628] @ (8002c30 <__aeabi_dsub+0x708>) 80029ba: 45b2 cmp sl, r6 80029bc: d100 bne.n 80029c0 <__aeabi_dsub+0x498> 80029be: e6bd b.n 800273c <__aeabi_dsub+0x214> 80029c0: 4688 mov r8, r1 80029c2: 000e movs r6, r1 80029c4: 2501 movs r5, #1 80029c6: 2a38 cmp r2, #56 @ 0x38 80029c8: dc10 bgt.n 80029ec <__aeabi_dsub+0x4c4> 80029ca: 2a1f cmp r2, #31 80029cc: dc7f bgt.n 8002ace <__aeabi_dsub+0x5a6> 80029ce: 2120 movs r1, #32 80029d0: 0025 movs r5, r4 80029d2: 1a89 subs r1, r1, r2 80029d4: 0007 movs r7, r0 80029d6: 4088 lsls r0, r1 80029d8: 408d lsls r5, r1 80029da: 40d7 lsrs r7, r2 80029dc: 40d4 lsrs r4, r2 80029de: 1e41 subs r1, r0, #1 80029e0: 4188 sbcs r0, r1 80029e2: 9b02 ldr r3, [sp, #8] 80029e4: 433d orrs r5, r7 80029e6: 1b1b subs r3, r3, r4 80029e8: 4305 orrs r5, r0 80029ea: 9302 str r3, [sp, #8] 80029ec: 4662 mov r2, ip 80029ee: 1b55 subs r5, r2, r5 80029f0: 45ac cmp ip, r5 80029f2: 4192 sbcs r2, r2 80029f4: 9b02 ldr r3, [sp, #8] 80029f6: 4252 negs r2, r2 80029f8: 464f mov r7, r9 80029fa: 1a9c subs r4, r3, r2 80029fc: e5f6 b.n 80025ec <__aeabi_dsub+0xc4> 80029fe: 2d00 cmp r5, #0 8002a00: d000 beq.n 8002a04 <__aeabi_dsub+0x4dc> 8002a02: e0b7 b.n 8002b74 <__aeabi_dsub+0x64c> 8002a04: 2a00 cmp r2, #0 8002a06: d100 bne.n 8002a0a <__aeabi_dsub+0x4e2> 8002a08: e0f0 b.n 8002bec <__aeabi_dsub+0x6c4> 8002a0a: 2601 movs r6, #1 8002a0c: 400e ands r6, r1 8002a0e: 4663 mov r3, ip 8002a10: 9802 ldr r0, [sp, #8] 8002a12: 08d9 lsrs r1, r3, #3 8002a14: 0742 lsls r2, r0, #29 8002a16: 430a orrs r2, r1 8002a18: 08c4 lsrs r4, r0, #3 8002a1a: e696 b.n 800274a <__aeabi_dsub+0x222> 8002a1c: 4c85 ldr r4, [pc, #532] @ (8002c34 <__aeabi_dsub+0x70c>) 8002a1e: 1aff subs r7, r7, r3 8002a20: 4014 ands r4, r2 8002a22: 0762 lsls r2, r4, #29 8002a24: 08e4 lsrs r4, r4, #3 8002a26: e760 b.n 80028ea <__aeabi_dsub+0x3c2> 8002a28: 4981 ldr r1, [pc, #516] @ (8002c30 <__aeabi_dsub+0x708>) 8002a2a: 428a cmp r2, r1 8002a2c: d100 bne.n 8002a30 <__aeabi_dsub+0x508> 8002a2e: e0c9 b.n 8002bc4 <__aeabi_dsub+0x69c> 8002a30: 4663 mov r3, ip 8002a32: 18c1 adds r1, r0, r3 8002a34: 4281 cmp r1, r0 8002a36: 4180 sbcs r0, r0 8002a38: 9b02 ldr r3, [sp, #8] 8002a3a: 4240 negs r0, r0 8002a3c: 18e3 adds r3, r4, r3 8002a3e: 181b adds r3, r3, r0 8002a40: 07dd lsls r5, r3, #31 8002a42: 085c lsrs r4, r3, #1 8002a44: 2307 movs r3, #7 8002a46: 0849 lsrs r1, r1, #1 8002a48: 430d orrs r5, r1 8002a4a: 0017 movs r7, r2 8002a4c: 402b ands r3, r5 8002a4e: e710 b.n 8002872 <__aeabi_dsub+0x34a> 8002a50: 4663 mov r3, ip 8002a52: 1a1d subs r5, r3, r0 8002a54: 45ac cmp ip, r5 8002a56: 4192 sbcs r2, r2 8002a58: 2601 movs r6, #1 8002a5a: 9b02 ldr r3, [sp, #8] 8002a5c: 4252 negs r2, r2 8002a5e: 1b1c subs r4, r3, r4 8002a60: 4688 mov r8, r1 8002a62: 1aa4 subs r4, r4, r2 8002a64: 400e ands r6, r1 8002a66: e5c6 b.n 80025f6 <__aeabi_dsub+0xce> 8002a68: 4663 mov r3, ip 8002a6a: 18c5 adds r5, r0, r3 8002a6c: 9b02 ldr r3, [sp, #8] 8002a6e: 4285 cmp r5, r0 8002a70: 4180 sbcs r0, r0 8002a72: 469c mov ip, r3 8002a74: 4240 negs r0, r0 8002a76: 4464 add r4, ip 8002a78: 1824 adds r4, r4, r0 8002a7a: 2701 movs r7, #1 8002a7c: 0223 lsls r3, r4, #8 8002a7e: d400 bmi.n 8002a82 <__aeabi_dsub+0x55a> 8002a80: e6f5 b.n 800286e <__aeabi_dsub+0x346> 8002a82: 2702 movs r7, #2 8002a84: e641 b.n 800270a <__aeabi_dsub+0x1e2> 8002a86: 4663 mov r3, ip 8002a88: 1ac5 subs r5, r0, r3 8002a8a: 42a8 cmp r0, r5 8002a8c: 4180 sbcs r0, r0 8002a8e: 9b02 ldr r3, [sp, #8] 8002a90: 4240 negs r0, r0 8002a92: 1ae4 subs r4, r4, r3 8002a94: 2701 movs r7, #1 8002a96: 1a24 subs r4, r4, r0 8002a98: e5a8 b.n 80025ec <__aeabi_dsub+0xc4> 8002a9a: 9d02 ldr r5, [sp, #8] 8002a9c: 4652 mov r2, sl 8002a9e: 002b movs r3, r5 8002aa0: 3a20 subs r2, #32 8002aa2: 40d3 lsrs r3, r2 8002aa4: 0019 movs r1, r3 8002aa6: 4653 mov r3, sl 8002aa8: 2b20 cmp r3, #32 8002aaa: d006 beq.n 8002aba <__aeabi_dsub+0x592> 8002aac: 2240 movs r2, #64 @ 0x40 8002aae: 1ad2 subs r2, r2, r3 8002ab0: 002b movs r3, r5 8002ab2: 4093 lsls r3, r2 8002ab4: 4662 mov r2, ip 8002ab6: 431a orrs r2, r3 8002ab8: 4693 mov fp, r2 8002aba: 465d mov r5, fp 8002abc: 1e6b subs r3, r5, #1 8002abe: 419d sbcs r5, r3 8002ac0: 430d orrs r5, r1 8002ac2: e615 b.n 80026f0 <__aeabi_dsub+0x1c8> 8002ac4: 0762 lsls r2, r4, #29 8002ac6: 08c0 lsrs r0, r0, #3 8002ac8: 4302 orrs r2, r0 8002aca: 08e4 lsrs r4, r4, #3 8002acc: e70d b.n 80028ea <__aeabi_dsub+0x3c2> 8002ace: 0011 movs r1, r2 8002ad0: 0027 movs r7, r4 8002ad2: 3920 subs r1, #32 8002ad4: 40cf lsrs r7, r1 8002ad6: 2a20 cmp r2, #32 8002ad8: d005 beq.n 8002ae6 <__aeabi_dsub+0x5be> 8002ada: 2140 movs r1, #64 @ 0x40 8002adc: 1a8a subs r2, r1, r2 8002ade: 4094 lsls r4, r2 8002ae0: 0025 movs r5, r4 8002ae2: 4305 orrs r5, r0 8002ae4: 9503 str r5, [sp, #12] 8002ae6: 9d03 ldr r5, [sp, #12] 8002ae8: 1e6a subs r2, r5, #1 8002aea: 4195 sbcs r5, r2 8002aec: 433d orrs r5, r7 8002aee: e77d b.n 80029ec <__aeabi_dsub+0x4c4> 8002af0: 2a00 cmp r2, #0 8002af2: d100 bne.n 8002af6 <__aeabi_dsub+0x5ce> 8002af4: e744 b.n 8002980 <__aeabi_dsub+0x458> 8002af6: 2601 movs r6, #1 8002af8: 400e ands r6, r1 8002afa: 4663 mov r3, ip 8002afc: 08d9 lsrs r1, r3, #3 8002afe: 9b02 ldr r3, [sp, #8] 8002b00: 075a lsls r2, r3, #29 8002b02: 430a orrs r2, r1 8002b04: 08dc lsrs r4, r3, #3 8002b06: e6f0 b.n 80028ea <__aeabi_dsub+0x3c2> 8002b08: 2a00 cmp r2, #0 8002b0a: d028 beq.n 8002b5e <__aeabi_dsub+0x636> 8002b0c: 4662 mov r2, ip 8002b0e: 9f02 ldr r7, [sp, #8] 8002b10: 08c0 lsrs r0, r0, #3 8002b12: 433a orrs r2, r7 8002b14: d100 bne.n 8002b18 <__aeabi_dsub+0x5f0> 8002b16: e6dc b.n 80028d2 <__aeabi_dsub+0x3aa> 8002b18: 0762 lsls r2, r4, #29 8002b1a: 4310 orrs r0, r2 8002b1c: 2280 movs r2, #128 @ 0x80 8002b1e: 08e4 lsrs r4, r4, #3 8002b20: 0312 lsls r2, r2, #12 8002b22: 4214 tst r4, r2 8002b24: d009 beq.n 8002b3a <__aeabi_dsub+0x612> 8002b26: 08fd lsrs r5, r7, #3 8002b28: 4215 tst r5, r2 8002b2a: d106 bne.n 8002b3a <__aeabi_dsub+0x612> 8002b2c: 4663 mov r3, ip 8002b2e: 2601 movs r6, #1 8002b30: 002c movs r4, r5 8002b32: 08d8 lsrs r0, r3, #3 8002b34: 077b lsls r3, r7, #29 8002b36: 4318 orrs r0, r3 8002b38: 400e ands r6, r1 8002b3a: 0f42 lsrs r2, r0, #29 8002b3c: 00c0 lsls r0, r0, #3 8002b3e: 08c0 lsrs r0, r0, #3 8002b40: 0752 lsls r2, r2, #29 8002b42: 4302 orrs r2, r0 8002b44: e601 b.n 800274a <__aeabi_dsub+0x222> 8002b46: 4663 mov r3, ip 8002b48: 1a1d subs r5, r3, r0 8002b4a: 45ac cmp ip, r5 8002b4c: 4192 sbcs r2, r2 8002b4e: 9b02 ldr r3, [sp, #8] 8002b50: 4252 negs r2, r2 8002b52: 1b1c subs r4, r3, r4 8002b54: 000e movs r6, r1 8002b56: 4688 mov r8, r1 8002b58: 2701 movs r7, #1 8002b5a: 1aa4 subs r4, r4, r2 8002b5c: e546 b.n 80025ec <__aeabi_dsub+0xc4> 8002b5e: 4663 mov r3, ip 8002b60: 08d9 lsrs r1, r3, #3 8002b62: 9b02 ldr r3, [sp, #8] 8002b64: 075a lsls r2, r3, #29 8002b66: 430a orrs r2, r1 8002b68: 08dc lsrs r4, r3, #3 8002b6a: e5ee b.n 800274a <__aeabi_dsub+0x222> 8002b6c: 4663 mov r3, ip 8002b6e: 9c02 ldr r4, [sp, #8] 8002b70: 9303 str r3, [sp, #12] 8002b72: e6c7 b.n 8002904 <__aeabi_dsub+0x3dc> 8002b74: 08c0 lsrs r0, r0, #3 8002b76: 2a00 cmp r2, #0 8002b78: d100 bne.n 8002b7c <__aeabi_dsub+0x654> 8002b7a: e6aa b.n 80028d2 <__aeabi_dsub+0x3aa> 8002b7c: 0762 lsls r2, r4, #29 8002b7e: 4310 orrs r0, r2 8002b80: 2280 movs r2, #128 @ 0x80 8002b82: 08e4 lsrs r4, r4, #3 8002b84: 0312 lsls r2, r2, #12 8002b86: 4214 tst r4, r2 8002b88: d0d7 beq.n 8002b3a <__aeabi_dsub+0x612> 8002b8a: 9f02 ldr r7, [sp, #8] 8002b8c: 08fd lsrs r5, r7, #3 8002b8e: 4215 tst r5, r2 8002b90: d1d3 bne.n 8002b3a <__aeabi_dsub+0x612> 8002b92: 4663 mov r3, ip 8002b94: 2601 movs r6, #1 8002b96: 08d8 lsrs r0, r3, #3 8002b98: 077b lsls r3, r7, #29 8002b9a: 002c movs r4, r5 8002b9c: 4318 orrs r0, r3 8002b9e: 400e ands r6, r1 8002ba0: e7cb b.n 8002b3a <__aeabi_dsub+0x612> 8002ba2: 000a movs r2, r1 8002ba4: 0027 movs r7, r4 8002ba6: 3a20 subs r2, #32 8002ba8: 40d7 lsrs r7, r2 8002baa: 2920 cmp r1, #32 8002bac: d005 beq.n 8002bba <__aeabi_dsub+0x692> 8002bae: 2240 movs r2, #64 @ 0x40 8002bb0: 1a52 subs r2, r2, r1 8002bb2: 4094 lsls r4, r2 8002bb4: 0025 movs r5, r4 8002bb6: 4305 orrs r5, r0 8002bb8: 9503 str r5, [sp, #12] 8002bba: 9d03 ldr r5, [sp, #12] 8002bbc: 1e6a subs r2, r5, #1 8002bbe: 4195 sbcs r5, r2 8002bc0: 432f orrs r7, r5 8002bc2: e610 b.n 80027e6 <__aeabi_dsub+0x2be> 8002bc4: 0014 movs r4, r2 8002bc6: 2500 movs r5, #0 8002bc8: 2200 movs r2, #0 8002bca: e556 b.n 800267a <__aeabi_dsub+0x152> 8002bcc: 9b02 ldr r3, [sp, #8] 8002bce: 4460 add r0, ip 8002bd0: 4699 mov r9, r3 8002bd2: 4560 cmp r0, ip 8002bd4: 4192 sbcs r2, r2 8002bd6: 444c add r4, r9 8002bd8: 4252 negs r2, r2 8002bda: 0005 movs r5, r0 8002bdc: 18a4 adds r4, r4, r2 8002bde: e74c b.n 8002a7a <__aeabi_dsub+0x552> 8002be0: 001a movs r2, r3 8002be2: 001c movs r4, r3 8002be4: 432a orrs r2, r5 8002be6: d000 beq.n 8002bea <__aeabi_dsub+0x6c2> 8002be8: e6b3 b.n 8002952 <__aeabi_dsub+0x42a> 8002bea: e6c9 b.n 8002980 <__aeabi_dsub+0x458> 8002bec: 2480 movs r4, #128 @ 0x80 8002bee: 2600 movs r6, #0 8002bf0: 0324 lsls r4, r4, #12 8002bf2: e5ae b.n 8002752 <__aeabi_dsub+0x22a> 8002bf4: 2120 movs r1, #32 8002bf6: 2500 movs r5, #0 8002bf8: 1a09 subs r1, r1, r0 8002bfa: e517 b.n 800262c <__aeabi_dsub+0x104> 8002bfc: 2200 movs r2, #0 8002bfe: 2500 movs r5, #0 8002c00: 4c0b ldr r4, [pc, #44] @ (8002c30 <__aeabi_dsub+0x708>) 8002c02: e53a b.n 800267a <__aeabi_dsub+0x152> 8002c04: 2d00 cmp r5, #0 8002c06: d100 bne.n 8002c0a <__aeabi_dsub+0x6e2> 8002c08: e5f6 b.n 80027f8 <__aeabi_dsub+0x2d0> 8002c0a: 464b mov r3, r9 8002c0c: 1bda subs r2, r3, r7 8002c0e: 4692 mov sl, r2 8002c10: 2f00 cmp r7, #0 8002c12: d100 bne.n 8002c16 <__aeabi_dsub+0x6ee> 8002c14: e66f b.n 80028f6 <__aeabi_dsub+0x3ce> 8002c16: 2a38 cmp r2, #56 @ 0x38 8002c18: dc05 bgt.n 8002c26 <__aeabi_dsub+0x6fe> 8002c1a: 2680 movs r6, #128 @ 0x80 8002c1c: 0436 lsls r6, r6, #16 8002c1e: 4334 orrs r4, r6 8002c20: 4688 mov r8, r1 8002c22: 000e movs r6, r1 8002c24: e6d1 b.n 80029ca <__aeabi_dsub+0x4a2> 8002c26: 4688 mov r8, r1 8002c28: 000e movs r6, r1 8002c2a: 2501 movs r5, #1 8002c2c: e6de b.n 80029ec <__aeabi_dsub+0x4c4> 8002c2e: 46c0 nop @ (mov r8, r8) 8002c30: 000007ff .word 0x000007ff 8002c34: ff7fffff .word 0xff7fffff 8002c38: 000007fe .word 0x000007fe 8002c3c: 2d00 cmp r5, #0 8002c3e: d100 bne.n 8002c42 <__aeabi_dsub+0x71a> 8002c40: e668 b.n 8002914 <__aeabi_dsub+0x3ec> 8002c42: 464b mov r3, r9 8002c44: 1bd9 subs r1, r3, r7 8002c46: 2f00 cmp r7, #0 8002c48: d101 bne.n 8002c4e <__aeabi_dsub+0x726> 8002c4a: 468a mov sl, r1 8002c4c: e5a7 b.n 800279e <__aeabi_dsub+0x276> 8002c4e: 2701 movs r7, #1 8002c50: 2938 cmp r1, #56 @ 0x38 8002c52: dd00 ble.n 8002c56 <__aeabi_dsub+0x72e> 8002c54: e5c7 b.n 80027e6 <__aeabi_dsub+0x2be> 8002c56: 2280 movs r2, #128 @ 0x80 8002c58: 0412 lsls r2, r2, #16 8002c5a: 4314 orrs r4, r2 8002c5c: e5af b.n 80027be <__aeabi_dsub+0x296> 8002c5e: 46c0 nop @ (mov r8, r8) 08002c60 <__aeabi_dcmpun>: 8002c60: b5f0 push {r4, r5, r6, r7, lr} 8002c62: 46c6 mov lr, r8 8002c64: 031e lsls r6, r3, #12 8002c66: 0b36 lsrs r6, r6, #12 8002c68: 46b0 mov r8, r6 8002c6a: 4e0d ldr r6, [pc, #52] @ (8002ca0 <__aeabi_dcmpun+0x40>) 8002c6c: 030c lsls r4, r1, #12 8002c6e: 004d lsls r5, r1, #1 8002c70: 005f lsls r7, r3, #1 8002c72: b500 push {lr} 8002c74: 0b24 lsrs r4, r4, #12 8002c76: 0d6d lsrs r5, r5, #21 8002c78: 0d7f lsrs r7, r7, #21 8002c7a: 42b5 cmp r5, r6 8002c7c: d00b beq.n 8002c96 <__aeabi_dcmpun+0x36> 8002c7e: 4908 ldr r1, [pc, #32] @ (8002ca0 <__aeabi_dcmpun+0x40>) 8002c80: 2000 movs r0, #0 8002c82: 428f cmp r7, r1 8002c84: d104 bne.n 8002c90 <__aeabi_dcmpun+0x30> 8002c86: 4646 mov r6, r8 8002c88: 4316 orrs r6, r2 8002c8a: 0030 movs r0, r6 8002c8c: 1e43 subs r3, r0, #1 8002c8e: 4198 sbcs r0, r3 8002c90: bc80 pop {r7} 8002c92: 46b8 mov r8, r7 8002c94: bdf0 pop {r4, r5, r6, r7, pc} 8002c96: 4304 orrs r4, r0 8002c98: 2001 movs r0, #1 8002c9a: 2c00 cmp r4, #0 8002c9c: d1f8 bne.n 8002c90 <__aeabi_dcmpun+0x30> 8002c9e: e7ee b.n 8002c7e <__aeabi_dcmpun+0x1e> 8002ca0: 000007ff .word 0x000007ff 08002ca4 <__aeabi_f2d>: 8002ca4: b570 push {r4, r5, r6, lr} 8002ca6: 0242 lsls r2, r0, #9 8002ca8: 0043 lsls r3, r0, #1 8002caa: 0fc4 lsrs r4, r0, #31 8002cac: 20fe movs r0, #254 @ 0xfe 8002cae: 0e1b lsrs r3, r3, #24 8002cb0: 1c59 adds r1, r3, #1 8002cb2: 0a55 lsrs r5, r2, #9 8002cb4: 4208 tst r0, r1 8002cb6: d00c beq.n 8002cd2 <__aeabi_f2d+0x2e> 8002cb8: 21e0 movs r1, #224 @ 0xe0 8002cba: 0089 lsls r1, r1, #2 8002cbc: 468c mov ip, r1 8002cbe: 076d lsls r5, r5, #29 8002cc0: 0b12 lsrs r2, r2, #12 8002cc2: 4463 add r3, ip 8002cc4: 051b lsls r3, r3, #20 8002cc6: 4313 orrs r3, r2 8002cc8: 07e4 lsls r4, r4, #31 8002cca: 4323 orrs r3, r4 8002ccc: 0028 movs r0, r5 8002cce: 0019 movs r1, r3 8002cd0: bd70 pop {r4, r5, r6, pc} 8002cd2: 2b00 cmp r3, #0 8002cd4: d114 bne.n 8002d00 <__aeabi_f2d+0x5c> 8002cd6: 2d00 cmp r5, #0 8002cd8: d01b beq.n 8002d12 <__aeabi_f2d+0x6e> 8002cda: 0028 movs r0, r5 8002cdc: f000 f8ae bl 8002e3c <__clzsi2> 8002ce0: 280a cmp r0, #10 8002ce2: dc1c bgt.n 8002d1e <__aeabi_f2d+0x7a> 8002ce4: 230b movs r3, #11 8002ce6: 002a movs r2, r5 8002ce8: 1a1b subs r3, r3, r0 8002cea: 40da lsrs r2, r3 8002cec: 0003 movs r3, r0 8002cee: 3315 adds r3, #21 8002cf0: 409d lsls r5, r3 8002cf2: 4b0e ldr r3, [pc, #56] @ (8002d2c <__aeabi_f2d+0x88>) 8002cf4: 0312 lsls r2, r2, #12 8002cf6: 1a1b subs r3, r3, r0 8002cf8: 055b lsls r3, r3, #21 8002cfa: 0b12 lsrs r2, r2, #12 8002cfc: 0d5b lsrs r3, r3, #21 8002cfe: e7e1 b.n 8002cc4 <__aeabi_f2d+0x20> 8002d00: 2d00 cmp r5, #0 8002d02: d009 beq.n 8002d18 <__aeabi_f2d+0x74> 8002d04: 0b13 lsrs r3, r2, #12 8002d06: 2280 movs r2, #128 @ 0x80 8002d08: 0312 lsls r2, r2, #12 8002d0a: 431a orrs r2, r3 8002d0c: 076d lsls r5, r5, #29 8002d0e: 4b08 ldr r3, [pc, #32] @ (8002d30 <__aeabi_f2d+0x8c>) 8002d10: e7d8 b.n 8002cc4 <__aeabi_f2d+0x20> 8002d12: 2300 movs r3, #0 8002d14: 2200 movs r2, #0 8002d16: e7d5 b.n 8002cc4 <__aeabi_f2d+0x20> 8002d18: 2200 movs r2, #0 8002d1a: 4b05 ldr r3, [pc, #20] @ (8002d30 <__aeabi_f2d+0x8c>) 8002d1c: e7d2 b.n 8002cc4 <__aeabi_f2d+0x20> 8002d1e: 0003 movs r3, r0 8002d20: 002a movs r2, r5 8002d22: 3b0b subs r3, #11 8002d24: 409a lsls r2, r3 8002d26: 2500 movs r5, #0 8002d28: e7e3 b.n 8002cf2 <__aeabi_f2d+0x4e> 8002d2a: 46c0 nop @ (mov r8, r8) 8002d2c: 00000389 .word 0x00000389 8002d30: 000007ff .word 0x000007ff 08002d34 <__aeabi_d2f>: 8002d34: b5f0 push {r4, r5, r6, r7, lr} 8002d36: 004b lsls r3, r1, #1 8002d38: 030f lsls r7, r1, #12 8002d3a: 0d5b lsrs r3, r3, #21 8002d3c: 4c3b ldr r4, [pc, #236] @ (8002e2c <__aeabi_d2f+0xf8>) 8002d3e: 0f45 lsrs r5, r0, #29 8002d40: b083 sub sp, #12 8002d42: 0a7f lsrs r7, r7, #9 8002d44: 1c5e adds r6, r3, #1 8002d46: 432f orrs r7, r5 8002d48: 9000 str r0, [sp, #0] 8002d4a: 9101 str r1, [sp, #4] 8002d4c: 0fca lsrs r2, r1, #31 8002d4e: 00c5 lsls r5, r0, #3 8002d50: 4226 tst r6, r4 8002d52: d00b beq.n 8002d6c <__aeabi_d2f+0x38> 8002d54: 4936 ldr r1, [pc, #216] @ (8002e30 <__aeabi_d2f+0xfc>) 8002d56: 185c adds r4, r3, r1 8002d58: 2cfe cmp r4, #254 @ 0xfe 8002d5a: dd13 ble.n 8002d84 <__aeabi_d2f+0x50> 8002d5c: 20ff movs r0, #255 @ 0xff 8002d5e: 2300 movs r3, #0 8002d60: 05c0 lsls r0, r0, #23 8002d62: 4318 orrs r0, r3 8002d64: 07d2 lsls r2, r2, #31 8002d66: 4310 orrs r0, r2 8002d68: b003 add sp, #12 8002d6a: bdf0 pop {r4, r5, r6, r7, pc} 8002d6c: 2b00 cmp r3, #0 8002d6e: d102 bne.n 8002d76 <__aeabi_d2f+0x42> 8002d70: 2000 movs r0, #0 8002d72: 2300 movs r3, #0 8002d74: e7f4 b.n 8002d60 <__aeabi_d2f+0x2c> 8002d76: 433d orrs r5, r7 8002d78: d0f0 beq.n 8002d5c <__aeabi_d2f+0x28> 8002d7a: 2380 movs r3, #128 @ 0x80 8002d7c: 03db lsls r3, r3, #15 8002d7e: 20ff movs r0, #255 @ 0xff 8002d80: 433b orrs r3, r7 8002d82: e7ed b.n 8002d60 <__aeabi_d2f+0x2c> 8002d84: 2c00 cmp r4, #0 8002d86: dd14 ble.n 8002db2 <__aeabi_d2f+0x7e> 8002d88: 9b00 ldr r3, [sp, #0] 8002d8a: 00ff lsls r7, r7, #3 8002d8c: 019b lsls r3, r3, #6 8002d8e: 1e58 subs r0, r3, #1 8002d90: 4183 sbcs r3, r0 8002d92: 0f69 lsrs r1, r5, #29 8002d94: 433b orrs r3, r7 8002d96: 430b orrs r3, r1 8002d98: 0759 lsls r1, r3, #29 8002d9a: d041 beq.n 8002e20 <__aeabi_d2f+0xec> 8002d9c: 210f movs r1, #15 8002d9e: 4019 ands r1, r3 8002da0: 2904 cmp r1, #4 8002da2: d028 beq.n 8002df6 <__aeabi_d2f+0xc2> 8002da4: 3304 adds r3, #4 8002da6: 0159 lsls r1, r3, #5 8002da8: d525 bpl.n 8002df6 <__aeabi_d2f+0xc2> 8002daa: 3401 adds r4, #1 8002dac: 2300 movs r3, #0 8002dae: b2e0 uxtb r0, r4 8002db0: e7d6 b.n 8002d60 <__aeabi_d2f+0x2c> 8002db2: 0021 movs r1, r4 8002db4: 3117 adds r1, #23 8002db6: dbdb blt.n 8002d70 <__aeabi_d2f+0x3c> 8002db8: 2180 movs r1, #128 @ 0x80 8002dba: 201e movs r0, #30 8002dbc: 0409 lsls r1, r1, #16 8002dbe: 4339 orrs r1, r7 8002dc0: 1b00 subs r0, r0, r4 8002dc2: 281f cmp r0, #31 8002dc4: dd1b ble.n 8002dfe <__aeabi_d2f+0xca> 8002dc6: 2602 movs r6, #2 8002dc8: 4276 negs r6, r6 8002dca: 1b34 subs r4, r6, r4 8002dcc: 000e movs r6, r1 8002dce: 40e6 lsrs r6, r4 8002dd0: 0034 movs r4, r6 8002dd2: 2820 cmp r0, #32 8002dd4: d004 beq.n 8002de0 <__aeabi_d2f+0xac> 8002dd6: 4817 ldr r0, [pc, #92] @ (8002e34 <__aeabi_d2f+0x100>) 8002dd8: 4684 mov ip, r0 8002dda: 4463 add r3, ip 8002ddc: 4099 lsls r1, r3 8002dde: 430d orrs r5, r1 8002de0: 002b movs r3, r5 8002de2: 1e59 subs r1, r3, #1 8002de4: 418b sbcs r3, r1 8002de6: 4323 orrs r3, r4 8002de8: 0759 lsls r1, r3, #29 8002dea: d015 beq.n 8002e18 <__aeabi_d2f+0xe4> 8002dec: 210f movs r1, #15 8002dee: 2400 movs r4, #0 8002df0: 4019 ands r1, r3 8002df2: 2904 cmp r1, #4 8002df4: d117 bne.n 8002e26 <__aeabi_d2f+0xf2> 8002df6: 019b lsls r3, r3, #6 8002df8: 0a5b lsrs r3, r3, #9 8002dfa: b2e0 uxtb r0, r4 8002dfc: e7b0 b.n 8002d60 <__aeabi_d2f+0x2c> 8002dfe: 4c0e ldr r4, [pc, #56] @ (8002e38 <__aeabi_d2f+0x104>) 8002e00: 191c adds r4, r3, r4 8002e02: 002b movs r3, r5 8002e04: 40a5 lsls r5, r4 8002e06: 40c3 lsrs r3, r0 8002e08: 40a1 lsls r1, r4 8002e0a: 1e68 subs r0, r5, #1 8002e0c: 4185 sbcs r5, r0 8002e0e: 4329 orrs r1, r5 8002e10: 430b orrs r3, r1 8002e12: 2400 movs r4, #0 8002e14: 0759 lsls r1, r3, #29 8002e16: d1c1 bne.n 8002d9c <__aeabi_d2f+0x68> 8002e18: 019b lsls r3, r3, #6 8002e1a: 2000 movs r0, #0 8002e1c: 0a5b lsrs r3, r3, #9 8002e1e: e79f b.n 8002d60 <__aeabi_d2f+0x2c> 8002e20: 08db lsrs r3, r3, #3 8002e22: b2e0 uxtb r0, r4 8002e24: e79c b.n 8002d60 <__aeabi_d2f+0x2c> 8002e26: 3304 adds r3, #4 8002e28: e7e5 b.n 8002df6 <__aeabi_d2f+0xc2> 8002e2a: 46c0 nop @ (mov r8, r8) 8002e2c: 000007fe .word 0x000007fe 8002e30: fffffc80 .word 0xfffffc80 8002e34: fffffca2 .word 0xfffffca2 8002e38: fffffc82 .word 0xfffffc82 08002e3c <__clzsi2>: 8002e3c: 211c movs r1, #28 8002e3e: 2301 movs r3, #1 8002e40: 041b lsls r3, r3, #16 8002e42: 4298 cmp r0, r3 8002e44: d301 bcc.n 8002e4a <__clzsi2+0xe> 8002e46: 0c00 lsrs r0, r0, #16 8002e48: 3910 subs r1, #16 8002e4a: 0a1b lsrs r3, r3, #8 8002e4c: 4298 cmp r0, r3 8002e4e: d301 bcc.n 8002e54 <__clzsi2+0x18> 8002e50: 0a00 lsrs r0, r0, #8 8002e52: 3908 subs r1, #8 8002e54: 091b lsrs r3, r3, #4 8002e56: 4298 cmp r0, r3 8002e58: d301 bcc.n 8002e5e <__clzsi2+0x22> 8002e5a: 0900 lsrs r0, r0, #4 8002e5c: 3904 subs r1, #4 8002e5e: a202 add r2, pc, #8 @ (adr r2, 8002e68 <__clzsi2+0x2c>) 8002e60: 5c10 ldrb r0, [r2, r0] 8002e62: 1840 adds r0, r0, r1 8002e64: 4770 bx lr 8002e66: 46c0 nop @ (mov r8, r8) 8002e68: 02020304 .word 0x02020304 8002e6c: 01010101 .word 0x01010101 ... 08002e78 : /** * @brief Converts raw sensor data to usable format * @retval none */ void MPU6000_Raw_Data_Convert(){ 8002e78: b580 push {r7, lr} 8002e7a: b082 sub sp, #8 8002e7c: af00 add r7, sp, #0 for(int i = 0; i < 6; i++){ 8002e7e: 2300 movs r3, #0 8002e80: 607b str r3, [r7, #4] 8002e82: e01d b.n 8002ec0 IMU.accel_data[i] = IMU.all_data[i]; 8002e84: 4a6c ldr r2, [pc, #432] @ (8003038 ) 8002e86: 213c movs r1, #60 @ 0x3c 8002e88: 687b ldr r3, [r7, #4] 8002e8a: 18d3 adds r3, r2, r3 8002e8c: 185b adds r3, r3, r1 8002e8e: 7818 ldrb r0, [r3, #0] 8002e90: 4a69 ldr r2, [pc, #420] @ (8003038 ) 8002e92: 2136 movs r1, #54 @ 0x36 8002e94: 687b ldr r3, [r7, #4] 8002e96: 18d3 adds r3, r2, r3 8002e98: 185b adds r3, r3, r1 8002e9a: 1c02 adds r2, r0, #0 8002e9c: 701a strb r2, [r3, #0] IMU.gyro_data[i] = IMU.all_data[i+8]; 8002e9e: 687b ldr r3, [r7, #4] 8002ea0: 3308 adds r3, #8 8002ea2: 4a65 ldr r2, [pc, #404] @ (8003038 ) 8002ea4: 213c movs r1, #60 @ 0x3c 8002ea6: 18d3 adds r3, r2, r3 8002ea8: 185b adds r3, r3, r1 8002eaa: 7818 ldrb r0, [r3, #0] 8002eac: 4a62 ldr r2, [pc, #392] @ (8003038 ) 8002eae: 2130 movs r1, #48 @ 0x30 8002eb0: 687b ldr r3, [r7, #4] 8002eb2: 18d3 adds r3, r2, r3 8002eb4: 185b adds r3, r3, r1 8002eb6: 1c02 adds r2, r0, #0 8002eb8: 701a strb r2, [r3, #0] for(int i = 0; i < 6; i++){ 8002eba: 687b ldr r3, [r7, #4] 8002ebc: 3301 adds r3, #1 8002ebe: 607b str r3, [r7, #4] 8002ec0: 687b ldr r3, [r7, #4] 8002ec2: 2b05 cmp r3, #5 8002ec4: ddde ble.n 8002e84 } IMU.g_x = (float)((int16_t)(IMU.gyro_data[0] * 256 + IMU.gyro_data[1]) - IMU.cal_g_x) / IMU.gyro_LSB; 8002ec6: 4b5c ldr r3, [pc, #368] @ (8003038 ) 8002ec8: 2230 movs r2, #48 @ 0x30 8002eca: 5c9b ldrb r3, [r3, r2] 8002ecc: 021b lsls r3, r3, #8 8002ece: b29b uxth r3, r3 8002ed0: 4a59 ldr r2, [pc, #356] @ (8003038 ) 8002ed2: 2131 movs r1, #49 @ 0x31 8002ed4: 5c52 ldrb r2, [r2, r1] 8002ed6: 189b adds r3, r3, r2 8002ed8: b29b uxth r3, r3 8002eda: b21b sxth r3, r3 8002edc: 001a movs r2, r3 8002ede: 4b56 ldr r3, [pc, #344] @ (8003038 ) 8002ee0: 2118 movs r1, #24 8002ee2: 5e5b ldrsh r3, [r3, r1] 8002ee4: 1ad3 subs r3, r2, r3 8002ee6: 0018 movs r0, r3 8002ee8: f7fe f862 bl 8000fb0 <__aeabi_i2f> 8002eec: 1c02 adds r2, r0, #0 8002eee: 4b52 ldr r3, [pc, #328] @ (8003038 ) 8002ef0: 6cdb ldr r3, [r3, #76] @ 0x4c 8002ef2: 1c19 adds r1, r3, #0 8002ef4: 1c10 adds r0, r2, #0 8002ef6: f7fd fb93 bl 8000620 <__aeabi_fdiv> 8002efa: 1c03 adds r3, r0, #0 8002efc: 1c1a adds r2, r3, #0 8002efe: 4b4e ldr r3, [pc, #312] @ (8003038 ) 8002f00: 601a str r2, [r3, #0] IMU.g_y = (float)((int16_t)(IMU.gyro_data[2] * 256 + IMU.gyro_data[3]) - IMU.cal_g_y) / IMU.gyro_LSB; 8002f02: 4b4d ldr r3, [pc, #308] @ (8003038 ) 8002f04: 2232 movs r2, #50 @ 0x32 8002f06: 5c9b ldrb r3, [r3, r2] 8002f08: 021b lsls r3, r3, #8 8002f0a: b29b uxth r3, r3 8002f0c: 4a4a ldr r2, [pc, #296] @ (8003038 ) 8002f0e: 2133 movs r1, #51 @ 0x33 8002f10: 5c52 ldrb r2, [r2, r1] 8002f12: 189b adds r3, r3, r2 8002f14: b29b uxth r3, r3 8002f16: b21b sxth r3, r3 8002f18: 001a movs r2, r3 8002f1a: 4b47 ldr r3, [pc, #284] @ (8003038 ) 8002f1c: 211a movs r1, #26 8002f1e: 5e5b ldrsh r3, [r3, r1] 8002f20: 1ad3 subs r3, r2, r3 8002f22: 0018 movs r0, r3 8002f24: f7fe f844 bl 8000fb0 <__aeabi_i2f> 8002f28: 1c02 adds r2, r0, #0 8002f2a: 4b43 ldr r3, [pc, #268] @ (8003038 ) 8002f2c: 6cdb ldr r3, [r3, #76] @ 0x4c 8002f2e: 1c19 adds r1, r3, #0 8002f30: 1c10 adds r0, r2, #0 8002f32: f7fd fb75 bl 8000620 <__aeabi_fdiv> 8002f36: 1c03 adds r3, r0, #0 8002f38: 1c1a adds r2, r3, #0 8002f3a: 4b3f ldr r3, [pc, #252] @ (8003038 ) 8002f3c: 605a str r2, [r3, #4] IMU.g_z = (float)((int16_t)(IMU.gyro_data[4] * 256 + IMU.gyro_data[5]) - IMU.cal_g_z) / IMU.gyro_LSB; 8002f3e: 4b3e ldr r3, [pc, #248] @ (8003038 ) 8002f40: 2234 movs r2, #52 @ 0x34 8002f42: 5c9b ldrb r3, [r3, r2] 8002f44: 021b lsls r3, r3, #8 8002f46: b29b uxth r3, r3 8002f48: 4a3b ldr r2, [pc, #236] @ (8003038 ) 8002f4a: 2135 movs r1, #53 @ 0x35 8002f4c: 5c52 ldrb r2, [r2, r1] 8002f4e: 189b adds r3, r3, r2 8002f50: b29b uxth r3, r3 8002f52: b21b sxth r3, r3 8002f54: 001a movs r2, r3 8002f56: 4b38 ldr r3, [pc, #224] @ (8003038 ) 8002f58: 211c movs r1, #28 8002f5a: 5e5b ldrsh r3, [r3, r1] 8002f5c: 1ad3 subs r3, r2, r3 8002f5e: 0018 movs r0, r3 8002f60: f7fe f826 bl 8000fb0 <__aeabi_i2f> 8002f64: 1c02 adds r2, r0, #0 8002f66: 4b34 ldr r3, [pc, #208] @ (8003038 ) 8002f68: 6cdb ldr r3, [r3, #76] @ 0x4c 8002f6a: 1c19 adds r1, r3, #0 8002f6c: 1c10 adds r0, r2, #0 8002f6e: f7fd fb57 bl 8000620 <__aeabi_fdiv> 8002f72: 1c03 adds r3, r0, #0 8002f74: 1c1a adds r2, r3, #0 8002f76: 4b30 ldr r3, [pc, #192] @ (8003038 ) 8002f78: 609a str r2, [r3, #8] IMU.a_x = (float)((int16_t)(IMU.accel_data[0] * 256 + IMU.accel_data[1]) - IMU.cal_a_x) / IMU.accel_LSB; 8002f7a: 4b2f ldr r3, [pc, #188] @ (8003038 ) 8002f7c: 2236 movs r2, #54 @ 0x36 8002f7e: 5c9b ldrb r3, [r3, r2] 8002f80: 021b lsls r3, r3, #8 8002f82: b29b uxth r3, r3 8002f84: 4a2c ldr r2, [pc, #176] @ (8003038 ) 8002f86: 2137 movs r1, #55 @ 0x37 8002f88: 5c52 ldrb r2, [r2, r1] 8002f8a: 189b adds r3, r3, r2 8002f8c: b29b uxth r3, r3 8002f8e: b21b sxth r3, r3 8002f90: 001a movs r2, r3 8002f92: 4b29 ldr r3, [pc, #164] @ (8003038 ) 8002f94: 211e movs r1, #30 8002f96: 5e5b ldrsh r3, [r3, r1] 8002f98: 1ad3 subs r3, r2, r3 8002f9a: 0018 movs r0, r3 8002f9c: f7fe f808 bl 8000fb0 <__aeabi_i2f> 8002fa0: 1c02 adds r2, r0, #0 8002fa2: 4b25 ldr r3, [pc, #148] @ (8003038 ) 8002fa4: 6d1b ldr r3, [r3, #80] @ 0x50 8002fa6: 1c19 adds r1, r3, #0 8002fa8: 1c10 adds r0, r2, #0 8002faa: f7fd fb39 bl 8000620 <__aeabi_fdiv> 8002fae: 1c03 adds r3, r0, #0 8002fb0: 1c1a adds r2, r3, #0 8002fb2: 4b21 ldr r3, [pc, #132] @ (8003038 ) 8002fb4: 60da str r2, [r3, #12] IMU.a_y = (float)((int16_t)(IMU.accel_data[2] * 256 + IMU.accel_data[3]) - IMU.cal_a_y) / IMU.accel_LSB; 8002fb6: 4b20 ldr r3, [pc, #128] @ (8003038 ) 8002fb8: 2238 movs r2, #56 @ 0x38 8002fba: 5c9b ldrb r3, [r3, r2] 8002fbc: 021b lsls r3, r3, #8 8002fbe: b29b uxth r3, r3 8002fc0: 4a1d ldr r2, [pc, #116] @ (8003038 ) 8002fc2: 2139 movs r1, #57 @ 0x39 8002fc4: 5c52 ldrb r2, [r2, r1] 8002fc6: 189b adds r3, r3, r2 8002fc8: b29b uxth r3, r3 8002fca: b21b sxth r3, r3 8002fcc: 001a movs r2, r3 8002fce: 4b1a ldr r3, [pc, #104] @ (8003038 ) 8002fd0: 2120 movs r1, #32 8002fd2: 5e5b ldrsh r3, [r3, r1] 8002fd4: 1ad3 subs r3, r2, r3 8002fd6: 0018 movs r0, r3 8002fd8: f7fd ffea bl 8000fb0 <__aeabi_i2f> 8002fdc: 1c02 adds r2, r0, #0 8002fde: 4b16 ldr r3, [pc, #88] @ (8003038 ) 8002fe0: 6d1b ldr r3, [r3, #80] @ 0x50 8002fe2: 1c19 adds r1, r3, #0 8002fe4: 1c10 adds r0, r2, #0 8002fe6: f7fd fb1b bl 8000620 <__aeabi_fdiv> 8002fea: 1c03 adds r3, r0, #0 8002fec: 1c1a adds r2, r3, #0 8002fee: 4b12 ldr r3, [pc, #72] @ (8003038 ) 8002ff0: 611a str r2, [r3, #16] IMU.a_z = (float)((int16_t)(IMU.accel_data[4] * 256 + IMU.accel_data[5]) - IMU.cal_a_z) / IMU.accel_LSB; 8002ff2: 4b11 ldr r3, [pc, #68] @ (8003038 ) 8002ff4: 223a movs r2, #58 @ 0x3a 8002ff6: 5c9b ldrb r3, [r3, r2] 8002ff8: 021b lsls r3, r3, #8 8002ffa: b29b uxth r3, r3 8002ffc: 4a0e ldr r2, [pc, #56] @ (8003038 ) 8002ffe: 213b movs r1, #59 @ 0x3b 8003000: 5c52 ldrb r2, [r2, r1] 8003002: 189b adds r3, r3, r2 8003004: b29b uxth r3, r3 8003006: b21b sxth r3, r3 8003008: 001a movs r2, r3 800300a: 4b0b ldr r3, [pc, #44] @ (8003038 ) 800300c: 2122 movs r1, #34 @ 0x22 800300e: 5e5b ldrsh r3, [r3, r1] 8003010: 1ad3 subs r3, r2, r3 8003012: 0018 movs r0, r3 8003014: f7fd ffcc bl 8000fb0 <__aeabi_i2f> 8003018: 1c02 adds r2, r0, #0 800301a: 4b07 ldr r3, [pc, #28] @ (8003038 ) 800301c: 6d1b ldr r3, [r3, #80] @ 0x50 800301e: 1c19 adds r1, r3, #0 8003020: 1c10 adds r0, r2, #0 8003022: f7fd fafd bl 8000620 <__aeabi_fdiv> 8003026: 1c03 adds r3, r0, #0 8003028: 1c1a adds r2, r3, #0 800302a: 4b03 ldr r3, [pc, #12] @ (8003038 ) 800302c: 615a str r2, [r3, #20] } 800302e: 46c0 nop @ (mov r8, r8) 8003030: 46bd mov sp, r7 8003032: b002 add sp, #8 8003034: bd80 pop {r7, pc} 8003036: 46c0 nop @ (mov r8, r8) 8003038: 2000008c .word 0x2000008c 0800303c : /** * @brief Read all data on the sensor * @retval none */ void MPU6000_readAll(){ 800303c: b580 push {r7, lr} 800303e: b082 sub sp, #8 8003040: af02 add r7, sp, #8 HAL_I2C_Mem_Read_IT(IMU.peripheral,(MPU6000_ADDRESS << 1),ACCEL_XOUT_H,1,IMU.all_data,14); 8003042: 4b07 ldr r3, [pc, #28] @ (8003060 ) 8003044: 4a07 ldr r2, [pc, #28] @ (8003064 ) 8003046: 5898 ldr r0, [r3, r2] 8003048: 230e movs r3, #14 800304a: 9301 str r3, [sp, #4] 800304c: 4b06 ldr r3, [pc, #24] @ (8003068 ) 800304e: 9300 str r3, [sp, #0] 8003050: 2301 movs r3, #1 8003052: 223b movs r2, #59 @ 0x3b 8003054: 21d0 movs r1, #208 @ 0xd0 8003056: f002 f835 bl 80050c4 } 800305a: 46c0 nop @ (mov r8, r8) 800305c: 46bd mov sp, r7 800305e: bd80 pop {r7, pc} 8003060: 2000008c .word 0x2000008c 8003064: 00000854 .word 0x00000854 8003068: 200000c8 .word 0x200000c8 0800306c : * @brief Initialization function of MPU6000 library * @param i2c peripheral to be used * @param i2c timeout * @retval none */ int MPU6000_Init(I2C_HandleTypeDef *hi2c, uint32_t timeout){ 800306c: b590 push {r4, r7, lr} 800306e: b08b sub sp, #44 @ 0x2c 8003070: af04 add r7, sp, #16 8003072: 6078 str r0, [r7, #4] 8003074: 6039 str r1, [r7, #0] uint8_t data; IMU.accel_LSB = 16384; 8003076: 4b55 ldr r3, [pc, #340] @ (80031cc ) 8003078: 228d movs r2, #141 @ 0x8d 800307a: 05d2 lsls r2, r2, #23 800307c: 651a str r2, [r3, #80] @ 0x50 IMU.gyro_LSB = 131; 800307e: 4b53 ldr r3, [pc, #332] @ (80031cc ) 8003080: 4a53 ldr r2, [pc, #332] @ (80031d0 ) 8003082: 64da str r2, [r3, #76] @ 0x4c IMU.peripheral = hi2c; 8003084: 4b51 ldr r3, [pc, #324] @ (80031cc ) 8003086: 4953 ldr r1, [pc, #332] @ (80031d4 ) 8003088: 687a ldr r2, [r7, #4] 800308a: 505a str r2, [r3, r1] IMU.timeout = timeout; 800308c: 4b4f ldr r3, [pc, #316] @ (80031cc ) 800308e: 4952 ldr r1, [pc, #328] @ (80031d8 ) 8003090: 683a ldr r2, [r7, #0] 8003092: 505a str r2, [r3, r1] IMU.dataReady = 0; 8003094: 4b4d ldr r3, [pc, #308] @ (80031cc ) 8003096: 4a51 ldr r2, [pc, #324] @ (80031dc ) 8003098: 2100 movs r1, #0 800309a: 5499 strb r1, [r3, r2] madgwick_cfg_t madgwick_cfg; madgwick_cfg.beta = MADGWICK_BETA; 800309c: 210c movs r1, #12 800309e: 187b adds r3, r7, r1 80030a0: 4a4f ldr r2, [pc, #316] @ (80031e0 ) 80030a2: 601a str r2, [r3, #0] madgwick_cfg.sample_freq = MADGWICK_SAMPLE_RATE; 80030a4: 187b adds r3, r7, r1 80030a6: 4a4f ldr r2, [pc, #316] @ (80031e4 ) 80030a8: 605a str r2, [r3, #4] madgwick_handle = madgwick_init(&madgwick_cfg); 80030aa: 187b adds r3, r7, r1 80030ac: 0018 movs r0, r3 80030ae: f000 fa3d bl 800352c 80030b2: 0002 movs r2, r0 80030b4: 4b4c ldr r3, [pc, #304] @ (80031e8 ) 80030b6: 601a str r2, [r3, #0] if(HAL_I2C_IsDeviceReady(hi2c, (uint16_t)(MPU6000_ADDRESS << 1), 3, IMU.timeout) != 0){ 80030b8: 4b44 ldr r3, [pc, #272] @ (80031cc ) 80030ba: 4a47 ldr r2, [pc, #284] @ (80031d8 ) 80030bc: 589b ldr r3, [r3, r2] 80030be: 6878 ldr r0, [r7, #4] 80030c0: 2203 movs r2, #3 80030c2: 21d0 movs r1, #208 @ 0xd0 80030c4: f002 f89c bl 8005200 80030c8: 1e03 subs r3, r0, #0 80030ca: d001 beq.n 80030d0 return 1; 80030cc: 2301 movs r3, #1 80030ce: e079 b.n 80031c4 } data = 0x00; 80030d0: 2117 movs r1, #23 80030d2: 187b adds r3, r7, r1 80030d4: 2200 movs r2, #0 80030d6: 701a strb r2, [r3, #0] HAL_I2C_Mem_Write(IMU.peripheral,(MPU6000_ADDRESS << 1),PWR_MGMT_1,1,&data,1,IMU.timeout); 80030d8: 4b3c ldr r3, [pc, #240] @ (80031cc ) 80030da: 4a3e ldr r2, [pc, #248] @ (80031d4 ) 80030dc: 5898 ldr r0, [r3, r2] 80030de: 4b3b ldr r3, [pc, #236] @ (80031cc ) 80030e0: 4a3d ldr r2, [pc, #244] @ (80031d8 ) 80030e2: 589b ldr r3, [r3, r2] 80030e4: 9302 str r3, [sp, #8] 80030e6: 2301 movs r3, #1 80030e8: 9301 str r3, [sp, #4] 80030ea: 000c movs r4, r1 80030ec: 187b adds r3, r7, r1 80030ee: 9300 str r3, [sp, #0] 80030f0: 2301 movs r3, #1 80030f2: 226b movs r2, #107 @ 0x6b 80030f4: 21d0 movs r1, #208 @ 0xd0 80030f6: f001 feb7 bl 8004e68 HAL_Delay(200); 80030fa: 20c8 movs r0, #200 @ 0xc8 80030fc: f001 fb14 bl 8004728 data = 0x07; 8003100: 0021 movs r1, r4 8003102: 187b adds r3, r7, r1 8003104: 2207 movs r2, #7 8003106: 701a strb r2, [r3, #0] HAL_I2C_Mem_Write(IMU.peripheral,(MPU6000_ADDRESS << 1),SMPLRT_DIV,1,&data,1,IMU.timeout); 8003108: 4b30 ldr r3, [pc, #192] @ (80031cc ) 800310a: 4a32 ldr r2, [pc, #200] @ (80031d4 ) 800310c: 5898 ldr r0, [r3, r2] 800310e: 4b2f ldr r3, [pc, #188] @ (80031cc ) 8003110: 4a31 ldr r2, [pc, #196] @ (80031d8 ) 8003112: 589b ldr r3, [r3, r2] 8003114: 9302 str r3, [sp, #8] 8003116: 2301 movs r3, #1 8003118: 9301 str r3, [sp, #4] 800311a: 000c movs r4, r1 800311c: 187b adds r3, r7, r1 800311e: 9300 str r3, [sp, #0] 8003120: 2301 movs r3, #1 8003122: 2219 movs r2, #25 8003124: 21d0 movs r1, #208 @ 0xd0 8003126: f001 fe9f bl 8004e68 HAL_Delay(50); 800312a: 2032 movs r0, #50 @ 0x32 800312c: f001 fafc bl 8004728 data = 0x00; 8003130: 0021 movs r1, r4 8003132: 187b adds r3, r7, r1 8003134: 2200 movs r2, #0 8003136: 701a strb r2, [r3, #0] HAL_I2C_Mem_Write(IMU.peripheral,(MPU6000_ADDRESS << 1),ACCEL_CONFIG,1,&data,1,IMU.timeout); 8003138: 4b24 ldr r3, [pc, #144] @ (80031cc ) 800313a: 4a26 ldr r2, [pc, #152] @ (80031d4 ) 800313c: 5898 ldr r0, [r3, r2] 800313e: 4b23 ldr r3, [pc, #140] @ (80031cc ) 8003140: 4a25 ldr r2, [pc, #148] @ (80031d8 ) 8003142: 589b ldr r3, [r3, r2] 8003144: 9302 str r3, [sp, #8] 8003146: 2301 movs r3, #1 8003148: 9301 str r3, [sp, #4] 800314a: 000c movs r4, r1 800314c: 187b adds r3, r7, r1 800314e: 9300 str r3, [sp, #0] 8003150: 2301 movs r3, #1 8003152: 221c movs r2, #28 8003154: 21d0 movs r1, #208 @ 0xd0 8003156: f001 fe87 bl 8004e68 HAL_Delay(50); 800315a: 2032 movs r0, #50 @ 0x32 800315c: f001 fae4 bl 8004728 data = 0x00; 8003160: 0021 movs r1, r4 8003162: 187b adds r3, r7, r1 8003164: 2200 movs r2, #0 8003166: 701a strb r2, [r3, #0] HAL_I2C_Mem_Write(IMU.peripheral,(MPU6000_ADDRESS << 1),GYRO_CONFIG,1,&data,1,IMU.timeout); 8003168: 4b18 ldr r3, [pc, #96] @ (80031cc ) 800316a: 4a1a ldr r2, [pc, #104] @ (80031d4 ) 800316c: 5898 ldr r0, [r3, r2] 800316e: 4b17 ldr r3, [pc, #92] @ (80031cc ) 8003170: 4a19 ldr r2, [pc, #100] @ (80031d8 ) 8003172: 589b ldr r3, [r3, r2] 8003174: 9302 str r3, [sp, #8] 8003176: 2301 movs r3, #1 8003178: 9301 str r3, [sp, #4] 800317a: 000c movs r4, r1 800317c: 187b adds r3, r7, r1 800317e: 9300 str r3, [sp, #0] 8003180: 2301 movs r3, #1 8003182: 221b movs r2, #27 8003184: 21d0 movs r1, #208 @ 0xd0 8003186: f001 fe6f bl 8004e68 HAL_Delay(50); 800318a: 2032 movs r0, #50 @ 0x32 800318c: f001 facc bl 8004728 // HAL_I2C_Mem_Write(IMU.peripheral,(MPU6000_ADDRESS << 1),PWR_MGMT_1,1,&data,1,IMU.timeout); // HAL_Delay(50); // data = 0x08;//0x28 pro lowpower rezim s frekvenci 1.25Hz // HAL_I2C_Mem_Write(IMU.peripheral,(MPU6000_ADDRESS << 1),PWR_MGMT_1,1,&data,1,IMU.timeout); // HAL_Delay(50); data = 0x00; 8003190: 0021 movs r1, r4 8003192: 187b adds r3, r7, r1 8003194: 2200 movs r2, #0 8003196: 701a strb r2, [r3, #0] HAL_I2C_Mem_Write(IMU.peripheral,(MPU6000_ADDRESS << 1),PWR_MGMT_2,1,&data,1,IMU.timeout); 8003198: 4b0c ldr r3, [pc, #48] @ (80031cc ) 800319a: 4a0e ldr r2, [pc, #56] @ (80031d4 ) 800319c: 5898 ldr r0, [r3, r2] 800319e: 4b0b ldr r3, [pc, #44] @ (80031cc ) 80031a0: 4a0d ldr r2, [pc, #52] @ (80031d8 ) 80031a2: 589b ldr r3, [r3, r2] 80031a4: 9302 str r3, [sp, #8] 80031a6: 2301 movs r3, #1 80031a8: 9301 str r3, [sp, #4] 80031aa: 187b adds r3, r7, r1 80031ac: 9300 str r3, [sp, #0] 80031ae: 2301 movs r3, #1 80031b0: 226c movs r2, #108 @ 0x6c 80031b2: 21d0 movs r1, #208 @ 0xd0 80031b4: f001 fe58 bl 8004e68 HAL_Delay(50); 80031b8: 2032 movs r0, #50 @ 0x32 80031ba: f001 fab5 bl 8004728 MPU6000_readAll(); 80031be: f7ff ff3d bl 800303c return 0; 80031c2: 2300 movs r3, #0 } 80031c4: 0018 movs r0, r3 80031c6: 46bd mov sp, r7 80031c8: b007 add sp, #28 80031ca: bd90 pop {r4, r7, pc} 80031cc: 2000008c .word 0x2000008c 80031d0: 43030000 .word 0x43030000 80031d4: 00000854 .word 0x00000854 80031d8: 00000858 .word 0x00000858 80031dc: 0000085c .word 0x0000085c 80031e0: 3e4ccccd .word 0x3e4ccccd 80031e4: 437a0000 .word 0x437a0000 80031e8: 200008ec .word 0x200008ec 080031ec : /** * @brief Function to be put into i2c callback function * @retval none */ void MPU6000_I2C_CallbackFunc(I2C_HandleTypeDef *hi2c){ 80031ec: b580 push {r7, lr} 80031ee: b082 sub sp, #8 80031f0: af00 add r7, sp, #0 80031f2: 6078 str r0, [r7, #4] if(hi2c -> Instance == IMU.peripheral->Instance){ 80031f4: 687b ldr r3, [r7, #4] 80031f6: 681a ldr r2, [r3, #0] 80031f8: 4b0c ldr r3, [pc, #48] @ (800322c ) 80031fa: 490d ldr r1, [pc, #52] @ (8003230 ) 80031fc: 585b ldr r3, [r3, r1] 80031fe: 681b ldr r3, [r3, #0] 8003200: 429a cmp r2, r3 8003202: d10f bne.n 8003224 IMU.peripheral->Instance->CR1 &= ~(1 << 1); 8003204: 4b09 ldr r3, [pc, #36] @ (800322c ) 8003206: 4a0a ldr r2, [pc, #40] @ (8003230 ) 8003208: 589b ldr r3, [r3, r2] 800320a: 681b ldr r3, [r3, #0] 800320c: 681a ldr r2, [r3, #0] 800320e: 4b07 ldr r3, [pc, #28] @ (800322c ) 8003210: 4907 ldr r1, [pc, #28] @ (8003230 ) 8003212: 585b ldr r3, [r3, r1] 8003214: 681b ldr r3, [r3, #0] 8003216: 2102 movs r1, #2 8003218: 438a bics r2, r1 800321a: 601a str r2, [r3, #0] IMU.dataReady = 1; 800321c: 4b03 ldr r3, [pc, #12] @ (800322c ) 800321e: 4a05 ldr r2, [pc, #20] @ (8003234 ) 8003220: 2101 movs r1, #1 8003222: 5499 strb r1, [r3, r2] // IMU.yaw = 180.0 / 3.14 * atan2f(quat_data.q0 * quat_data.q3 + quat_data.q1 * quat_data.q2, 0.5f - quat_data.q2 * quat_data.q2 - quat_data.q3 * quat_data.q3); // // IMU.dataReady = 0; // MPU6000_readAll(); } } 8003224: 46c0 nop @ (mov r8, r8) 8003226: 46bd mov sp, r7 8003228: b002 add sp, #8 800322a: bd80 pop {r7, pc} 800322c: 2000008c .word 0x2000008c 8003230: 00000854 .word 0x00000854 8003234: 0000085c .word 0x0000085c 08003238 : void IMU_Check_State(){ 8003238: b5f0 push {r4, r5, r6, r7, lr} 800323a: b085 sub sp, #20 800323c: af04 add r7, sp, #16 if(IMU.dataReady){ 800323e: 4b95 ldr r3, [pc, #596] @ (8003494 ) 8003240: 4a95 ldr r2, [pc, #596] @ (8003498 ) 8003242: 5c9b ldrb r3, [r3, r2] 8003244: 2b00 cmp r3, #0 8003246: d100 bne.n 800324a 8003248: e120 b.n 800348c MPU6000_Raw_Data_Convert(); 800324a: f7ff fe15 bl 8002e78 madgwick_update_6dof(madgwick_handle, IMU.g_x * DEG2RAD, IMU.g_y * DEG2RAD, IMU.g_z * DEG2RAD, IMU.a_x, IMU.a_y, IMU.a_z); 800324e: 4b93 ldr r3, [pc, #588] @ (800349c ) 8003250: 681c ldr r4, [r3, #0] 8003252: 4b90 ldr r3, [pc, #576] @ (8003494 ) 8003254: 681b ldr r3, [r3, #0] 8003256: 4992 ldr r1, [pc, #584] @ (80034a0 ) 8003258: 1c18 adds r0, r3, #0 800325a: f7fd fbc7 bl 80009ec <__aeabi_fmul> 800325e: 1c03 adds r3, r0, #0 8003260: 4990 ldr r1, [pc, #576] @ (80034a4 ) 8003262: 1c18 adds r0, r3, #0 8003264: f7fd f9dc bl 8000620 <__aeabi_fdiv> 8003268: 1c03 adds r3, r0, #0 800326a: 1c1d adds r5, r3, #0 800326c: 4b89 ldr r3, [pc, #548] @ (8003494 ) 800326e: 685b ldr r3, [r3, #4] 8003270: 498b ldr r1, [pc, #556] @ (80034a0 ) 8003272: 1c18 adds r0, r3, #0 8003274: f7fd fbba bl 80009ec <__aeabi_fmul> 8003278: 1c03 adds r3, r0, #0 800327a: 498a ldr r1, [pc, #552] @ (80034a4 ) 800327c: 1c18 adds r0, r3, #0 800327e: f7fd f9cf bl 8000620 <__aeabi_fdiv> 8003282: 1c03 adds r3, r0, #0 8003284: 1c1e adds r6, r3, #0 8003286: 4b83 ldr r3, [pc, #524] @ (8003494 ) 8003288: 689b ldr r3, [r3, #8] 800328a: 4985 ldr r1, [pc, #532] @ (80034a0 ) 800328c: 1c18 adds r0, r3, #0 800328e: f7fd fbad bl 80009ec <__aeabi_fmul> 8003292: 1c03 adds r3, r0, #0 8003294: 4983 ldr r1, [pc, #524] @ (80034a4 ) 8003296: 1c18 adds r0, r3, #0 8003298: f7fd f9c2 bl 8000620 <__aeabi_fdiv> 800329c: 1c03 adds r3, r0, #0 800329e: 1c18 adds r0, r3, #0 80032a0: 4b7c ldr r3, [pc, #496] @ (8003494 ) 80032a2: 68da ldr r2, [r3, #12] 80032a4: 4b7b ldr r3, [pc, #492] @ (8003494 ) 80032a6: 6919 ldr r1, [r3, #16] 80032a8: 4b7a ldr r3, [pc, #488] @ (8003494 ) 80032aa: 695b ldr r3, [r3, #20] 80032ac: 9302 str r3, [sp, #8] 80032ae: 9101 str r1, [sp, #4] 80032b0: 9200 str r2, [sp, #0] 80032b2: 1c03 adds r3, r0, #0 80032b4: 1c32 adds r2, r6, #0 80032b6: 1c29 adds r1, r5, #0 80032b8: 0020 movs r0, r4 80032ba: f000 f98d bl 80035d8 madgwick_get_quaternion(madgwick_handle, &quat_data); 80032be: 4b77 ldr r3, [pc, #476] @ (800349c ) 80032c0: 681b ldr r3, [r3, #0] 80032c2: 4a79 ldr r2, [pc, #484] @ (80034a8 ) 80032c4: 0011 movs r1, r2 80032c6: 0018 movs r0, r3 80032c8: f000 f961 bl 800358e IMU.roll = 180.0 / 3.14 * atan2(2 * (quat_data.q0 * quat_data.q1 + quat_data.q2 * quat_data.q3), 1 - 2 * (quat_data.q1 * quat_data.q1 + quat_data.q2 * quat_data.q2)); 80032cc: 4b76 ldr r3, [pc, #472] @ (80034a8 ) 80032ce: 681a ldr r2, [r3, #0] 80032d0: 4b75 ldr r3, [pc, #468] @ (80034a8 ) 80032d2: 685b ldr r3, [r3, #4] 80032d4: 1c19 adds r1, r3, #0 80032d6: 1c10 adds r0, r2, #0 80032d8: f7fd fb88 bl 80009ec <__aeabi_fmul> 80032dc: 1c03 adds r3, r0, #0 80032de: 1c1c adds r4, r3, #0 80032e0: 4b71 ldr r3, [pc, #452] @ (80034a8 ) 80032e2: 689a ldr r2, [r3, #8] 80032e4: 4b70 ldr r3, [pc, #448] @ (80034a8 ) 80032e6: 68db ldr r3, [r3, #12] 80032e8: 1c19 adds r1, r3, #0 80032ea: 1c10 adds r0, r2, #0 80032ec: f7fd fb7e bl 80009ec <__aeabi_fmul> 80032f0: 1c03 adds r3, r0, #0 80032f2: 1c19 adds r1, r3, #0 80032f4: 1c20 adds r0, r4, #0 80032f6: f7fd f809 bl 800030c <__aeabi_fadd> 80032fa: 1c03 adds r3, r0, #0 80032fc: 1c19 adds r1, r3, #0 80032fe: 1c18 adds r0, r3, #0 8003300: f7fd f804 bl 800030c <__aeabi_fadd> 8003304: 1c03 adds r3, r0, #0 8003306: 1c18 adds r0, r3, #0 8003308: f7ff fccc bl 8002ca4 <__aeabi_f2d> 800330c: 0004 movs r4, r0 800330e: 000d movs r5, r1 8003310: 4b65 ldr r3, [pc, #404] @ (80034a8 ) 8003312: 685a ldr r2, [r3, #4] 8003314: 4b64 ldr r3, [pc, #400] @ (80034a8 ) 8003316: 685b ldr r3, [r3, #4] 8003318: 1c19 adds r1, r3, #0 800331a: 1c10 adds r0, r2, #0 800331c: f7fd fb66 bl 80009ec <__aeabi_fmul> 8003320: 1c03 adds r3, r0, #0 8003322: 1c1e adds r6, r3, #0 8003324: 4b60 ldr r3, [pc, #384] @ (80034a8 ) 8003326: 689a ldr r2, [r3, #8] 8003328: 4b5f ldr r3, [pc, #380] @ (80034a8 ) 800332a: 689b ldr r3, [r3, #8] 800332c: 1c19 adds r1, r3, #0 800332e: 1c10 adds r0, r2, #0 8003330: f7fd fb5c bl 80009ec <__aeabi_fmul> 8003334: 1c03 adds r3, r0, #0 8003336: 1c19 adds r1, r3, #0 8003338: 1c30 adds r0, r6, #0 800333a: f7fc ffe7 bl 800030c <__aeabi_fadd> 800333e: 1c03 adds r3, r0, #0 8003340: 1c19 adds r1, r3, #0 8003342: 1c18 adds r0, r3, #0 8003344: f7fc ffe2 bl 800030c <__aeabi_fadd> 8003348: 1c03 adds r3, r0, #0 800334a: 1c19 adds r1, r3, #0 800334c: 20fe movs r0, #254 @ 0xfe 800334e: 0580 lsls r0, r0, #22 8003350: f7fd fc8a bl 8000c68 <__aeabi_fsub> 8003354: 1c03 adds r3, r0, #0 8003356: 1c18 adds r0, r3, #0 8003358: f7ff fca4 bl 8002ca4 <__aeabi_f2d> 800335c: 0002 movs r2, r0 800335e: 000b movs r3, r1 8003360: 0020 movs r0, r4 8003362: 0029 movs r1, r5 8003364: f005 fea6 bl 80090b4 8003368: 4a50 ldr r2, [pc, #320] @ (80034ac ) 800336a: 4b51 ldr r3, [pc, #324] @ (80034b0 ) 800336c: f7fe fe14 bl 8001f98 <__aeabi_dmul> 8003370: 0002 movs r2, r0 8003372: 000b movs r3, r1 8003374: 0010 movs r0, r2 8003376: 0019 movs r1, r3 8003378: f7ff fcdc bl 8002d34 <__aeabi_d2f> 800337c: 1c02 adds r2, r0, #0 800337e: 4b45 ldr r3, [pc, #276] @ (8003494 ) 8003380: 629a str r2, [r3, #40] @ 0x28 IMU.pitch = 180.0 / 3.14 * asin(2 * (quat_data.q0 * quat_data.q2 - quat_data.q3 * quat_data.q1)); 8003382: 4b49 ldr r3, [pc, #292] @ (80034a8 ) 8003384: 681a ldr r2, [r3, #0] 8003386: 4b48 ldr r3, [pc, #288] @ (80034a8 ) 8003388: 689b ldr r3, [r3, #8] 800338a: 1c19 adds r1, r3, #0 800338c: 1c10 adds r0, r2, #0 800338e: f7fd fb2d bl 80009ec <__aeabi_fmul> 8003392: 1c03 adds r3, r0, #0 8003394: 1c1c adds r4, r3, #0 8003396: 4b44 ldr r3, [pc, #272] @ (80034a8 ) 8003398: 68da ldr r2, [r3, #12] 800339a: 4b43 ldr r3, [pc, #268] @ (80034a8 ) 800339c: 685b ldr r3, [r3, #4] 800339e: 1c19 adds r1, r3, #0 80033a0: 1c10 adds r0, r2, #0 80033a2: f7fd fb23 bl 80009ec <__aeabi_fmul> 80033a6: 1c03 adds r3, r0, #0 80033a8: 1c19 adds r1, r3, #0 80033aa: 1c20 adds r0, r4, #0 80033ac: f7fd fc5c bl 8000c68 <__aeabi_fsub> 80033b0: 1c03 adds r3, r0, #0 80033b2: 1c19 adds r1, r3, #0 80033b4: 1c18 adds r0, r3, #0 80033b6: f7fc ffa9 bl 800030c <__aeabi_fadd> 80033ba: 1c03 adds r3, r0, #0 80033bc: 1c18 adds r0, r3, #0 80033be: f7ff fc71 bl 8002ca4 <__aeabi_f2d> 80033c2: 0002 movs r2, r0 80033c4: 000b movs r3, r1 80033c6: 0010 movs r0, r2 80033c8: 0019 movs r1, r3 80033ca: f005 fe49 bl 8009060 80033ce: 4a37 ldr r2, [pc, #220] @ (80034ac ) 80033d0: 4b37 ldr r3, [pc, #220] @ (80034b0 ) 80033d2: f7fe fde1 bl 8001f98 <__aeabi_dmul> 80033d6: 0002 movs r2, r0 80033d8: 000b movs r3, r1 80033da: 0010 movs r0, r2 80033dc: 0019 movs r1, r3 80033de: f7ff fca9 bl 8002d34 <__aeabi_d2f> 80033e2: 1c02 adds r2, r0, #0 80033e4: 4b2b ldr r3, [pc, #172] @ (8003494 ) 80033e6: 625a str r2, [r3, #36] @ 0x24 IMU.yaw = 180.0 / 3.14 * atan2f(quat_data.q0 * quat_data.q3 + quat_data.q1 * quat_data.q2, 0.5f - quat_data.q2 * quat_data.q2 - quat_data.q3 * quat_data.q3); 80033e8: 4b2f ldr r3, [pc, #188] @ (80034a8 ) 80033ea: 681a ldr r2, [r3, #0] 80033ec: 4b2e ldr r3, [pc, #184] @ (80034a8 ) 80033ee: 68db ldr r3, [r3, #12] 80033f0: 1c19 adds r1, r3, #0 80033f2: 1c10 adds r0, r2, #0 80033f4: f7fd fafa bl 80009ec <__aeabi_fmul> 80033f8: 1c03 adds r3, r0, #0 80033fa: 1c1c adds r4, r3, #0 80033fc: 4b2a ldr r3, [pc, #168] @ (80034a8 ) 80033fe: 685a ldr r2, [r3, #4] 8003400: 4b29 ldr r3, [pc, #164] @ (80034a8 ) 8003402: 689b ldr r3, [r3, #8] 8003404: 1c19 adds r1, r3, #0 8003406: 1c10 adds r0, r2, #0 8003408: f7fd faf0 bl 80009ec <__aeabi_fmul> 800340c: 1c03 adds r3, r0, #0 800340e: 1c19 adds r1, r3, #0 8003410: 1c20 adds r0, r4, #0 8003412: f7fc ff7b bl 800030c <__aeabi_fadd> 8003416: 1c03 adds r3, r0, #0 8003418: 1c1c adds r4, r3, #0 800341a: 4b23 ldr r3, [pc, #140] @ (80034a8 ) 800341c: 689a ldr r2, [r3, #8] 800341e: 4b22 ldr r3, [pc, #136] @ (80034a8 ) 8003420: 689b ldr r3, [r3, #8] 8003422: 1c19 adds r1, r3, #0 8003424: 1c10 adds r0, r2, #0 8003426: f7fd fae1 bl 80009ec <__aeabi_fmul> 800342a: 1c03 adds r3, r0, #0 800342c: 1c19 adds r1, r3, #0 800342e: 20fc movs r0, #252 @ 0xfc 8003430: 0580 lsls r0, r0, #22 8003432: f7fd fc19 bl 8000c68 <__aeabi_fsub> 8003436: 1c03 adds r3, r0, #0 8003438: 1c1d adds r5, r3, #0 800343a: 4b1b ldr r3, [pc, #108] @ (80034a8 ) 800343c: 68da ldr r2, [r3, #12] 800343e: 4b1a ldr r3, [pc, #104] @ (80034a8 ) 8003440: 68db ldr r3, [r3, #12] 8003442: 1c19 adds r1, r3, #0 8003444: 1c10 adds r0, r2, #0 8003446: f7fd fad1 bl 80009ec <__aeabi_fmul> 800344a: 1c03 adds r3, r0, #0 800344c: 1c19 adds r1, r3, #0 800344e: 1c28 adds r0, r5, #0 8003450: f7fd fc0a bl 8000c68 <__aeabi_fsub> 8003454: 1c03 adds r3, r0, #0 8003456: 1c19 adds r1, r3, #0 8003458: 1c20 adds r0, r4, #0 800345a: f005 fe33 bl 80090c4 800345e: 1c03 adds r3, r0, #0 8003460: 1c18 adds r0, r3, #0 8003462: f7ff fc1f bl 8002ca4 <__aeabi_f2d> 8003466: 4a11 ldr r2, [pc, #68] @ (80034ac ) 8003468: 4b11 ldr r3, [pc, #68] @ (80034b0 ) 800346a: f7fe fd95 bl 8001f98 <__aeabi_dmul> 800346e: 0002 movs r2, r0 8003470: 000b movs r3, r1 8003472: 0010 movs r0, r2 8003474: 0019 movs r1, r3 8003476: f7ff fc5d bl 8002d34 <__aeabi_d2f> 800347a: 1c02 adds r2, r0, #0 800347c: 4b05 ldr r3, [pc, #20] @ (8003494 ) 800347e: 62da str r2, [r3, #44] @ 0x2c IMU.dataReady = 0; 8003480: 4b04 ldr r3, [pc, #16] @ (8003494 ) 8003482: 4a05 ldr r2, [pc, #20] @ (8003498 ) 8003484: 2100 movs r1, #0 8003486: 5499 strb r1, [r3, r2] MPU6000_readAll(); 8003488: f7ff fdd8 bl 800303c } } 800348c: 46c0 nop @ (mov r8, r8) 800348e: 46bd mov sp, r7 8003490: b001 add sp, #4 8003492: bdf0 pop {r4, r5, r6, r7, pc} 8003494: 2000008c .word 0x2000008c 8003498: 0000085c .word 0x0000085c 800349c: 200008ec .word 0x200008ec 80034a0: 4048f5c3 .word 0x4048f5c3 80034a4: 43340000 .word 0x43340000 80034a8: 200008f0 .word 0x200008f0 80034ac: 61d59ae7 .word 0x61d59ae7 80034b0: 404ca994 .word 0x404ca994 080034b4 : float q3; uint8_t lock; } madgwick_t; static float invSqrt(float x) { 80034b4: b580 push {r7, lr} 80034b6: b086 sub sp, #24 80034b8: af00 add r7, sp, #0 80034ba: 6078 str r0, [r7, #4] float halfx = 0.5f * x; 80034bc: 21fc movs r1, #252 @ 0xfc 80034be: 0589 lsls r1, r1, #22 80034c0: 6878 ldr r0, [r7, #4] 80034c2: f7fd fa93 bl 80009ec <__aeabi_fmul> 80034c6: 1c03 adds r3, r0, #0 80034c8: 617b str r3, [r7, #20] float y = x; 80034ca: 687b ldr r3, [r7, #4] 80034cc: 613b str r3, [r7, #16] long i = *(long*)&y; 80034ce: 2310 movs r3, #16 80034d0: 18fb adds r3, r7, r3 80034d2: 681b ldr r3, [r3, #0] 80034d4: 60fb str r3, [r7, #12] i = 0x5f3759df - (i >> 1); 80034d6: 68fb ldr r3, [r7, #12] 80034d8: 105b asrs r3, r3, #1 80034da: 4a13 ldr r2, [pc, #76] @ (8003528 ) 80034dc: 1ad3 subs r3, r2, r3 80034de: 60fb str r3, [r7, #12] y = *(float*)&i; 80034e0: 230c movs r3, #12 80034e2: 18fb adds r3, r7, r3 80034e4: 681b ldr r3, [r3, #0] 80034e6: 613b str r3, [r7, #16] y = y * (1.5f - (halfx * y * y)); 80034e8: 693b ldr r3, [r7, #16] 80034ea: 6979 ldr r1, [r7, #20] 80034ec: 1c18 adds r0, r3, #0 80034ee: f7fd fa7d bl 80009ec <__aeabi_fmul> 80034f2: 1c03 adds r3, r0, #0 80034f4: 1c1a adds r2, r3, #0 80034f6: 693b ldr r3, [r7, #16] 80034f8: 1c19 adds r1, r3, #0 80034fa: 1c10 adds r0, r2, #0 80034fc: f7fd fa76 bl 80009ec <__aeabi_fmul> 8003500: 1c03 adds r3, r0, #0 8003502: 1c19 adds r1, r3, #0 8003504: 20ff movs r0, #255 @ 0xff 8003506: 0580 lsls r0, r0, #22 8003508: f7fd fbae bl 8000c68 <__aeabi_fsub> 800350c: 1c03 adds r3, r0, #0 800350e: 1c1a adds r2, r3, #0 8003510: 693b ldr r3, [r7, #16] 8003512: 1c19 adds r1, r3, #0 8003514: 1c10 adds r0, r2, #0 8003516: f7fd fa69 bl 80009ec <__aeabi_fmul> 800351a: 1c03 adds r3, r0, #0 800351c: 613b str r3, [r7, #16] return y; 800351e: 693b ldr r3, [r7, #16] } 8003520: 1c18 adds r0, r3, #0 8003522: 46bd mov sp, r7 8003524: b006 add sp, #24 8003526: bd80 pop {r7, pc} 8003528: 5f3759df .word 0x5f3759df 0800352c : madgwick_handle_t madgwick_init(madgwick_cfg_t *config) { 800352c: b580 push {r7, lr} 800352e: b084 sub sp, #16 8003530: af00 add r7, sp, #0 8003532: 6078 str r0, [r7, #4] /* Check input conditions */ MADGWICK_CHECK(config, MADGWICK_INIT_ERR_STR, NULL); 8003534: 687b ldr r3, [r7, #4] 8003536: 2b00 cmp r3, #0 8003538: d101 bne.n 800353e 800353a: 2300 movs r3, #0 800353c: e023 b.n 8003586 /* Allocate memory for handle structure */ madgwick_handle_t handle = calloc(1, sizeof(madgwick_t)); 800353e: 211c movs r1, #28 8003540: 2001 movs r0, #1 8003542: f005 fc5d bl 8008e00 8003546: 0003 movs r3, r0 8003548: 60fb str r3, [r7, #12] MADGWICK_CHECK(handle, MADGWICK_INIT_ERR_STR, NULL); 800354a: 68fb ldr r3, [r7, #12] 800354c: 2b00 cmp r3, #0 800354e: d101 bne.n 8003554 8003550: 2300 movs r3, #0 8003552: e018 b.n 8003586 /* Update handle structure */ handle->beta = config->beta; 8003554: 687b ldr r3, [r7, #4] 8003556: 681a ldr r2, [r3, #0] 8003558: 68fb ldr r3, [r7, #12] 800355a: 601a str r2, [r3, #0] handle->sample_freq = config->sample_freq; 800355c: 687b ldr r3, [r7, #4] 800355e: 685a ldr r2, [r3, #4] 8003560: 68fb ldr r3, [r7, #12] 8003562: 605a str r2, [r3, #4] handle->q0 = 1.0f; 8003564: 68fb ldr r3, [r7, #12] 8003566: 22fe movs r2, #254 @ 0xfe 8003568: 0592 lsls r2, r2, #22 800356a: 609a str r2, [r3, #8] handle->q1 = 0.0f; 800356c: 68fb ldr r3, [r7, #12] 800356e: 2200 movs r2, #0 8003570: 60da str r2, [r3, #12] handle->q2 = 0.0f; 8003572: 68fb ldr r3, [r7, #12] 8003574: 2200 movs r2, #0 8003576: 611a str r2, [r3, #16] handle->q3 = 0.0f; 8003578: 68fb ldr r3, [r7, #12] 800357a: 2200 movs r2, #0 800357c: 615a str r2, [r3, #20] handle->lock = 0; 800357e: 68fb ldr r3, [r7, #12] 8003580: 2200 movs r2, #0 8003582: 761a strb r2, [r3, #24] return handle; 8003584: 68fb ldr r3, [r7, #12] } 8003586: 0018 movs r0, r3 8003588: 46bd mov sp, r7 800358a: b004 add sp, #16 800358c: bd80 pop {r7, pc} 0800358e : return 0; } uint8_t madgwick_get_quaternion(madgwick_handle_t handle, madgwick_quat_data_t *quat_data) { 800358e: b580 push {r7, lr} 8003590: b082 sub sp, #8 8003592: af00 add r7, sp, #0 8003594: 6078 str r0, [r7, #4] 8003596: 6039 str r1, [r7, #0] /* Check input conditions */ MADGWICK_CHECK(handle, MADGWICK_GET_QUAT_ERR_STR, STM_ERR_INVALID_ARG); 8003598: 687b ldr r3, [r7, #4] 800359a: 2b00 cmp r3, #0 800359c: d101 bne.n 80035a2 800359e: 2301 movs r3, #1 80035a0: e016 b.n 80035d0 handle->lock = 1; 80035a2: 687b ldr r3, [r7, #4] 80035a4: 2201 movs r2, #1 80035a6: 761a strb r2, [r3, #24] quat_data->q0 = handle->q0; 80035a8: 687b ldr r3, [r7, #4] 80035aa: 689a ldr r2, [r3, #8] 80035ac: 683b ldr r3, [r7, #0] 80035ae: 601a str r2, [r3, #0] quat_data->q1 = handle->q1; 80035b0: 687b ldr r3, [r7, #4] 80035b2: 68da ldr r2, [r3, #12] 80035b4: 683b ldr r3, [r7, #0] 80035b6: 605a str r2, [r3, #4] quat_data->q2 = handle->q2; 80035b8: 687b ldr r3, [r7, #4] 80035ba: 691a ldr r2, [r3, #16] 80035bc: 683b ldr r3, [r7, #0] 80035be: 609a str r2, [r3, #8] quat_data->q3 = handle->q3; 80035c0: 687b ldr r3, [r7, #4] 80035c2: 695a ldr r2, [r3, #20] 80035c4: 683b ldr r3, [r7, #0] 80035c6: 60da str r2, [r3, #12] handle->lock = 0; 80035c8: 687b ldr r3, [r7, #4] 80035ca: 2200 movs r2, #0 80035cc: 761a strb r2, [r3, #24] return 0; 80035ce: 2300 movs r3, #0 } 80035d0: 0018 movs r0, r3 80035d2: 46bd mov sp, r7 80035d4: b002 add sp, #8 80035d6: bd80 pop {r7, pc} 080035d8 : uint8_t madgwick_update_6dof(madgwick_handle_t handle, float gx, float gy, float gz, float ax, float ay, float az) { 80035d8: b5f0 push {r4, r5, r6, r7, lr} 80035da: b0a1 sub sp, #132 @ 0x84 80035dc: af00 add r7, sp, #0 80035de: 60f8 str r0, [r7, #12] 80035e0: 60b9 str r1, [r7, #8] 80035e2: 607a str r2, [r7, #4] 80035e4: 603b str r3, [r7, #0] /* Check input conditions */ MADGWICK_CHECK(handle, MADGWICK_UPDATE_6DOF_ERR_STR, STM_ERR_INVALID_ARG); 80035e6: 68fb ldr r3, [r7, #12] 80035e8: 2b00 cmp r3, #0 80035ea: d101 bne.n 80035f0 80035ec: 2301 movs r3, #1 80035ee: e38e b.n 8003d0e handle->lock = 1; 80035f0: 68fb ldr r3, [r7, #12] 80035f2: 2201 movs r2, #1 80035f4: 761a strb r2, [r3, #24] float q0 = handle->q0; 80035f6: 68fb ldr r3, [r7, #12] 80035f8: 689b ldr r3, [r3, #8] 80035fa: 66fb str r3, [r7, #108] @ 0x6c float q1 = handle->q1; 80035fc: 68fb ldr r3, [r7, #12] 80035fe: 68db ldr r3, [r3, #12] 8003600: 66bb str r3, [r7, #104] @ 0x68 float q2 = handle->q2; 8003602: 68fb ldr r3, [r7, #12] 8003604: 691b ldr r3, [r3, #16] 8003606: 667b str r3, [r7, #100] @ 0x64 float q3 = handle->q3; 8003608: 68fb ldr r3, [r7, #12] 800360a: 695b ldr r3, [r3, #20] 800360c: 663b str r3, [r7, #96] @ 0x60 float beta = handle->beta; 800360e: 68fb ldr r3, [r7, #12] 8003610: 681b ldr r3, [r3, #0] 8003612: 65fb str r3, [r7, #92] @ 0x5c float sampleFreq = handle->sample_freq; 8003614: 68fb ldr r3, [r7, #12] 8003616: 685b ldr r3, [r3, #4] 8003618: 65bb str r3, [r7, #88] @ 0x58 float s0, s1, s2, s3; float qDot1, qDot2, qDot3, qDot4; float _2q0, _2q1, _2q2, _2q3, _4q0, _4q1, _4q2 , _8q1, _8q2, q0q0, q1q1, q2q2, q3q3; // Rate of change of quaternion from gyroscope qDot1 = 0.5f * (-q1 * gx - q2 * gy - q3 * gz); 800361a: 6ebb ldr r3, [r7, #104] @ 0x68 800361c: 2280 movs r2, #128 @ 0x80 800361e: 0612 lsls r2, r2, #24 8003620: 4053 eors r3, r2 8003622: 68b9 ldr r1, [r7, #8] 8003624: 1c18 adds r0, r3, #0 8003626: f7fd f9e1 bl 80009ec <__aeabi_fmul> 800362a: 1c03 adds r3, r0, #0 800362c: 1c1c adds r4, r3, #0 800362e: 6879 ldr r1, [r7, #4] 8003630: 6e78 ldr r0, [r7, #100] @ 0x64 8003632: f7fd f9db bl 80009ec <__aeabi_fmul> 8003636: 1c03 adds r3, r0, #0 8003638: 1c19 adds r1, r3, #0 800363a: 1c20 adds r0, r4, #0 800363c: f7fd fb14 bl 8000c68 <__aeabi_fsub> 8003640: 1c03 adds r3, r0, #0 8003642: 1c1c adds r4, r3, #0 8003644: 6839 ldr r1, [r7, #0] 8003646: 6e38 ldr r0, [r7, #96] @ 0x60 8003648: f7fd f9d0 bl 80009ec <__aeabi_fmul> 800364c: 1c03 adds r3, r0, #0 800364e: 1c19 adds r1, r3, #0 8003650: 1c20 adds r0, r4, #0 8003652: f7fd fb09 bl 8000c68 <__aeabi_fsub> 8003656: 1c03 adds r3, r0, #0 8003658: 21fc movs r1, #252 @ 0xfc 800365a: 0589 lsls r1, r1, #22 800365c: 1c18 adds r0, r3, #0 800365e: f7fd f9c5 bl 80009ec <__aeabi_fmul> 8003662: 1c03 adds r3, r0, #0 8003664: 67fb str r3, [r7, #124] @ 0x7c qDot2 = 0.5f * (q0 * gx + q2 * gz - q3 * gy); 8003666: 68b9 ldr r1, [r7, #8] 8003668: 6ef8 ldr r0, [r7, #108] @ 0x6c 800366a: f7fd f9bf bl 80009ec <__aeabi_fmul> 800366e: 1c03 adds r3, r0, #0 8003670: 1c1c adds r4, r3, #0 8003672: 6839 ldr r1, [r7, #0] 8003674: 6e78 ldr r0, [r7, #100] @ 0x64 8003676: f7fd f9b9 bl 80009ec <__aeabi_fmul> 800367a: 1c03 adds r3, r0, #0 800367c: 1c19 adds r1, r3, #0 800367e: 1c20 adds r0, r4, #0 8003680: f7fc fe44 bl 800030c <__aeabi_fadd> 8003684: 1c03 adds r3, r0, #0 8003686: 1c1c adds r4, r3, #0 8003688: 6879 ldr r1, [r7, #4] 800368a: 6e38 ldr r0, [r7, #96] @ 0x60 800368c: f7fd f9ae bl 80009ec <__aeabi_fmul> 8003690: 1c03 adds r3, r0, #0 8003692: 1c19 adds r1, r3, #0 8003694: 1c20 adds r0, r4, #0 8003696: f7fd fae7 bl 8000c68 <__aeabi_fsub> 800369a: 1c03 adds r3, r0, #0 800369c: 21fc movs r1, #252 @ 0xfc 800369e: 0589 lsls r1, r1, #22 80036a0: 1c18 adds r0, r3, #0 80036a2: f7fd f9a3 bl 80009ec <__aeabi_fmul> 80036a6: 1c03 adds r3, r0, #0 80036a8: 67bb str r3, [r7, #120] @ 0x78 qDot3 = 0.5f * (q0 * gy - q1 * gz + q3 * gx); 80036aa: 6879 ldr r1, [r7, #4] 80036ac: 6ef8 ldr r0, [r7, #108] @ 0x6c 80036ae: f7fd f99d bl 80009ec <__aeabi_fmul> 80036b2: 1c03 adds r3, r0, #0 80036b4: 1c1c adds r4, r3, #0 80036b6: 6839 ldr r1, [r7, #0] 80036b8: 6eb8 ldr r0, [r7, #104] @ 0x68 80036ba: f7fd f997 bl 80009ec <__aeabi_fmul> 80036be: 1c03 adds r3, r0, #0 80036c0: 1c19 adds r1, r3, #0 80036c2: 1c20 adds r0, r4, #0 80036c4: f7fd fad0 bl 8000c68 <__aeabi_fsub> 80036c8: 1c03 adds r3, r0, #0 80036ca: 1c1c adds r4, r3, #0 80036cc: 68b9 ldr r1, [r7, #8] 80036ce: 6e38 ldr r0, [r7, #96] @ 0x60 80036d0: f7fd f98c bl 80009ec <__aeabi_fmul> 80036d4: 1c03 adds r3, r0, #0 80036d6: 1c19 adds r1, r3, #0 80036d8: 1c20 adds r0, r4, #0 80036da: f7fc fe17 bl 800030c <__aeabi_fadd> 80036de: 1c03 adds r3, r0, #0 80036e0: 21fc movs r1, #252 @ 0xfc 80036e2: 0589 lsls r1, r1, #22 80036e4: 1c18 adds r0, r3, #0 80036e6: f7fd f981 bl 80009ec <__aeabi_fmul> 80036ea: 1c03 adds r3, r0, #0 80036ec: 677b str r3, [r7, #116] @ 0x74 qDot4 = 0.5f * (q0 * gz + q1 * gy - q2 * gx); 80036ee: 6839 ldr r1, [r7, #0] 80036f0: 6ef8 ldr r0, [r7, #108] @ 0x6c 80036f2: f7fd f97b bl 80009ec <__aeabi_fmul> 80036f6: 1c03 adds r3, r0, #0 80036f8: 1c1c adds r4, r3, #0 80036fa: 6879 ldr r1, [r7, #4] 80036fc: 6eb8 ldr r0, [r7, #104] @ 0x68 80036fe: f7fd f975 bl 80009ec <__aeabi_fmul> 8003702: 1c03 adds r3, r0, #0 8003704: 1c19 adds r1, r3, #0 8003706: 1c20 adds r0, r4, #0 8003708: f7fc fe00 bl 800030c <__aeabi_fadd> 800370c: 1c03 adds r3, r0, #0 800370e: 1c1c adds r4, r3, #0 8003710: 68b9 ldr r1, [r7, #8] 8003712: 6e78 ldr r0, [r7, #100] @ 0x64 8003714: f7fd f96a bl 80009ec <__aeabi_fmul> 8003718: 1c03 adds r3, r0, #0 800371a: 1c19 adds r1, r3, #0 800371c: 1c20 adds r0, r4, #0 800371e: f7fd faa3 bl 8000c68 <__aeabi_fsub> 8003722: 1c03 adds r3, r0, #0 8003724: 21fc movs r1, #252 @ 0xfc 8003726: 0589 lsls r1, r1, #22 8003728: 1c18 adds r0, r3, #0 800372a: f7fd f95f bl 80009ec <__aeabi_fmul> 800372e: 1c03 adds r3, r0, #0 8003730: 673b str r3, [r7, #112] @ 0x70 // Compute feedback only if accelerometer measurement valid (avoids NaN in accelerometer normalisation) if (!((ax == 0.0f) && (ay == 0.0f) && (az == 0.0f))) { 8003732: 2100 movs r1, #0 8003734: 2390 movs r3, #144 @ 0x90 8003736: 2408 movs r4, #8 8003738: 191b adds r3, r3, r4 800373a: 19db adds r3, r3, r7 800373c: 6818 ldr r0, [r3, #0] 800373e: f7fc fdb7 bl 80002b0 <__aeabi_fcmpeq> 8003742: 1e03 subs r3, r0, #0 8003744: d012 beq.n 800376c 8003746: 2100 movs r1, #0 8003748: 2394 movs r3, #148 @ 0x94 800374a: 191b adds r3, r3, r4 800374c: 19db adds r3, r3, r7 800374e: 6818 ldr r0, [r3, #0] 8003750: f7fc fdae bl 80002b0 <__aeabi_fcmpeq> 8003754: 1e03 subs r3, r0, #0 8003756: d009 beq.n 800376c 8003758: 2100 movs r1, #0 800375a: 2398 movs r3, #152 @ 0x98 800375c: 191b adds r3, r3, r4 800375e: 19db adds r3, r3, r7 8003760: 6818 ldr r0, [r3, #0] 8003762: f7fc fda5 bl 80002b0 <__aeabi_fcmpeq> 8003766: 1e03 subs r3, r0, #0 8003768: d000 beq.n 800376c 800376a: e239 b.n 8003be0 // Normalise accelerometer measurement recipNorm = invSqrt(ax * ax + ay * ay + az * az); 800376c: 2590 movs r5, #144 @ 0x90 800376e: 2008 movs r0, #8 8003770: 182b adds r3, r5, r0 8003772: 19db adds r3, r3, r7 8003774: 6819 ldr r1, [r3, #0] 8003776: 182b adds r3, r5, r0 8003778: 19db adds r3, r3, r7 800377a: 6818 ldr r0, [r3, #0] 800377c: f7fd f936 bl 80009ec <__aeabi_fmul> 8003780: 1c03 adds r3, r0, #0 8003782: 1c1c adds r4, r3, #0 8003784: 2694 movs r6, #148 @ 0x94 8003786: 2008 movs r0, #8 8003788: 1833 adds r3, r6, r0 800378a: 19db adds r3, r3, r7 800378c: 6819 ldr r1, [r3, #0] 800378e: 1833 adds r3, r6, r0 8003790: 19db adds r3, r3, r7 8003792: 6818 ldr r0, [r3, #0] 8003794: f7fd f92a bl 80009ec <__aeabi_fmul> 8003798: 1c03 adds r3, r0, #0 800379a: 1c19 adds r1, r3, #0 800379c: 1c20 adds r0, r4, #0 800379e: f7fc fdb5 bl 800030c <__aeabi_fadd> 80037a2: 1c03 adds r3, r0, #0 80037a4: 1c1c adds r4, r3, #0 80037a6: 2398 movs r3, #152 @ 0x98 80037a8: 2008 movs r0, #8 80037aa: 181a adds r2, r3, r0 80037ac: 19d2 adds r2, r2, r7 80037ae: 6811 ldr r1, [r2, #0] 80037b0: 181b adds r3, r3, r0 80037b2: 19da adds r2, r3, r7 80037b4: 6810 ldr r0, [r2, #0] 80037b6: f7fd f919 bl 80009ec <__aeabi_fmul> 80037ba: 1c03 adds r3, r0, #0 80037bc: 1c19 adds r1, r3, #0 80037be: 1c20 adds r0, r4, #0 80037c0: f7fc fda4 bl 800030c <__aeabi_fadd> 80037c4: 1c03 adds r3, r0, #0 80037c6: 1c18 adds r0, r3, #0 80037c8: f7ff fe74 bl 80034b4 80037cc: 1c03 adds r3, r0, #0 80037ce: 657b str r3, [r7, #84] @ 0x54 ax *= recipNorm; 80037d0: 6d79 ldr r1, [r7, #84] @ 0x54 80037d2: 2408 movs r4, #8 80037d4: 192b adds r3, r5, r4 80037d6: 19da adds r2, r3, r7 80037d8: 6810 ldr r0, [r2, #0] 80037da: f7fd f907 bl 80009ec <__aeabi_fmul> 80037de: 1c03 adds r3, r0, #0 80037e0: 192a adds r2, r5, r4 80037e2: 19d2 adds r2, r2, r7 80037e4: 6013 str r3, [r2, #0] ay *= recipNorm; 80037e6: 6d79 ldr r1, [r7, #84] @ 0x54 80037e8: 1933 adds r3, r6, r4 80037ea: 19da adds r2, r3, r7 80037ec: 6810 ldr r0, [r2, #0] 80037ee: f7fd f8fd bl 80009ec <__aeabi_fmul> 80037f2: 1c03 adds r3, r0, #0 80037f4: 0020 movs r0, r4 80037f6: 1832 adds r2, r6, r0 80037f8: 19d2 adds r2, r2, r7 80037fa: 6013 str r3, [r2, #0] az *= recipNorm; 80037fc: 6d79 ldr r1, [r7, #84] @ 0x54 80037fe: 2498 movs r4, #152 @ 0x98 8003800: 1823 adds r3, r4, r0 8003802: 19db adds r3, r3, r7 8003804: 6818 ldr r0, [r3, #0] 8003806: f7fd f8f1 bl 80009ec <__aeabi_fmul> 800380a: 1c03 adds r3, r0, #0 800380c: 2208 movs r2, #8 800380e: 18a1 adds r1, r4, r2 8003810: 19ca adds r2, r1, r7 8003812: 6013 str r3, [r2, #0] // Auxiliary variables to avoid repeated arithmetic _2q0 = 2.0f * q0; 8003814: 6efb ldr r3, [r7, #108] @ 0x6c 8003816: 1c19 adds r1, r3, #0 8003818: 1c18 adds r0, r3, #0 800381a: f7fc fd77 bl 800030c <__aeabi_fadd> 800381e: 1c03 adds r3, r0, #0 8003820: 653b str r3, [r7, #80] @ 0x50 _2q1 = 2.0f * q1; 8003822: 6ebb ldr r3, [r7, #104] @ 0x68 8003824: 1c19 adds r1, r3, #0 8003826: 1c18 adds r0, r3, #0 8003828: f7fc fd70 bl 800030c <__aeabi_fadd> 800382c: 1c03 adds r3, r0, #0 800382e: 64fb str r3, [r7, #76] @ 0x4c _2q2 = 2.0f * q2; 8003830: 6e7b ldr r3, [r7, #100] @ 0x64 8003832: 1c19 adds r1, r3, #0 8003834: 1c18 adds r0, r3, #0 8003836: f7fc fd69 bl 800030c <__aeabi_fadd> 800383a: 1c03 adds r3, r0, #0 800383c: 64bb str r3, [r7, #72] @ 0x48 _2q3 = 2.0f * q3; 800383e: 6e3b ldr r3, [r7, #96] @ 0x60 8003840: 1c19 adds r1, r3, #0 8003842: 1c18 adds r0, r3, #0 8003844: f7fc fd62 bl 800030c <__aeabi_fadd> 8003848: 1c03 adds r3, r0, #0 800384a: 647b str r3, [r7, #68] @ 0x44 _4q0 = 4.0f * q0; 800384c: 2181 movs r1, #129 @ 0x81 800384e: 05c9 lsls r1, r1, #23 8003850: 6ef8 ldr r0, [r7, #108] @ 0x6c 8003852: f7fd f8cb bl 80009ec <__aeabi_fmul> 8003856: 1c03 adds r3, r0, #0 8003858: 643b str r3, [r7, #64] @ 0x40 _4q1 = 4.0f * q1; 800385a: 2181 movs r1, #129 @ 0x81 800385c: 05c9 lsls r1, r1, #23 800385e: 6eb8 ldr r0, [r7, #104] @ 0x68 8003860: f7fd f8c4 bl 80009ec <__aeabi_fmul> 8003864: 1c03 adds r3, r0, #0 8003866: 63fb str r3, [r7, #60] @ 0x3c _4q2 = 4.0f * q2; 8003868: 2181 movs r1, #129 @ 0x81 800386a: 05c9 lsls r1, r1, #23 800386c: 6e78 ldr r0, [r7, #100] @ 0x64 800386e: f7fd f8bd bl 80009ec <__aeabi_fmul> 8003872: 1c03 adds r3, r0, #0 8003874: 63bb str r3, [r7, #56] @ 0x38 _8q1 = 8.0f * q1; 8003876: 2182 movs r1, #130 @ 0x82 8003878: 05c9 lsls r1, r1, #23 800387a: 6eb8 ldr r0, [r7, #104] @ 0x68 800387c: f7fd f8b6 bl 80009ec <__aeabi_fmul> 8003880: 1c03 adds r3, r0, #0 8003882: 637b str r3, [r7, #52] @ 0x34 _8q2 = 8.0f * q2; 8003884: 2182 movs r1, #130 @ 0x82 8003886: 05c9 lsls r1, r1, #23 8003888: 6e78 ldr r0, [r7, #100] @ 0x64 800388a: f7fd f8af bl 80009ec <__aeabi_fmul> 800388e: 1c03 adds r3, r0, #0 8003890: 633b str r3, [r7, #48] @ 0x30 q0q0 = q0 * q0; 8003892: 6ef9 ldr r1, [r7, #108] @ 0x6c 8003894: 6ef8 ldr r0, [r7, #108] @ 0x6c 8003896: f7fd f8a9 bl 80009ec <__aeabi_fmul> 800389a: 1c03 adds r3, r0, #0 800389c: 62fb str r3, [r7, #44] @ 0x2c q1q1 = q1 * q1; 800389e: 6eb9 ldr r1, [r7, #104] @ 0x68 80038a0: 6eb8 ldr r0, [r7, #104] @ 0x68 80038a2: f7fd f8a3 bl 80009ec <__aeabi_fmul> 80038a6: 1c03 adds r3, r0, #0 80038a8: 62bb str r3, [r7, #40] @ 0x28 q2q2 = q2 * q2; 80038aa: 6e79 ldr r1, [r7, #100] @ 0x64 80038ac: 6e78 ldr r0, [r7, #100] @ 0x64 80038ae: f7fd f89d bl 80009ec <__aeabi_fmul> 80038b2: 1c03 adds r3, r0, #0 80038b4: 627b str r3, [r7, #36] @ 0x24 q3q3 = q3 * q3; 80038b6: 6e39 ldr r1, [r7, #96] @ 0x60 80038b8: 6e38 ldr r0, [r7, #96] @ 0x60 80038ba: f7fd f897 bl 80009ec <__aeabi_fmul> 80038be: 1c03 adds r3, r0, #0 80038c0: 623b str r3, [r7, #32] // Gradient decent algorithm corrective step s0 = _4q0 * q2q2 + _2q2 * ax + _4q0 * q1q1 - _2q1 * ay; 80038c2: 6a79 ldr r1, [r7, #36] @ 0x24 80038c4: 6c38 ldr r0, [r7, #64] @ 0x40 80038c6: f7fd f891 bl 80009ec <__aeabi_fmul> 80038ca: 1c03 adds r3, r0, #0 80038cc: 1c1c adds r4, r3, #0 80038ce: 2208 movs r2, #8 80038d0: 18ab adds r3, r5, r2 80038d2: 19da adds r2, r3, r7 80038d4: 6811 ldr r1, [r2, #0] 80038d6: 6cb8 ldr r0, [r7, #72] @ 0x48 80038d8: f7fd f888 bl 80009ec <__aeabi_fmul> 80038dc: 1c03 adds r3, r0, #0 80038de: 1c19 adds r1, r3, #0 80038e0: 1c20 adds r0, r4, #0 80038e2: f7fc fd13 bl 800030c <__aeabi_fadd> 80038e6: 1c03 adds r3, r0, #0 80038e8: 1c1c adds r4, r3, #0 80038ea: 6ab9 ldr r1, [r7, #40] @ 0x28 80038ec: 6c38 ldr r0, [r7, #64] @ 0x40 80038ee: f7fd f87d bl 80009ec <__aeabi_fmul> 80038f2: 1c03 adds r3, r0, #0 80038f4: 1c19 adds r1, r3, #0 80038f6: 1c20 adds r0, r4, #0 80038f8: f7fc fd08 bl 800030c <__aeabi_fadd> 80038fc: 1c03 adds r3, r0, #0 80038fe: 1c1c adds r4, r3, #0 8003900: 2208 movs r2, #8 8003902: 18b3 adds r3, r6, r2 8003904: 19da adds r2, r3, r7 8003906: 6811 ldr r1, [r2, #0] 8003908: 6cf8 ldr r0, [r7, #76] @ 0x4c 800390a: f7fd f86f bl 80009ec <__aeabi_fmul> 800390e: 1c03 adds r3, r0, #0 8003910: 1c19 adds r1, r3, #0 8003912: 1c20 adds r0, r4, #0 8003914: f7fd f9a8 bl 8000c68 <__aeabi_fsub> 8003918: 1c03 adds r3, r0, #0 800391a: 61fb str r3, [r7, #28] s1 = _4q1 * q3q3 - _2q3 * ax + 4.0f * q0q0 * q1 - _2q0 * ay - _4q1 + _8q1 * q1q1 + _8q1 * q2q2 + _4q1 * az; 800391c: 6a39 ldr r1, [r7, #32] 800391e: 6bf8 ldr r0, [r7, #60] @ 0x3c 8003920: f7fd f864 bl 80009ec <__aeabi_fmul> 8003924: 1c03 adds r3, r0, #0 8003926: 1c1c adds r4, r3, #0 8003928: 2208 movs r2, #8 800392a: 18ab adds r3, r5, r2 800392c: 19da adds r2, r3, r7 800392e: 6811 ldr r1, [r2, #0] 8003930: 6c78 ldr r0, [r7, #68] @ 0x44 8003932: f7fd f85b bl 80009ec <__aeabi_fmul> 8003936: 1c03 adds r3, r0, #0 8003938: 1c19 adds r1, r3, #0 800393a: 1c20 adds r0, r4, #0 800393c: f7fd f994 bl 8000c68 <__aeabi_fsub> 8003940: 1c03 adds r3, r0, #0 8003942: 1c1c adds r4, r3, #0 8003944: 2181 movs r1, #129 @ 0x81 8003946: 05c9 lsls r1, r1, #23 8003948: 6af8 ldr r0, [r7, #44] @ 0x2c 800394a: f7fd f84f bl 80009ec <__aeabi_fmul> 800394e: 1c03 adds r3, r0, #0 8003950: 6eb9 ldr r1, [r7, #104] @ 0x68 8003952: 1c18 adds r0, r3, #0 8003954: f7fd f84a bl 80009ec <__aeabi_fmul> 8003958: 1c03 adds r3, r0, #0 800395a: 1c19 adds r1, r3, #0 800395c: 1c20 adds r0, r4, #0 800395e: f7fc fcd5 bl 800030c <__aeabi_fadd> 8003962: 1c03 adds r3, r0, #0 8003964: 1c1c adds r4, r3, #0 8003966: 2208 movs r2, #8 8003968: 18b3 adds r3, r6, r2 800396a: 19da adds r2, r3, r7 800396c: 6811 ldr r1, [r2, #0] 800396e: 6d38 ldr r0, [r7, #80] @ 0x50 8003970: f7fd f83c bl 80009ec <__aeabi_fmul> 8003974: 1c03 adds r3, r0, #0 8003976: 1c19 adds r1, r3, #0 8003978: 1c20 adds r0, r4, #0 800397a: f7fd f975 bl 8000c68 <__aeabi_fsub> 800397e: 1c03 adds r3, r0, #0 8003980: 6bf9 ldr r1, [r7, #60] @ 0x3c 8003982: 1c18 adds r0, r3, #0 8003984: f7fd f970 bl 8000c68 <__aeabi_fsub> 8003988: 1c03 adds r3, r0, #0 800398a: 1c1c adds r4, r3, #0 800398c: 6ab9 ldr r1, [r7, #40] @ 0x28 800398e: 6b78 ldr r0, [r7, #52] @ 0x34 8003990: f7fd f82c bl 80009ec <__aeabi_fmul> 8003994: 1c03 adds r3, r0, #0 8003996: 1c19 adds r1, r3, #0 8003998: 1c20 adds r0, r4, #0 800399a: f7fc fcb7 bl 800030c <__aeabi_fadd> 800399e: 1c03 adds r3, r0, #0 80039a0: 1c1c adds r4, r3, #0 80039a2: 6a79 ldr r1, [r7, #36] @ 0x24 80039a4: 6b78 ldr r0, [r7, #52] @ 0x34 80039a6: f7fd f821 bl 80009ec <__aeabi_fmul> 80039aa: 1c03 adds r3, r0, #0 80039ac: 1c19 adds r1, r3, #0 80039ae: 1c20 adds r0, r4, #0 80039b0: f7fc fcac bl 800030c <__aeabi_fadd> 80039b4: 1c03 adds r3, r0, #0 80039b6: 1c1c adds r4, r3, #0 80039b8: 2398 movs r3, #152 @ 0x98 80039ba: 2208 movs r2, #8 80039bc: 189b adds r3, r3, r2 80039be: 19da adds r2, r3, r7 80039c0: 6811 ldr r1, [r2, #0] 80039c2: 6bf8 ldr r0, [r7, #60] @ 0x3c 80039c4: f7fd f812 bl 80009ec <__aeabi_fmul> 80039c8: 1c03 adds r3, r0, #0 80039ca: 1c19 adds r1, r3, #0 80039cc: 1c20 adds r0, r4, #0 80039ce: f7fc fc9d bl 800030c <__aeabi_fadd> 80039d2: 1c03 adds r3, r0, #0 80039d4: 61bb str r3, [r7, #24] s2 = 4.0f * q0q0 * q2 + _2q0 * ax + _4q2 * q3q3 - _2q3 * ay - _4q2 + _8q2 * q1q1 + _8q2 * q2q2 + _4q2 * az; 80039d6: 2181 movs r1, #129 @ 0x81 80039d8: 05c9 lsls r1, r1, #23 80039da: 6af8 ldr r0, [r7, #44] @ 0x2c 80039dc: f7fd f806 bl 80009ec <__aeabi_fmul> 80039e0: 1c03 adds r3, r0, #0 80039e2: 6e79 ldr r1, [r7, #100] @ 0x64 80039e4: 1c18 adds r0, r3, #0 80039e6: f7fd f801 bl 80009ec <__aeabi_fmul> 80039ea: 1c03 adds r3, r0, #0 80039ec: 1c1c adds r4, r3, #0 80039ee: 2208 movs r2, #8 80039f0: 18a9 adds r1, r5, r2 80039f2: 19ca adds r2, r1, r7 80039f4: 6811 ldr r1, [r2, #0] 80039f6: 6d38 ldr r0, [r7, #80] @ 0x50 80039f8: f7fc fff8 bl 80009ec <__aeabi_fmul> 80039fc: 1c03 adds r3, r0, #0 80039fe: 1c19 adds r1, r3, #0 8003a00: 1c20 adds r0, r4, #0 8003a02: f7fc fc83 bl 800030c <__aeabi_fadd> 8003a06: 1c03 adds r3, r0, #0 8003a08: 1c1c adds r4, r3, #0 8003a0a: 6a39 ldr r1, [r7, #32] 8003a0c: 6bb8 ldr r0, [r7, #56] @ 0x38 8003a0e: f7fc ffed bl 80009ec <__aeabi_fmul> 8003a12: 1c03 adds r3, r0, #0 8003a14: 1c19 adds r1, r3, #0 8003a16: 1c20 adds r0, r4, #0 8003a18: f7fc fc78 bl 800030c <__aeabi_fadd> 8003a1c: 1c03 adds r3, r0, #0 8003a1e: 1c1c adds r4, r3, #0 8003a20: 2208 movs r2, #8 8003a22: 18b1 adds r1, r6, r2 8003a24: 19ca adds r2, r1, r7 8003a26: 6811 ldr r1, [r2, #0] 8003a28: 6c78 ldr r0, [r7, #68] @ 0x44 8003a2a: f7fc ffdf bl 80009ec <__aeabi_fmul> 8003a2e: 1c03 adds r3, r0, #0 8003a30: 1c19 adds r1, r3, #0 8003a32: 1c20 adds r0, r4, #0 8003a34: f7fd f918 bl 8000c68 <__aeabi_fsub> 8003a38: 1c03 adds r3, r0, #0 8003a3a: 6bb9 ldr r1, [r7, #56] @ 0x38 8003a3c: 1c18 adds r0, r3, #0 8003a3e: f7fd f913 bl 8000c68 <__aeabi_fsub> 8003a42: 1c03 adds r3, r0, #0 8003a44: 1c1c adds r4, r3, #0 8003a46: 6ab9 ldr r1, [r7, #40] @ 0x28 8003a48: 6b38 ldr r0, [r7, #48] @ 0x30 8003a4a: f7fc ffcf bl 80009ec <__aeabi_fmul> 8003a4e: 1c03 adds r3, r0, #0 8003a50: 1c19 adds r1, r3, #0 8003a52: 1c20 adds r0, r4, #0 8003a54: f7fc fc5a bl 800030c <__aeabi_fadd> 8003a58: 1c03 adds r3, r0, #0 8003a5a: 1c1c adds r4, r3, #0 8003a5c: 6a79 ldr r1, [r7, #36] @ 0x24 8003a5e: 6b38 ldr r0, [r7, #48] @ 0x30 8003a60: f7fc ffc4 bl 80009ec <__aeabi_fmul> 8003a64: 1c03 adds r3, r0, #0 8003a66: 1c19 adds r1, r3, #0 8003a68: 1c20 adds r0, r4, #0 8003a6a: f7fc fc4f bl 800030c <__aeabi_fadd> 8003a6e: 1c03 adds r3, r0, #0 8003a70: 1c1c adds r4, r3, #0 8003a72: 2398 movs r3, #152 @ 0x98 8003a74: 2208 movs r2, #8 8003a76: 1899 adds r1, r3, r2 8003a78: 19cb adds r3, r1, r7 8003a7a: 6819 ldr r1, [r3, #0] 8003a7c: 6bb8 ldr r0, [r7, #56] @ 0x38 8003a7e: f7fc ffb5 bl 80009ec <__aeabi_fmul> 8003a82: 1c03 adds r3, r0, #0 8003a84: 1c19 adds r1, r3, #0 8003a86: 1c20 adds r0, r4, #0 8003a88: f7fc fc40 bl 800030c <__aeabi_fadd> 8003a8c: 1c03 adds r3, r0, #0 8003a8e: 617b str r3, [r7, #20] s3 = 4.0f * q1q1 * q3 - _2q1 * ax + 4.0f * q2q2 * q3 - _2q2 * ay; 8003a90: 2181 movs r1, #129 @ 0x81 8003a92: 05c9 lsls r1, r1, #23 8003a94: 6ab8 ldr r0, [r7, #40] @ 0x28 8003a96: f7fc ffa9 bl 80009ec <__aeabi_fmul> 8003a9a: 1c03 adds r3, r0, #0 8003a9c: 6e39 ldr r1, [r7, #96] @ 0x60 8003a9e: 1c18 adds r0, r3, #0 8003aa0: f7fc ffa4 bl 80009ec <__aeabi_fmul> 8003aa4: 1c03 adds r3, r0, #0 8003aa6: 1c1c adds r4, r3, #0 8003aa8: 2308 movs r3, #8 8003aaa: 18ea adds r2, r5, r3 8003aac: 19d3 adds r3, r2, r7 8003aae: 6819 ldr r1, [r3, #0] 8003ab0: 6cf8 ldr r0, [r7, #76] @ 0x4c 8003ab2: f7fc ff9b bl 80009ec <__aeabi_fmul> 8003ab6: 1c03 adds r3, r0, #0 8003ab8: 1c19 adds r1, r3, #0 8003aba: 1c20 adds r0, r4, #0 8003abc: f7fd f8d4 bl 8000c68 <__aeabi_fsub> 8003ac0: 1c03 adds r3, r0, #0 8003ac2: 1c1c adds r4, r3, #0 8003ac4: 2181 movs r1, #129 @ 0x81 8003ac6: 05c9 lsls r1, r1, #23 8003ac8: 6a78 ldr r0, [r7, #36] @ 0x24 8003aca: f7fc ff8f bl 80009ec <__aeabi_fmul> 8003ace: 1c03 adds r3, r0, #0 8003ad0: 6e39 ldr r1, [r7, #96] @ 0x60 8003ad2: 1c18 adds r0, r3, #0 8003ad4: f7fc ff8a bl 80009ec <__aeabi_fmul> 8003ad8: 1c03 adds r3, r0, #0 8003ada: 1c19 adds r1, r3, #0 8003adc: 1c20 adds r0, r4, #0 8003ade: f7fc fc15 bl 800030c <__aeabi_fadd> 8003ae2: 1c03 adds r3, r0, #0 8003ae4: 1c1c adds r4, r3, #0 8003ae6: 2308 movs r3, #8 8003ae8: 18f3 adds r3, r6, r3 8003aea: 19db adds r3, r3, r7 8003aec: 6819 ldr r1, [r3, #0] 8003aee: 6cb8 ldr r0, [r7, #72] @ 0x48 8003af0: f7fc ff7c bl 80009ec <__aeabi_fmul> 8003af4: 1c03 adds r3, r0, #0 8003af6: 1c19 adds r1, r3, #0 8003af8: 1c20 adds r0, r4, #0 8003afa: f7fd f8b5 bl 8000c68 <__aeabi_fsub> 8003afe: 1c03 adds r3, r0, #0 8003b00: 613b str r3, [r7, #16] recipNorm = invSqrt(s0 * s0 + s1 * s1 + s2 * s2 + s3 * s3); // normalise step magnitude 8003b02: 69f9 ldr r1, [r7, #28] 8003b04: 69f8 ldr r0, [r7, #28] 8003b06: f7fc ff71 bl 80009ec <__aeabi_fmul> 8003b0a: 1c03 adds r3, r0, #0 8003b0c: 1c1c adds r4, r3, #0 8003b0e: 69b9 ldr r1, [r7, #24] 8003b10: 69b8 ldr r0, [r7, #24] 8003b12: f7fc ff6b bl 80009ec <__aeabi_fmul> 8003b16: 1c03 adds r3, r0, #0 8003b18: 1c19 adds r1, r3, #0 8003b1a: 1c20 adds r0, r4, #0 8003b1c: f7fc fbf6 bl 800030c <__aeabi_fadd> 8003b20: 1c03 adds r3, r0, #0 8003b22: 1c1c adds r4, r3, #0 8003b24: 6979 ldr r1, [r7, #20] 8003b26: 6978 ldr r0, [r7, #20] 8003b28: f7fc ff60 bl 80009ec <__aeabi_fmul> 8003b2c: 1c03 adds r3, r0, #0 8003b2e: 1c19 adds r1, r3, #0 8003b30: 1c20 adds r0, r4, #0 8003b32: f7fc fbeb bl 800030c <__aeabi_fadd> 8003b36: 1c03 adds r3, r0, #0 8003b38: 1c1c adds r4, r3, #0 8003b3a: 6939 ldr r1, [r7, #16] 8003b3c: 6938 ldr r0, [r7, #16] 8003b3e: f7fc ff55 bl 80009ec <__aeabi_fmul> 8003b42: 1c03 adds r3, r0, #0 8003b44: 1c19 adds r1, r3, #0 8003b46: 1c20 adds r0, r4, #0 8003b48: f7fc fbe0 bl 800030c <__aeabi_fadd> 8003b4c: 1c03 adds r3, r0, #0 8003b4e: 1c18 adds r0, r3, #0 8003b50: f7ff fcb0 bl 80034b4 8003b54: 1c03 adds r3, r0, #0 8003b56: 657b str r3, [r7, #84] @ 0x54 s0 *= recipNorm; 8003b58: 6d79 ldr r1, [r7, #84] @ 0x54 8003b5a: 69f8 ldr r0, [r7, #28] 8003b5c: f7fc ff46 bl 80009ec <__aeabi_fmul> 8003b60: 1c03 adds r3, r0, #0 8003b62: 61fb str r3, [r7, #28] s1 *= recipNorm; 8003b64: 6d79 ldr r1, [r7, #84] @ 0x54 8003b66: 69b8 ldr r0, [r7, #24] 8003b68: f7fc ff40 bl 80009ec <__aeabi_fmul> 8003b6c: 1c03 adds r3, r0, #0 8003b6e: 61bb str r3, [r7, #24] s2 *= recipNorm; 8003b70: 6d79 ldr r1, [r7, #84] @ 0x54 8003b72: 6978 ldr r0, [r7, #20] 8003b74: f7fc ff3a bl 80009ec <__aeabi_fmul> 8003b78: 1c03 adds r3, r0, #0 8003b7a: 617b str r3, [r7, #20] s3 *= recipNorm; 8003b7c: 6d79 ldr r1, [r7, #84] @ 0x54 8003b7e: 6938 ldr r0, [r7, #16] 8003b80: f7fc ff34 bl 80009ec <__aeabi_fmul> 8003b84: 1c03 adds r3, r0, #0 8003b86: 613b str r3, [r7, #16] // Apply feedback step qDot1 -= beta * s0; 8003b88: 69f9 ldr r1, [r7, #28] 8003b8a: 6df8 ldr r0, [r7, #92] @ 0x5c 8003b8c: f7fc ff2e bl 80009ec <__aeabi_fmul> 8003b90: 1c03 adds r3, r0, #0 8003b92: 1c19 adds r1, r3, #0 8003b94: 6ff8 ldr r0, [r7, #124] @ 0x7c 8003b96: f7fd f867 bl 8000c68 <__aeabi_fsub> 8003b9a: 1c03 adds r3, r0, #0 8003b9c: 67fb str r3, [r7, #124] @ 0x7c qDot2 -= beta * s1; 8003b9e: 69b9 ldr r1, [r7, #24] 8003ba0: 6df8 ldr r0, [r7, #92] @ 0x5c 8003ba2: f7fc ff23 bl 80009ec <__aeabi_fmul> 8003ba6: 1c03 adds r3, r0, #0 8003ba8: 1c19 adds r1, r3, #0 8003baa: 6fb8 ldr r0, [r7, #120] @ 0x78 8003bac: f7fd f85c bl 8000c68 <__aeabi_fsub> 8003bb0: 1c03 adds r3, r0, #0 8003bb2: 67bb str r3, [r7, #120] @ 0x78 qDot3 -= beta * s2; 8003bb4: 6979 ldr r1, [r7, #20] 8003bb6: 6df8 ldr r0, [r7, #92] @ 0x5c 8003bb8: f7fc ff18 bl 80009ec <__aeabi_fmul> 8003bbc: 1c03 adds r3, r0, #0 8003bbe: 1c19 adds r1, r3, #0 8003bc0: 6f78 ldr r0, [r7, #116] @ 0x74 8003bc2: f7fd f851 bl 8000c68 <__aeabi_fsub> 8003bc6: 1c03 adds r3, r0, #0 8003bc8: 677b str r3, [r7, #116] @ 0x74 qDot4 -= beta * s3; 8003bca: 6939 ldr r1, [r7, #16] 8003bcc: 6df8 ldr r0, [r7, #92] @ 0x5c 8003bce: f7fc ff0d bl 80009ec <__aeabi_fmul> 8003bd2: 1c03 adds r3, r0, #0 8003bd4: 1c19 adds r1, r3, #0 8003bd6: 6f38 ldr r0, [r7, #112] @ 0x70 8003bd8: f7fd f846 bl 8000c68 <__aeabi_fsub> 8003bdc: 1c03 adds r3, r0, #0 8003bde: 673b str r3, [r7, #112] @ 0x70 } // Integrate rate of change of quaternion to yield quaternion q0 += qDot1 * (1.0f / sampleFreq); 8003be0: 6db9 ldr r1, [r7, #88] @ 0x58 8003be2: 20fe movs r0, #254 @ 0xfe 8003be4: 0580 lsls r0, r0, #22 8003be6: f7fc fd1b bl 8000620 <__aeabi_fdiv> 8003bea: 1c03 adds r3, r0, #0 8003bec: 6ff9 ldr r1, [r7, #124] @ 0x7c 8003bee: 1c18 adds r0, r3, #0 8003bf0: f7fc fefc bl 80009ec <__aeabi_fmul> 8003bf4: 1c03 adds r3, r0, #0 8003bf6: 1c19 adds r1, r3, #0 8003bf8: 6ef8 ldr r0, [r7, #108] @ 0x6c 8003bfa: f7fc fb87 bl 800030c <__aeabi_fadd> 8003bfe: 1c03 adds r3, r0, #0 8003c00: 66fb str r3, [r7, #108] @ 0x6c q1 += qDot2 * (1.0f / sampleFreq); 8003c02: 6db9 ldr r1, [r7, #88] @ 0x58 8003c04: 20fe movs r0, #254 @ 0xfe 8003c06: 0580 lsls r0, r0, #22 8003c08: f7fc fd0a bl 8000620 <__aeabi_fdiv> 8003c0c: 1c03 adds r3, r0, #0 8003c0e: 6fb9 ldr r1, [r7, #120] @ 0x78 8003c10: 1c18 adds r0, r3, #0 8003c12: f7fc feeb bl 80009ec <__aeabi_fmul> 8003c16: 1c03 adds r3, r0, #0 8003c18: 1c19 adds r1, r3, #0 8003c1a: 6eb8 ldr r0, [r7, #104] @ 0x68 8003c1c: f7fc fb76 bl 800030c <__aeabi_fadd> 8003c20: 1c03 adds r3, r0, #0 8003c22: 66bb str r3, [r7, #104] @ 0x68 q2 += qDot3 * (1.0f / sampleFreq); 8003c24: 6db9 ldr r1, [r7, #88] @ 0x58 8003c26: 20fe movs r0, #254 @ 0xfe 8003c28: 0580 lsls r0, r0, #22 8003c2a: f7fc fcf9 bl 8000620 <__aeabi_fdiv> 8003c2e: 1c03 adds r3, r0, #0 8003c30: 6f79 ldr r1, [r7, #116] @ 0x74 8003c32: 1c18 adds r0, r3, #0 8003c34: f7fc feda bl 80009ec <__aeabi_fmul> 8003c38: 1c03 adds r3, r0, #0 8003c3a: 1c19 adds r1, r3, #0 8003c3c: 6e78 ldr r0, [r7, #100] @ 0x64 8003c3e: f7fc fb65 bl 800030c <__aeabi_fadd> 8003c42: 1c03 adds r3, r0, #0 8003c44: 667b str r3, [r7, #100] @ 0x64 q3 += qDot4 * (1.0f / sampleFreq); 8003c46: 6db9 ldr r1, [r7, #88] @ 0x58 8003c48: 20fe movs r0, #254 @ 0xfe 8003c4a: 0580 lsls r0, r0, #22 8003c4c: f7fc fce8 bl 8000620 <__aeabi_fdiv> 8003c50: 1c03 adds r3, r0, #0 8003c52: 6f39 ldr r1, [r7, #112] @ 0x70 8003c54: 1c18 adds r0, r3, #0 8003c56: f7fc fec9 bl 80009ec <__aeabi_fmul> 8003c5a: 1c03 adds r3, r0, #0 8003c5c: 1c19 adds r1, r3, #0 8003c5e: 6e38 ldr r0, [r7, #96] @ 0x60 8003c60: f7fc fb54 bl 800030c <__aeabi_fadd> 8003c64: 1c03 adds r3, r0, #0 8003c66: 663b str r3, [r7, #96] @ 0x60 // Normalise quaternion recipNorm = invSqrt(q0 * q0 + q1 * q1 + q2 * q2 + q3 * q3); 8003c68: 6ef9 ldr r1, [r7, #108] @ 0x6c 8003c6a: 6ef8 ldr r0, [r7, #108] @ 0x6c 8003c6c: f7fc febe bl 80009ec <__aeabi_fmul> 8003c70: 1c03 adds r3, r0, #0 8003c72: 1c1c adds r4, r3, #0 8003c74: 6eb9 ldr r1, [r7, #104] @ 0x68 8003c76: 6eb8 ldr r0, [r7, #104] @ 0x68 8003c78: f7fc feb8 bl 80009ec <__aeabi_fmul> 8003c7c: 1c03 adds r3, r0, #0 8003c7e: 1c19 adds r1, r3, #0 8003c80: 1c20 adds r0, r4, #0 8003c82: f7fc fb43 bl 800030c <__aeabi_fadd> 8003c86: 1c03 adds r3, r0, #0 8003c88: 1c1c adds r4, r3, #0 8003c8a: 6e79 ldr r1, [r7, #100] @ 0x64 8003c8c: 6e78 ldr r0, [r7, #100] @ 0x64 8003c8e: f7fc fead bl 80009ec <__aeabi_fmul> 8003c92: 1c03 adds r3, r0, #0 8003c94: 1c19 adds r1, r3, #0 8003c96: 1c20 adds r0, r4, #0 8003c98: f7fc fb38 bl 800030c <__aeabi_fadd> 8003c9c: 1c03 adds r3, r0, #0 8003c9e: 1c1c adds r4, r3, #0 8003ca0: 6e39 ldr r1, [r7, #96] @ 0x60 8003ca2: 6e38 ldr r0, [r7, #96] @ 0x60 8003ca4: f7fc fea2 bl 80009ec <__aeabi_fmul> 8003ca8: 1c03 adds r3, r0, #0 8003caa: 1c19 adds r1, r3, #0 8003cac: 1c20 adds r0, r4, #0 8003cae: f7fc fb2d bl 800030c <__aeabi_fadd> 8003cb2: 1c03 adds r3, r0, #0 8003cb4: 1c18 adds r0, r3, #0 8003cb6: f7ff fbfd bl 80034b4 8003cba: 1c03 adds r3, r0, #0 8003cbc: 657b str r3, [r7, #84] @ 0x54 q0 *= recipNorm; 8003cbe: 6d79 ldr r1, [r7, #84] @ 0x54 8003cc0: 6ef8 ldr r0, [r7, #108] @ 0x6c 8003cc2: f7fc fe93 bl 80009ec <__aeabi_fmul> 8003cc6: 1c03 adds r3, r0, #0 8003cc8: 66fb str r3, [r7, #108] @ 0x6c q1 *= recipNorm; 8003cca: 6d79 ldr r1, [r7, #84] @ 0x54 8003ccc: 6eb8 ldr r0, [r7, #104] @ 0x68 8003cce: f7fc fe8d bl 80009ec <__aeabi_fmul> 8003cd2: 1c03 adds r3, r0, #0 8003cd4: 66bb str r3, [r7, #104] @ 0x68 q2 *= recipNorm; 8003cd6: 6d79 ldr r1, [r7, #84] @ 0x54 8003cd8: 6e78 ldr r0, [r7, #100] @ 0x64 8003cda: f7fc fe87 bl 80009ec <__aeabi_fmul> 8003cde: 1c03 adds r3, r0, #0 8003ce0: 667b str r3, [r7, #100] @ 0x64 q3 *= recipNorm; 8003ce2: 6d79 ldr r1, [r7, #84] @ 0x54 8003ce4: 6e38 ldr r0, [r7, #96] @ 0x60 8003ce6: f7fc fe81 bl 80009ec <__aeabi_fmul> 8003cea: 1c03 adds r3, r0, #0 8003cec: 663b str r3, [r7, #96] @ 0x60 handle->q0 = q0; 8003cee: 68fb ldr r3, [r7, #12] 8003cf0: 6efa ldr r2, [r7, #108] @ 0x6c 8003cf2: 609a str r2, [r3, #8] handle->q1 = q1; 8003cf4: 68fb ldr r3, [r7, #12] 8003cf6: 6eba ldr r2, [r7, #104] @ 0x68 8003cf8: 60da str r2, [r3, #12] handle->q2 = q2; 8003cfa: 68fb ldr r3, [r7, #12] 8003cfc: 6e7a ldr r2, [r7, #100] @ 0x64 8003cfe: 611a str r2, [r3, #16] handle->q3 = q3; 8003d00: 68fb ldr r3, [r7, #12] 8003d02: 6e3a ldr r2, [r7, #96] @ 0x60 8003d04: 615a str r2, [r3, #20] handle->lock = 0; 8003d06: 68fb ldr r3, [r7, #12] 8003d08: 2200 movs r2, #0 8003d0a: 761a strb r2, [r3, #24] return 0; 8003d0c: 2300 movs r3, #0 } 8003d0e: 0018 movs r0, r3 8003d10: 46bd mov sp, r7 8003d12: b021 add sp, #132 @ 0x84 8003d14: bdf0 pop {r4, r5, r6, r7, pc} ... 08003d18
: /** * @brief The application entry point. * @retval int */ int main(void) { 8003d18: b580 push {r7, lr} 8003d1a: b082 sub sp, #8 8003d1c: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 8003d1e: f000 fc7d bl 800461c /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8003d22: f000 f825 bl 8003d70 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8003d26: f000 fa3b bl 80041a0 MX_I2C1_Init(); 8003d2a: f000 f87f bl 8003e2c MX_TIM1_Init(); 8003d2e: f000 f8bf bl 8003eb0 MX_TIM2_Init(); 8003d32: f000 f995 bl 8004060 /* USER CODE BEGIN 2 */ int state = 0; 8003d36: 2300 movs r3, #0 8003d38: 607b str r3, [r7, #4] state = MPU6000_Init(&hi2c1, 1000); 8003d3a: 23fa movs r3, #250 @ 0xfa 8003d3c: 009a lsls r2, r3, #2 8003d3e: 4b0a ldr r3, [pc, #40] @ (8003d68 ) 8003d40: 0011 movs r1, r2 8003d42: 0018 movs r0, r3 8003d44: f7ff f992 bl 800306c 8003d48: 0003 movs r3, r0 8003d4a: 607b str r3, [r7, #4] if(!state){ 8003d4c: 687b ldr r3, [r7, #4] 8003d4e: 2b00 cmp r3, #0 8003d50: d106 bne.n 8003d60 HAL_GPIO_WritePin(GPIOC, LED_Pin, 1); 8003d52: 2380 movs r3, #128 @ 0x80 8003d54: 021b lsls r3, r3, #8 8003d56: 4805 ldr r0, [pc, #20] @ (8003d6c ) 8003d58: 2201 movs r2, #1 8003d5a: 0019 movs r1, r3 8003d5c: f000 ffc0 bl 8004ce0 //#ifndef USE_CRSF // SBUS_Check_State(); //#else // CRSF_Check_State(); //#endif IMU_Check_State(); 8003d60: f7ff fa6a bl 8003238 8003d64: e7fc b.n 8003d60 8003d66: 46c0 nop @ (mov r8, r8) 8003d68: 20000900 .word 0x20000900 8003d6c: 50000800 .word 0x50000800 08003d70 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8003d70: b590 push {r4, r7, lr} 8003d72: b093 sub sp, #76 @ 0x4c 8003d74: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8003d76: 2410 movs r4, #16 8003d78: 193b adds r3, r7, r4 8003d7a: 0018 movs r0, r3 8003d7c: 2338 movs r3, #56 @ 0x38 8003d7e: 001a movs r2, r3 8003d80: 2100 movs r1, #0 8003d82: f005 f927 bl 8008fd4 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8003d86: 003b movs r3, r7 8003d88: 0018 movs r0, r3 8003d8a: 2310 movs r3, #16 8003d8c: 001a movs r2, r3 8003d8e: 2100 movs r1, #0 8003d90: f005 f920 bl 8008fd4 /** Configure the main internal regulator output voltage */ HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1); 8003d94: 2380 movs r3, #128 @ 0x80 8003d96: 009b lsls r3, r3, #2 8003d98: 0018 movs r0, r3 8003d9a: f003 fa85 bl 80072a8 /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; 8003d9e: 193b adds r3, r7, r4 8003da0: 2202 movs r2, #2 8003da2: 601a str r2, [r3, #0] RCC_OscInitStruct.HSIState = RCC_HSI_ON; 8003da4: 193b adds r3, r7, r4 8003da6: 2280 movs r2, #128 @ 0x80 8003da8: 0052 lsls r2, r2, #1 8003daa: 60da str r2, [r3, #12] RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1; 8003dac: 0021 movs r1, r4 8003dae: 187b adds r3, r7, r1 8003db0: 2200 movs r2, #0 8003db2: 611a str r2, [r3, #16] RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 8003db4: 187b adds r3, r7, r1 8003db6: 2240 movs r2, #64 @ 0x40 8003db8: 615a str r2, [r3, #20] RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 8003dba: 187b adds r3, r7, r1 8003dbc: 2202 movs r2, #2 8003dbe: 61da str r2, [r3, #28] RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; 8003dc0: 187b adds r3, r7, r1 8003dc2: 2202 movs r2, #2 8003dc4: 621a str r2, [r3, #32] RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1; 8003dc6: 187b adds r3, r7, r1 8003dc8: 2200 movs r2, #0 8003dca: 625a str r2, [r3, #36] @ 0x24 RCC_OscInitStruct.PLL.PLLN = 8; 8003dcc: 187b adds r3, r7, r1 8003dce: 2208 movs r2, #8 8003dd0: 629a str r2, [r3, #40] @ 0x28 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; 8003dd2: 187b adds r3, r7, r1 8003dd4: 2280 movs r2, #128 @ 0x80 8003dd6: 0292 lsls r2, r2, #10 8003dd8: 62da str r2, [r3, #44] @ 0x2c RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; 8003dda: 187b adds r3, r7, r1 8003ddc: 2280 movs r2, #128 @ 0x80 8003dde: 0492 lsls r2, r2, #18 8003de0: 631a str r2, [r3, #48] @ 0x30 RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; 8003de2: 187b adds r3, r7, r1 8003de4: 2280 movs r2, #128 @ 0x80 8003de6: 0592 lsls r2, r2, #22 8003de8: 635a str r2, [r3, #52] @ 0x34 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8003dea: 187b adds r3, r7, r1 8003dec: 0018 movs r0, r3 8003dee: f003 fa9b bl 8007328 8003df2: 1e03 subs r3, r0, #0 8003df4: d001 beq.n 8003dfa { Error_Handler(); 8003df6: f000 fa31 bl 800425c } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8003dfa: 003b movs r3, r7 8003dfc: 2207 movs r2, #7 8003dfe: 601a str r2, [r3, #0] |RCC_CLOCKTYPE_PCLK1; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 8003e00: 003b movs r3, r7 8003e02: 2202 movs r2, #2 8003e04: 605a str r2, [r3, #4] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 8003e06: 003b movs r3, r7 8003e08: 2200 movs r2, #0 8003e0a: 609a str r2, [r3, #8] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 8003e0c: 003b movs r3, r7 8003e0e: 2200 movs r2, #0 8003e10: 60da str r2, [r3, #12] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 8003e12: 003b movs r3, r7 8003e14: 2102 movs r1, #2 8003e16: 0018 movs r0, r3 8003e18: f003 fda0 bl 800795c 8003e1c: 1e03 subs r3, r0, #0 8003e1e: d001 beq.n 8003e24 { Error_Handler(); 8003e20: f000 fa1c bl 800425c } } 8003e24: 46c0 nop @ (mov r8, r8) 8003e26: 46bd mov sp, r7 8003e28: b013 add sp, #76 @ 0x4c 8003e2a: bd90 pop {r4, r7, pc} 08003e2c : * @brief I2C1 Initialization Function * @param None * @retval None */ static void MX_I2C1_Init(void) { 8003e2c: b580 push {r7, lr} 8003e2e: af00 add r7, sp, #0 /* USER CODE END I2C1_Init 0 */ /* USER CODE BEGIN I2C1_Init 1 */ /* USER CODE END I2C1_Init 1 */ hi2c1.Instance = I2C1; 8003e30: 4b1c ldr r3, [pc, #112] @ (8003ea4 ) 8003e32: 4a1d ldr r2, [pc, #116] @ (8003ea8 ) 8003e34: 601a str r2, [r3, #0] hi2c1.Init.Timing = 0x00303D5D; 8003e36: 4b1b ldr r3, [pc, #108] @ (8003ea4 ) 8003e38: 4a1c ldr r2, [pc, #112] @ (8003eac ) 8003e3a: 605a str r2, [r3, #4] hi2c1.Init.OwnAddress1 = 0; 8003e3c: 4b19 ldr r3, [pc, #100] @ (8003ea4 ) 8003e3e: 2200 movs r2, #0 8003e40: 609a str r2, [r3, #8] hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; 8003e42: 4b18 ldr r3, [pc, #96] @ (8003ea4 ) 8003e44: 2201 movs r2, #1 8003e46: 60da str r2, [r3, #12] hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; 8003e48: 4b16 ldr r3, [pc, #88] @ (8003ea4 ) 8003e4a: 2200 movs r2, #0 8003e4c: 611a str r2, [r3, #16] hi2c1.Init.OwnAddress2 = 0; 8003e4e: 4b15 ldr r3, [pc, #84] @ (8003ea4 ) 8003e50: 2200 movs r2, #0 8003e52: 615a str r2, [r3, #20] hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK; 8003e54: 4b13 ldr r3, [pc, #76] @ (8003ea4 ) 8003e56: 2200 movs r2, #0 8003e58: 619a str r2, [r3, #24] hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; 8003e5a: 4b12 ldr r3, [pc, #72] @ (8003ea4 ) 8003e5c: 2200 movs r2, #0 8003e5e: 61da str r2, [r3, #28] hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; 8003e60: 4b10 ldr r3, [pc, #64] @ (8003ea4 ) 8003e62: 2200 movs r2, #0 8003e64: 621a str r2, [r3, #32] if (HAL_I2C_Init(&hi2c1) != HAL_OK) 8003e66: 4b0f ldr r3, [pc, #60] @ (8003ea4 ) 8003e68: 0018 movs r0, r3 8003e6a: f000 ff57 bl 8004d1c 8003e6e: 1e03 subs r3, r0, #0 8003e70: d001 beq.n 8003e76 { Error_Handler(); 8003e72: f000 f9f3 bl 800425c } /** Configure Analogue filter */ if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_DISABLE) != HAL_OK) 8003e76: 2380 movs r3, #128 @ 0x80 8003e78: 015a lsls r2, r3, #5 8003e7a: 4b0a ldr r3, [pc, #40] @ (8003ea4 ) 8003e7c: 0011 movs r1, r2 8003e7e: 0018 movs r0, r3 8003e80: f003 f97a bl 8007178 8003e84: 1e03 subs r3, r0, #0 8003e86: d001 beq.n 8003e8c { Error_Handler(); 8003e88: f000 f9e8 bl 800425c } /** Configure Digital filter */ if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK) 8003e8c: 4b05 ldr r3, [pc, #20] @ (8003ea4 ) 8003e8e: 2100 movs r1, #0 8003e90: 0018 movs r0, r3 8003e92: f003 f9bd bl 8007210 8003e96: 1e03 subs r3, r0, #0 8003e98: d001 beq.n 8003e9e { Error_Handler(); 8003e9a: f000 f9df bl 800425c } /* USER CODE BEGIN I2C1_Init 2 */ /* USER CODE END I2C1_Init 2 */ } 8003e9e: 46c0 nop @ (mov r8, r8) 8003ea0: 46bd mov sp, r7 8003ea2: bd80 pop {r7, pc} 8003ea4: 20000900 .word 0x20000900 8003ea8: 40005400 .word 0x40005400 8003eac: 00303d5d .word 0x00303d5d 08003eb0 : * @brief TIM1 Initialization Function * @param None * @retval None */ static void MX_TIM1_Init(void) { 8003eb0: b580 push {r7, lr} 8003eb2: b09c sub sp, #112 @ 0x70 8003eb4: af00 add r7, sp, #0 /* USER CODE BEGIN TIM1_Init 0 */ /* USER CODE END TIM1_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 8003eb6: 2360 movs r3, #96 @ 0x60 8003eb8: 18fb adds r3, r7, r3 8003eba: 0018 movs r0, r3 8003ebc: 2310 movs r3, #16 8003ebe: 001a movs r2, r3 8003ec0: 2100 movs r1, #0 8003ec2: f005 f887 bl 8008fd4 TIM_MasterConfigTypeDef sMasterConfig = {0}; 8003ec6: 2354 movs r3, #84 @ 0x54 8003ec8: 18fb adds r3, r7, r3 8003eca: 0018 movs r0, r3 8003ecc: 230c movs r3, #12 8003ece: 001a movs r2, r3 8003ed0: 2100 movs r1, #0 8003ed2: f005 f87f bl 8008fd4 TIM_OC_InitTypeDef sConfigOC = {0}; 8003ed6: 2338 movs r3, #56 @ 0x38 8003ed8: 18fb adds r3, r7, r3 8003eda: 0018 movs r0, r3 8003edc: 231c movs r3, #28 8003ede: 001a movs r2, r3 8003ee0: 2100 movs r1, #0 8003ee2: f005 f877 bl 8008fd4 TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0}; 8003ee6: 1d3b adds r3, r7, #4 8003ee8: 0018 movs r0, r3 8003eea: 2334 movs r3, #52 @ 0x34 8003eec: 001a movs r2, r3 8003eee: 2100 movs r1, #0 8003ef0: f005 f870 bl 8008fd4 /* USER CODE BEGIN TIM1_Init 1 */ /* USER CODE END TIM1_Init 1 */ htim1.Instance = TIM1; 8003ef4: 4b56 ldr r3, [pc, #344] @ (8004050 ) 8003ef6: 4a57 ldr r2, [pc, #348] @ (8004054 ) 8003ef8: 601a str r2, [r3, #0] htim1.Init.Prescaler = 63; 8003efa: 4b55 ldr r3, [pc, #340] @ (8004050 ) 8003efc: 223f movs r2, #63 @ 0x3f 8003efe: 605a str r2, [r3, #4] htim1.Init.CounterMode = TIM_COUNTERMODE_UP; 8003f00: 4b53 ldr r3, [pc, #332] @ (8004050 ) 8003f02: 2200 movs r2, #0 8003f04: 609a str r2, [r3, #8] htim1.Init.Period = 19999; 8003f06: 4b52 ldr r3, [pc, #328] @ (8004050 ) 8003f08: 4a53 ldr r2, [pc, #332] @ (8004058 ) 8003f0a: 60da str r2, [r3, #12] htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 8003f0c: 4b50 ldr r3, [pc, #320] @ (8004050 ) 8003f0e: 2200 movs r2, #0 8003f10: 611a str r2, [r3, #16] htim1.Init.RepetitionCounter = 0; 8003f12: 4b4f ldr r3, [pc, #316] @ (8004050 ) 8003f14: 2200 movs r2, #0 8003f16: 615a str r2, [r3, #20] htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 8003f18: 4b4d ldr r3, [pc, #308] @ (8004050 ) 8003f1a: 2200 movs r2, #0 8003f1c: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim1) != HAL_OK) 8003f1e: 4b4c ldr r3, [pc, #304] @ (8004050 ) 8003f20: 0018 movs r0, r3 8003f22: f004 f81f bl 8007f64 8003f26: 1e03 subs r3, r0, #0 8003f28: d001 beq.n 8003f2e { Error_Handler(); 8003f2a: f000 f997 bl 800425c } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 8003f2e: 2160 movs r1, #96 @ 0x60 8003f30: 187b adds r3, r7, r1 8003f32: 2280 movs r2, #128 @ 0x80 8003f34: 0152 lsls r2, r2, #5 8003f36: 601a str r2, [r3, #0] if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK) 8003f38: 187a adds r2, r7, r1 8003f3a: 4b45 ldr r3, [pc, #276] @ (8004050 ) 8003f3c: 0011 movs r1, r2 8003f3e: 0018 movs r0, r3 8003f40: f004 f9c8 bl 80082d4 8003f44: 1e03 subs r3, r0, #0 8003f46: d001 beq.n 8003f4c { Error_Handler(); 8003f48: f000 f988 bl 800425c } if (HAL_TIM_PWM_Init(&htim1) != HAL_OK) 8003f4c: 4b40 ldr r3, [pc, #256] @ (8004050 ) 8003f4e: 0018 movs r0, r3 8003f50: f004 f860 bl 8008014 8003f54: 1e03 subs r3, r0, #0 8003f56: d001 beq.n 8003f5c { Error_Handler(); 8003f58: f000 f980 bl 800425c } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8003f5c: 2154 movs r1, #84 @ 0x54 8003f5e: 187b adds r3, r7, r1 8003f60: 2200 movs r2, #0 8003f62: 601a str r2, [r3, #0] sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET; 8003f64: 187b adds r3, r7, r1 8003f66: 2200 movs r2, #0 8003f68: 605a str r2, [r3, #4] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8003f6a: 187b adds r3, r7, r1 8003f6c: 2200 movs r2, #0 8003f6e: 609a str r2, [r3, #8] if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK) 8003f70: 187a adds r2, r7, r1 8003f72: 4b37 ldr r3, [pc, #220] @ (8004050 ) 8003f74: 0011 movs r1, r2 8003f76: 0018 movs r0, r3 8003f78: f004 fe3e bl 8008bf8 8003f7c: 1e03 subs r3, r0, #0 8003f7e: d001 beq.n 8003f84 { Error_Handler(); 8003f80: f000 f96c bl 800425c } sConfigOC.OCMode = TIM_OCMODE_PWM1; 8003f84: 2138 movs r1, #56 @ 0x38 8003f86: 187b adds r3, r7, r1 8003f88: 2260 movs r2, #96 @ 0x60 8003f8a: 601a str r2, [r3, #0] sConfigOC.Pulse = 1500; 8003f8c: 187b adds r3, r7, r1 8003f8e: 4a33 ldr r2, [pc, #204] @ (800405c ) 8003f90: 605a str r2, [r3, #4] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 8003f92: 187b adds r3, r7, r1 8003f94: 2200 movs r2, #0 8003f96: 609a str r2, [r3, #8] sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH; 8003f98: 187b adds r3, r7, r1 8003f9a: 2200 movs r2, #0 8003f9c: 60da str r2, [r3, #12] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 8003f9e: 187b adds r3, r7, r1 8003fa0: 2200 movs r2, #0 8003fa2: 611a str r2, [r3, #16] sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET; 8003fa4: 187b adds r3, r7, r1 8003fa6: 2200 movs r2, #0 8003fa8: 615a str r2, [r3, #20] sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET; 8003faa: 187b adds r3, r7, r1 8003fac: 2200 movs r2, #0 8003fae: 619a str r2, [r3, #24] if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 8003fb0: 1879 adds r1, r7, r1 8003fb2: 4b27 ldr r3, [pc, #156] @ (8004050 ) 8003fb4: 2200 movs r2, #0 8003fb6: 0018 movs r0, r3 8003fb8: f004 f88c bl 80080d4 8003fbc: 1e03 subs r3, r0, #0 8003fbe: d001 beq.n 8003fc4 { Error_Handler(); 8003fc0: f000 f94c bl 800425c } if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) 8003fc4: 2338 movs r3, #56 @ 0x38 8003fc6: 18f9 adds r1, r7, r3 8003fc8: 4b21 ldr r3, [pc, #132] @ (8004050 ) 8003fca: 220c movs r2, #12 8003fcc: 0018 movs r0, r3 8003fce: f004 f881 bl 80080d4 8003fd2: 1e03 subs r3, r0, #0 8003fd4: d001 beq.n 8003fda { Error_Handler(); 8003fd6: f000 f941 bl 800425c } sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE; 8003fda: 1d3b adds r3, r7, #4 8003fdc: 2200 movs r2, #0 8003fde: 601a str r2, [r3, #0] sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE; 8003fe0: 1d3b adds r3, r7, #4 8003fe2: 2200 movs r2, #0 8003fe4: 605a str r2, [r3, #4] sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF; 8003fe6: 1d3b adds r3, r7, #4 8003fe8: 2200 movs r2, #0 8003fea: 609a str r2, [r3, #8] sBreakDeadTimeConfig.DeadTime = 0; 8003fec: 1d3b adds r3, r7, #4 8003fee: 2200 movs r2, #0 8003ff0: 60da str r2, [r3, #12] sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE; 8003ff2: 1d3b adds r3, r7, #4 8003ff4: 2200 movs r2, #0 8003ff6: 611a str r2, [r3, #16] sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH; 8003ff8: 1d3b adds r3, r7, #4 8003ffa: 2280 movs r2, #128 @ 0x80 8003ffc: 0192 lsls r2, r2, #6 8003ffe: 615a str r2, [r3, #20] sBreakDeadTimeConfig.BreakFilter = 0; 8004000: 1d3b adds r3, r7, #4 8004002: 2200 movs r2, #0 8004004: 619a str r2, [r3, #24] sBreakDeadTimeConfig.BreakAFMode = TIM_BREAK_AFMODE_INPUT; 8004006: 1d3b adds r3, r7, #4 8004008: 2200 movs r2, #0 800400a: 61da str r2, [r3, #28] sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE; 800400c: 1d3b adds r3, r7, #4 800400e: 2200 movs r2, #0 8004010: 621a str r2, [r3, #32] sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH; 8004012: 1d3b adds r3, r7, #4 8004014: 2280 movs r2, #128 @ 0x80 8004016: 0492 lsls r2, r2, #18 8004018: 625a str r2, [r3, #36] @ 0x24 sBreakDeadTimeConfig.Break2Filter = 0; 800401a: 1d3b adds r3, r7, #4 800401c: 2200 movs r2, #0 800401e: 629a str r2, [r3, #40] @ 0x28 sBreakDeadTimeConfig.Break2AFMode = TIM_BREAK_AFMODE_INPUT; 8004020: 1d3b adds r3, r7, #4 8004022: 2200 movs r2, #0 8004024: 62da str r2, [r3, #44] @ 0x2c sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE; 8004026: 1d3b adds r3, r7, #4 8004028: 2200 movs r2, #0 800402a: 631a str r2, [r3, #48] @ 0x30 if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK) 800402c: 1d3a adds r2, r7, #4 800402e: 4b08 ldr r3, [pc, #32] @ (8004050 ) 8004030: 0011 movs r1, r2 8004032: 0018 movs r0, r3 8004034: f004 fe48 bl 8008cc8 8004038: 1e03 subs r3, r0, #0 800403a: d001 beq.n 8004040 { Error_Handler(); 800403c: f000 f90e bl 800425c } /* USER CODE BEGIN TIM1_Init 2 */ /* USER CODE END TIM1_Init 2 */ HAL_TIM_MspPostInit(&htim1); 8004040: 4b03 ldr r3, [pc, #12] @ (8004050 ) 8004042: 0018 movs r0, r3 8004044: f000 f9ea bl 800441c } 8004048: 46c0 nop @ (mov r8, r8) 800404a: 46bd mov sp, r7 800404c: b01c add sp, #112 @ 0x70 800404e: bd80 pop {r7, pc} 8004050: 20000954 .word 0x20000954 8004054: 40012c00 .word 0x40012c00 8004058: 00004e1f .word 0x00004e1f 800405c: 000005dc .word 0x000005dc 08004060 : * @brief TIM2 Initialization Function * @param None * @retval None */ static void MX_TIM2_Init(void) { 8004060: b580 push {r7, lr} 8004062: b08e sub sp, #56 @ 0x38 8004064: af00 add r7, sp, #0 /* USER CODE BEGIN TIM2_Init 0 */ /* USER CODE END TIM2_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 8004066: 2328 movs r3, #40 @ 0x28 8004068: 18fb adds r3, r7, r3 800406a: 0018 movs r0, r3 800406c: 2310 movs r3, #16 800406e: 001a movs r2, r3 8004070: 2100 movs r1, #0 8004072: f004 ffaf bl 8008fd4 TIM_MasterConfigTypeDef sMasterConfig = {0}; 8004076: 231c movs r3, #28 8004078: 18fb adds r3, r7, r3 800407a: 0018 movs r0, r3 800407c: 230c movs r3, #12 800407e: 001a movs r2, r3 8004080: 2100 movs r1, #0 8004082: f004 ffa7 bl 8008fd4 TIM_OC_InitTypeDef sConfigOC = {0}; 8004086: 003b movs r3, r7 8004088: 0018 movs r0, r3 800408a: 231c movs r3, #28 800408c: 001a movs r2, r3 800408e: 2100 movs r1, #0 8004090: f004 ffa0 bl 8008fd4 /* USER CODE BEGIN TIM2_Init 1 */ /* USER CODE END TIM2_Init 1 */ htim2.Instance = TIM2; 8004094: 4b3f ldr r3, [pc, #252] @ (8004194 ) 8004096: 2280 movs r2, #128 @ 0x80 8004098: 05d2 lsls r2, r2, #23 800409a: 601a str r2, [r3, #0] htim2.Init.Prescaler = 63; 800409c: 4b3d ldr r3, [pc, #244] @ (8004194 ) 800409e: 223f movs r2, #63 @ 0x3f 80040a0: 605a str r2, [r3, #4] htim2.Init.CounterMode = TIM_COUNTERMODE_UP; 80040a2: 4b3c ldr r3, [pc, #240] @ (8004194 ) 80040a4: 2200 movs r2, #0 80040a6: 609a str r2, [r3, #8] htim2.Init.Period = 19999; 80040a8: 4b3a ldr r3, [pc, #232] @ (8004194 ) 80040aa: 4a3b ldr r2, [pc, #236] @ (8004198 ) 80040ac: 60da str r2, [r3, #12] htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 80040ae: 4b39 ldr r3, [pc, #228] @ (8004194 ) 80040b0: 2200 movs r2, #0 80040b2: 611a str r2, [r3, #16] htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 80040b4: 4b37 ldr r3, [pc, #220] @ (8004194 ) 80040b6: 2200 movs r2, #0 80040b8: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim2) != HAL_OK) 80040ba: 4b36 ldr r3, [pc, #216] @ (8004194 ) 80040bc: 0018 movs r0, r3 80040be: f003 ff51 bl 8007f64 80040c2: 1e03 subs r3, r0, #0 80040c4: d001 beq.n 80040ca { Error_Handler(); 80040c6: f000 f8c9 bl 800425c } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 80040ca: 2128 movs r1, #40 @ 0x28 80040cc: 187b adds r3, r7, r1 80040ce: 2280 movs r2, #128 @ 0x80 80040d0: 0152 lsls r2, r2, #5 80040d2: 601a str r2, [r3, #0] if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK) 80040d4: 187a adds r2, r7, r1 80040d6: 4b2f ldr r3, [pc, #188] @ (8004194 ) 80040d8: 0011 movs r1, r2 80040da: 0018 movs r0, r3 80040dc: f004 f8fa bl 80082d4 80040e0: 1e03 subs r3, r0, #0 80040e2: d001 beq.n 80040e8 { Error_Handler(); 80040e4: f000 f8ba bl 800425c } if (HAL_TIM_PWM_Init(&htim2) != HAL_OK) 80040e8: 4b2a ldr r3, [pc, #168] @ (8004194 ) 80040ea: 0018 movs r0, r3 80040ec: f003 ff92 bl 8008014 80040f0: 1e03 subs r3, r0, #0 80040f2: d001 beq.n 80040f8 { Error_Handler(); 80040f4: f000 f8b2 bl 800425c } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 80040f8: 211c movs r1, #28 80040fa: 187b adds r3, r7, r1 80040fc: 2200 movs r2, #0 80040fe: 601a str r2, [r3, #0] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8004100: 187b adds r3, r7, r1 8004102: 2200 movs r2, #0 8004104: 609a str r2, [r3, #8] if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) 8004106: 187a adds r2, r7, r1 8004108: 4b22 ldr r3, [pc, #136] @ (8004194 ) 800410a: 0011 movs r1, r2 800410c: 0018 movs r0, r3 800410e: f004 fd73 bl 8008bf8 8004112: 1e03 subs r3, r0, #0 8004114: d001 beq.n 800411a { Error_Handler(); 8004116: f000 f8a1 bl 800425c } sConfigOC.OCMode = TIM_OCMODE_PWM1; 800411a: 003b movs r3, r7 800411c: 2260 movs r2, #96 @ 0x60 800411e: 601a str r2, [r3, #0] sConfigOC.Pulse = 1500; 8004120: 003b movs r3, r7 8004122: 4a1e ldr r2, [pc, #120] @ (800419c ) 8004124: 605a str r2, [r3, #4] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 8004126: 003b movs r3, r7 8004128: 2200 movs r2, #0 800412a: 609a str r2, [r3, #8] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 800412c: 003b movs r3, r7 800412e: 2200 movs r2, #0 8004130: 611a str r2, [r3, #16] if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 8004132: 0039 movs r1, r7 8004134: 4b17 ldr r3, [pc, #92] @ (8004194 ) 8004136: 2200 movs r2, #0 8004138: 0018 movs r0, r3 800413a: f003 ffcb bl 80080d4 800413e: 1e03 subs r3, r0, #0 8004140: d001 beq.n 8004146 { Error_Handler(); 8004142: f000 f88b bl 800425c } if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 8004146: 0039 movs r1, r7 8004148: 4b12 ldr r3, [pc, #72] @ (8004194 ) 800414a: 2204 movs r2, #4 800414c: 0018 movs r0, r3 800414e: f003 ffc1 bl 80080d4 8004152: 1e03 subs r3, r0, #0 8004154: d001 beq.n 800415a { Error_Handler(); 8004156: f000 f881 bl 800425c } if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) 800415a: 0039 movs r1, r7 800415c: 4b0d ldr r3, [pc, #52] @ (8004194 ) 800415e: 2208 movs r2, #8 8004160: 0018 movs r0, r3 8004162: f003 ffb7 bl 80080d4 8004166: 1e03 subs r3, r0, #0 8004168: d001 beq.n 800416e { Error_Handler(); 800416a: f000 f877 bl 800425c } if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) 800416e: 0039 movs r1, r7 8004170: 4b08 ldr r3, [pc, #32] @ (8004194 ) 8004172: 220c movs r2, #12 8004174: 0018 movs r0, r3 8004176: f003 ffad bl 80080d4 800417a: 1e03 subs r3, r0, #0 800417c: d001 beq.n 8004182 { Error_Handler(); 800417e: f000 f86d bl 800425c } /* USER CODE BEGIN TIM2_Init 2 */ /* USER CODE END TIM2_Init 2 */ HAL_TIM_MspPostInit(&htim2); 8004182: 4b04 ldr r3, [pc, #16] @ (8004194 ) 8004184: 0018 movs r0, r3 8004186: f000 f949 bl 800441c } 800418a: 46c0 nop @ (mov r8, r8) 800418c: 46bd mov sp, r7 800418e: b00e add sp, #56 @ 0x38 8004190: bd80 pop {r7, pc} 8004192: 46c0 nop @ (mov r8, r8) 8004194: 200009a0 .word 0x200009a0 8004198: 00004e1f .word 0x00004e1f 800419c: 000005dc .word 0x000005dc 080041a0 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 80041a0: b590 push {r4, r7, lr} 80041a2: b089 sub sp, #36 @ 0x24 80041a4: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 80041a6: 240c movs r4, #12 80041a8: 193b adds r3, r7, r4 80041aa: 0018 movs r0, r3 80041ac: 2314 movs r3, #20 80041ae: 001a movs r2, r3 80041b0: 2100 movs r1, #0 80041b2: f004 ff0f bl 8008fd4 /* USER CODE BEGIN MX_GPIO_Init_1 */ /* USER CODE END MX_GPIO_Init_1 */ /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOB_CLK_ENABLE(); 80041b6: 4b21 ldr r3, [pc, #132] @ (800423c ) 80041b8: 6b5a ldr r2, [r3, #52] @ 0x34 80041ba: 4b20 ldr r3, [pc, #128] @ (800423c ) 80041bc: 2102 movs r1, #2 80041be: 430a orrs r2, r1 80041c0: 635a str r2, [r3, #52] @ 0x34 80041c2: 4b1e ldr r3, [pc, #120] @ (800423c ) 80041c4: 6b5b ldr r3, [r3, #52] @ 0x34 80041c6: 2202 movs r2, #2 80041c8: 4013 ands r3, r2 80041ca: 60bb str r3, [r7, #8] 80041cc: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOC_CLK_ENABLE(); 80041ce: 4b1b ldr r3, [pc, #108] @ (800423c ) 80041d0: 6b5a ldr r2, [r3, #52] @ 0x34 80041d2: 4b1a ldr r3, [pc, #104] @ (800423c ) 80041d4: 2104 movs r1, #4 80041d6: 430a orrs r2, r1 80041d8: 635a str r2, [r3, #52] @ 0x34 80041da: 4b18 ldr r3, [pc, #96] @ (800423c ) 80041dc: 6b5b ldr r3, [r3, #52] @ 0x34 80041de: 2204 movs r2, #4 80041e0: 4013 ands r3, r2 80041e2: 607b str r3, [r7, #4] 80041e4: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOA_CLK_ENABLE(); 80041e6: 4b15 ldr r3, [pc, #84] @ (800423c ) 80041e8: 6b5a ldr r2, [r3, #52] @ 0x34 80041ea: 4b14 ldr r3, [pc, #80] @ (800423c ) 80041ec: 2101 movs r1, #1 80041ee: 430a orrs r2, r1 80041f0: 635a str r2, [r3, #52] @ 0x34 80041f2: 4b12 ldr r3, [pc, #72] @ (800423c ) 80041f4: 6b5b ldr r3, [r3, #52] @ 0x34 80041f6: 2201 movs r2, #1 80041f8: 4013 ands r3, r2 80041fa: 603b str r3, [r7, #0] 80041fc: 683b ldr r3, [r7, #0] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(LED_GPIO_Port, LED_Pin, GPIO_PIN_RESET); 80041fe: 2380 movs r3, #128 @ 0x80 8004200: 021b lsls r3, r3, #8 8004202: 480f ldr r0, [pc, #60] @ (8004240 ) 8004204: 2200 movs r2, #0 8004206: 0019 movs r1, r3 8004208: f000 fd6a bl 8004ce0 /*Configure GPIO pin : LED_Pin */ GPIO_InitStruct.Pin = LED_Pin; 800420c: 193b adds r3, r7, r4 800420e: 2280 movs r2, #128 @ 0x80 8004210: 0212 lsls r2, r2, #8 8004212: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8004214: 193b adds r3, r7, r4 8004216: 2201 movs r2, #1 8004218: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 800421a: 193b adds r3, r7, r4 800421c: 2200 movs r2, #0 800421e: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8004220: 193b adds r3, r7, r4 8004222: 2200 movs r2, #0 8004224: 60da str r2, [r3, #12] HAL_GPIO_Init(LED_GPIO_Port, &GPIO_InitStruct); 8004226: 193b adds r3, r7, r4 8004228: 4a05 ldr r2, [pc, #20] @ (8004240 ) 800422a: 0019 movs r1, r3 800422c: 0010 movs r0, r2 800422e: f000 fbf3 bl 8004a18 /* USER CODE BEGIN MX_GPIO_Init_2 */ /* USER CODE END MX_GPIO_Init_2 */ } 8004232: 46c0 nop @ (mov r8, r8) 8004234: 46bd mov sp, r7 8004236: b009 add sp, #36 @ 0x24 8004238: bd90 pop {r4, r7, pc} 800423a: 46c0 nop @ (mov r8, r8) 800423c: 40021000 .word 0x40021000 8004240: 50000800 .word 0x50000800 08004244 : #else CRSF_UART_Callback(huart); #endif }*/ void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c){ 8004244: b580 push {r7, lr} 8004246: b082 sub sp, #8 8004248: af00 add r7, sp, #0 800424a: 6078 str r0, [r7, #4] MPU6000_I2C_CallbackFunc(hi2c); 800424c: 687b ldr r3, [r7, #4] 800424e: 0018 movs r0, r3 8004250: f7fe ffcc bl 80031ec } 8004254: 46c0 nop @ (mov r8, r8) 8004256: 46bd mov sp, r7 8004258: b002 add sp, #8 800425a: bd80 pop {r7, pc} 0800425c : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 800425c: b580 push {r7, lr} 800425e: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 8004260: b672 cpsid i } 8004262: 46c0 nop @ (mov r8, r8) /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8004264: 46c0 nop @ (mov r8, r8) 8004266: e7fd b.n 8004264 08004268 : void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8004268: b580 push {r7, lr} 800426a: b082 sub sp, #8 800426c: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 800426e: 4b0f ldr r3, [pc, #60] @ (80042ac ) 8004270: 6c1a ldr r2, [r3, #64] @ 0x40 8004272: 4b0e ldr r3, [pc, #56] @ (80042ac ) 8004274: 2101 movs r1, #1 8004276: 430a orrs r2, r1 8004278: 641a str r2, [r3, #64] @ 0x40 800427a: 4b0c ldr r3, [pc, #48] @ (80042ac ) 800427c: 6c1b ldr r3, [r3, #64] @ 0x40 800427e: 2201 movs r2, #1 8004280: 4013 ands r3, r2 8004282: 607b str r3, [r7, #4] 8004284: 687b ldr r3, [r7, #4] __HAL_RCC_PWR_CLK_ENABLE(); 8004286: 4b09 ldr r3, [pc, #36] @ (80042ac ) 8004288: 6bda ldr r2, [r3, #60] @ 0x3c 800428a: 4b08 ldr r3, [pc, #32] @ (80042ac ) 800428c: 2180 movs r1, #128 @ 0x80 800428e: 0549 lsls r1, r1, #21 8004290: 430a orrs r2, r1 8004292: 63da str r2, [r3, #60] @ 0x3c 8004294: 4b05 ldr r3, [pc, #20] @ (80042ac ) 8004296: 6bda ldr r2, [r3, #60] @ 0x3c 8004298: 2380 movs r3, #128 @ 0x80 800429a: 055b lsls r3, r3, #21 800429c: 4013 ands r3, r2 800429e: 603b str r3, [r7, #0] 80042a0: 683b ldr r3, [r7, #0] /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 80042a2: 46c0 nop @ (mov r8, r8) 80042a4: 46bd mov sp, r7 80042a6: b002 add sp, #8 80042a8: bd80 pop {r7, pc} 80042aa: 46c0 nop @ (mov r8, r8) 80042ac: 40021000 .word 0x40021000 080042b0 : * This function configures the hardware resources used in this example * @param hi2c: I2C handle pointer * @retval None */ void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) { 80042b0: b590 push {r4, r7, lr} 80042b2: b095 sub sp, #84 @ 0x54 80042b4: af00 add r7, sp, #0 80042b6: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80042b8: 233c movs r3, #60 @ 0x3c 80042ba: 18fb adds r3, r7, r3 80042bc: 0018 movs r0, r3 80042be: 2314 movs r3, #20 80042c0: 001a movs r2, r3 80042c2: 2100 movs r1, #0 80042c4: f004 fe86 bl 8008fd4 RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 80042c8: 2414 movs r4, #20 80042ca: 193b adds r3, r7, r4 80042cc: 0018 movs r0, r3 80042ce: 2328 movs r3, #40 @ 0x28 80042d0: 001a movs r2, r3 80042d2: 2100 movs r1, #0 80042d4: f004 fe7e bl 8008fd4 if(hi2c->Instance==I2C1) 80042d8: 687b ldr r3, [r7, #4] 80042da: 681b ldr r3, [r3, #0] 80042dc: 4a27 ldr r2, [pc, #156] @ (800437c ) 80042de: 4293 cmp r3, r2 80042e0: d147 bne.n 8004372 /* USER CODE END I2C1_MspInit 0 */ /** Initializes the peripherals clocks */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C1; 80042e2: 193b adds r3, r7, r4 80042e4: 2220 movs r2, #32 80042e6: 601a str r2, [r3, #0] PeriphClkInit.I2c1ClockSelection = RCC_I2C1CLKSOURCE_HSI; 80042e8: 193b adds r3, r7, r4 80042ea: 2280 movs r2, #128 @ 0x80 80042ec: 0192 lsls r2, r2, #6 80042ee: 60da str r2, [r3, #12] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 80042f0: 193b adds r3, r7, r4 80042f2: 0018 movs r0, r3 80042f4: f003 fcbc bl 8007c70 80042f8: 1e03 subs r3, r0, #0 80042fa: d001 beq.n 8004300 { Error_Handler(); 80042fc: f7ff ffae bl 800425c } __HAL_RCC_GPIOB_CLK_ENABLE(); 8004300: 4b1f ldr r3, [pc, #124] @ (8004380 ) 8004302: 6b5a ldr r2, [r3, #52] @ 0x34 8004304: 4b1e ldr r3, [pc, #120] @ (8004380 ) 8004306: 2102 movs r1, #2 8004308: 430a orrs r2, r1 800430a: 635a str r2, [r3, #52] @ 0x34 800430c: 4b1c ldr r3, [pc, #112] @ (8004380 ) 800430e: 6b5b ldr r3, [r3, #52] @ 0x34 8004310: 2202 movs r2, #2 8004312: 4013 ands r3, r2 8004314: 613b str r3, [r7, #16] 8004316: 693b ldr r3, [r7, #16] /**I2C1 GPIO Configuration PB8 ------> I2C1_SCL PB9 ------> I2C1_SDA */ GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; 8004318: 213c movs r1, #60 @ 0x3c 800431a: 187b adds r3, r7, r1 800431c: 22c0 movs r2, #192 @ 0xc0 800431e: 0092 lsls r2, r2, #2 8004320: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; 8004322: 187b adds r3, r7, r1 8004324: 2212 movs r2, #18 8004326: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_PULLUP; 8004328: 187b adds r3, r7, r1 800432a: 2201 movs r2, #1 800432c: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800432e: 187b adds r3, r7, r1 8004330: 2200 movs r2, #0 8004332: 60da str r2, [r3, #12] GPIO_InitStruct.Alternate = GPIO_AF6_I2C1; 8004334: 187b adds r3, r7, r1 8004336: 2206 movs r2, #6 8004338: 611a str r2, [r3, #16] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800433a: 187b adds r3, r7, r1 800433c: 4a11 ldr r2, [pc, #68] @ (8004384 ) 800433e: 0019 movs r1, r3 8004340: 0010 movs r0, r2 8004342: f000 fb69 bl 8004a18 /* Peripheral clock enable */ __HAL_RCC_I2C1_CLK_ENABLE(); 8004346: 4b0e ldr r3, [pc, #56] @ (8004380 ) 8004348: 6bda ldr r2, [r3, #60] @ 0x3c 800434a: 4b0d ldr r3, [pc, #52] @ (8004380 ) 800434c: 2180 movs r1, #128 @ 0x80 800434e: 0389 lsls r1, r1, #14 8004350: 430a orrs r2, r1 8004352: 63da str r2, [r3, #60] @ 0x3c 8004354: 4b0a ldr r3, [pc, #40] @ (8004380 ) 8004356: 6bda ldr r2, [r3, #60] @ 0x3c 8004358: 2380 movs r3, #128 @ 0x80 800435a: 039b lsls r3, r3, #14 800435c: 4013 ands r3, r2 800435e: 60fb str r3, [r7, #12] 8004360: 68fb ldr r3, [r7, #12] /* I2C1 interrupt Init */ HAL_NVIC_SetPriority(I2C1_IRQn, 1, 0); 8004362: 2200 movs r2, #0 8004364: 2101 movs r1, #1 8004366: 2017 movs r0, #23 8004368: f000 faae bl 80048c8 HAL_NVIC_EnableIRQ(I2C1_IRQn); 800436c: 2017 movs r0, #23 800436e: f000 fac0 bl 80048f2 /* USER CODE BEGIN I2C1_MspInit 1 */ /* USER CODE END I2C1_MspInit 1 */ } } 8004372: 46c0 nop @ (mov r8, r8) 8004374: 46bd mov sp, r7 8004376: b015 add sp, #84 @ 0x54 8004378: bd90 pop {r4, r7, pc} 800437a: 46c0 nop @ (mov r8, r8) 800437c: 40005400 .word 0x40005400 8004380: 40021000 .word 0x40021000 8004384: 50000400 .word 0x50000400 08004388 : * This function configures the hardware resources used in this example * @param htim_base: TIM_Base handle pointer * @retval None */ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) { 8004388: b590 push {r4, r7, lr} 800438a: b08f sub sp, #60 @ 0x3c 800438c: af00 add r7, sp, #0 800438e: 6078 str r0, [r7, #4] RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 8004390: 2410 movs r4, #16 8004392: 193b adds r3, r7, r4 8004394: 0018 movs r0, r3 8004396: 2328 movs r3, #40 @ 0x28 8004398: 001a movs r2, r3 800439a: 2100 movs r1, #0 800439c: f004 fe1a bl 8008fd4 if(htim_base->Instance==TIM1) 80043a0: 687b ldr r3, [r7, #4] 80043a2: 681b ldr r3, [r3, #0] 80043a4: 4a1b ldr r2, [pc, #108] @ (8004414 ) 80043a6: 4293 cmp r3, r2 80043a8: d11d bne.n 80043e6 /* USER CODE END TIM1_MspInit 0 */ /** Initializes the peripherals clocks */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_TIM1; 80043aa: 193b adds r3, r7, r4 80043ac: 2280 movs r2, #128 @ 0x80 80043ae: 0392 lsls r2, r2, #14 80043b0: 601a str r2, [r3, #0] PeriphClkInit.Tim1ClockSelection = RCC_TIM1CLKSOURCE_PCLK1; 80043b2: 193b adds r3, r7, r4 80043b4: 2200 movs r2, #0 80043b6: 621a str r2, [r3, #32] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 80043b8: 193b adds r3, r7, r4 80043ba: 0018 movs r0, r3 80043bc: f003 fc58 bl 8007c70 80043c0: 1e03 subs r3, r0, #0 80043c2: d001 beq.n 80043c8 { Error_Handler(); 80043c4: f7ff ff4a bl 800425c } /* Peripheral clock enable */ __HAL_RCC_TIM1_CLK_ENABLE(); 80043c8: 4b13 ldr r3, [pc, #76] @ (8004418 ) 80043ca: 6c1a ldr r2, [r3, #64] @ 0x40 80043cc: 4b12 ldr r3, [pc, #72] @ (8004418 ) 80043ce: 2180 movs r1, #128 @ 0x80 80043d0: 0109 lsls r1, r1, #4 80043d2: 430a orrs r2, r1 80043d4: 641a str r2, [r3, #64] @ 0x40 80043d6: 4b10 ldr r3, [pc, #64] @ (8004418 ) 80043d8: 6c1a ldr r2, [r3, #64] @ 0x40 80043da: 2380 movs r3, #128 @ 0x80 80043dc: 011b lsls r3, r3, #4 80043de: 4013 ands r3, r2 80043e0: 60fb str r3, [r7, #12] 80043e2: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN TIM2_MspInit 1 */ /* USER CODE END TIM2_MspInit 1 */ } } 80043e4: e011 b.n 800440a else if(htim_base->Instance==TIM2) 80043e6: 687b ldr r3, [r7, #4] 80043e8: 681a ldr r2, [r3, #0] 80043ea: 2380 movs r3, #128 @ 0x80 80043ec: 05db lsls r3, r3, #23 80043ee: 429a cmp r2, r3 80043f0: d10b bne.n 800440a __HAL_RCC_TIM2_CLK_ENABLE(); 80043f2: 4b09 ldr r3, [pc, #36] @ (8004418 ) 80043f4: 6bda ldr r2, [r3, #60] @ 0x3c 80043f6: 4b08 ldr r3, [pc, #32] @ (8004418 ) 80043f8: 2101 movs r1, #1 80043fa: 430a orrs r2, r1 80043fc: 63da str r2, [r3, #60] @ 0x3c 80043fe: 4b06 ldr r3, [pc, #24] @ (8004418 ) 8004400: 6bdb ldr r3, [r3, #60] @ 0x3c 8004402: 2201 movs r2, #1 8004404: 4013 ands r3, r2 8004406: 60bb str r3, [r7, #8] 8004408: 68bb ldr r3, [r7, #8] } 800440a: 46c0 nop @ (mov r8, r8) 800440c: 46bd mov sp, r7 800440e: b00f add sp, #60 @ 0x3c 8004410: bd90 pop {r4, r7, pc} 8004412: 46c0 nop @ (mov r8, r8) 8004414: 40012c00 .word 0x40012c00 8004418: 40021000 .word 0x40021000 0800441c : void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) { 800441c: b590 push {r4, r7, lr} 800441e: b08b sub sp, #44 @ 0x2c 8004420: af00 add r7, sp, #0 8004422: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8004424: 2414 movs r4, #20 8004426: 193b adds r3, r7, r4 8004428: 0018 movs r0, r3 800442a: 2314 movs r3, #20 800442c: 001a movs r2, r3 800442e: 2100 movs r1, #0 8004430: f004 fdd0 bl 8008fd4 if(htim->Instance==TIM1) 8004434: 687b ldr r3, [r7, #4] 8004436: 681b ldr r3, [r3, #0] 8004438: 4a2a ldr r2, [pc, #168] @ (80044e4 ) 800443a: 4293 cmp r3, r2 800443c: d124 bne.n 8004488 { /* USER CODE BEGIN TIM1_MspPostInit 0 */ /* USER CODE END TIM1_MspPostInit 0 */ __HAL_RCC_GPIOA_CLK_ENABLE(); 800443e: 4b2a ldr r3, [pc, #168] @ (80044e8 ) 8004440: 6b5a ldr r2, [r3, #52] @ 0x34 8004442: 4b29 ldr r3, [pc, #164] @ (80044e8 ) 8004444: 2101 movs r1, #1 8004446: 430a orrs r2, r1 8004448: 635a str r2, [r3, #52] @ 0x34 800444a: 4b27 ldr r3, [pc, #156] @ (80044e8 ) 800444c: 6b5b ldr r3, [r3, #52] @ 0x34 800444e: 2201 movs r2, #1 8004450: 4013 ands r3, r2 8004452: 613b str r3, [r7, #16] 8004454: 693b ldr r3, [r7, #16] /**TIM1 GPIO Configuration PA8 ------> TIM1_CH1 PA11 [PA9] ------> TIM1_CH4 */ GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_11; 8004456: 193b adds r3, r7, r4 8004458: 2290 movs r2, #144 @ 0x90 800445a: 0112 lsls r2, r2, #4 800445c: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800445e: 0021 movs r1, r4 8004460: 187b adds r3, r7, r1 8004462: 2202 movs r2, #2 8004464: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 8004466: 187b adds r3, r7, r1 8004468: 2200 movs r2, #0 800446a: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800446c: 187b adds r3, r7, r1 800446e: 2200 movs r2, #0 8004470: 60da str r2, [r3, #12] GPIO_InitStruct.Alternate = GPIO_AF2_TIM1; 8004472: 187b adds r3, r7, r1 8004474: 2202 movs r2, #2 8004476: 611a str r2, [r3, #16] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8004478: 187a adds r2, r7, r1 800447a: 23a0 movs r3, #160 @ 0xa0 800447c: 05db lsls r3, r3, #23 800447e: 0011 movs r1, r2 8004480: 0018 movs r0, r3 8004482: f000 fac9 bl 8004a18 /* USER CODE BEGIN TIM2_MspPostInit 1 */ /* USER CODE END TIM2_MspPostInit 1 */ } } 8004486: e028 b.n 80044da else if(htim->Instance==TIM2) 8004488: 687b ldr r3, [r7, #4] 800448a: 681a ldr r2, [r3, #0] 800448c: 2380 movs r3, #128 @ 0x80 800448e: 05db lsls r3, r3, #23 8004490: 429a cmp r2, r3 8004492: d122 bne.n 80044da __HAL_RCC_GPIOA_CLK_ENABLE(); 8004494: 4b14 ldr r3, [pc, #80] @ (80044e8 ) 8004496: 6b5a ldr r2, [r3, #52] @ 0x34 8004498: 4b13 ldr r3, [pc, #76] @ (80044e8 ) 800449a: 2101 movs r1, #1 800449c: 430a orrs r2, r1 800449e: 635a str r2, [r3, #52] @ 0x34 80044a0: 4b11 ldr r3, [pc, #68] @ (80044e8 ) 80044a2: 6b5b ldr r3, [r3, #52] @ 0x34 80044a4: 2201 movs r2, #1 80044a6: 4013 ands r3, r2 80044a8: 60fb str r3, [r7, #12] 80044aa: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3; 80044ac: 2114 movs r1, #20 80044ae: 187b adds r3, r7, r1 80044b0: 220f movs r2, #15 80044b2: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80044b4: 187b adds r3, r7, r1 80044b6: 2202 movs r2, #2 80044b8: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 80044ba: 187b adds r3, r7, r1 80044bc: 2200 movs r2, #0 80044be: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80044c0: 187b adds r3, r7, r1 80044c2: 2200 movs r2, #0 80044c4: 60da str r2, [r3, #12] GPIO_InitStruct.Alternate = GPIO_AF2_TIM2; 80044c6: 187b adds r3, r7, r1 80044c8: 2202 movs r2, #2 80044ca: 611a str r2, [r3, #16] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80044cc: 187a adds r2, r7, r1 80044ce: 23a0 movs r3, #160 @ 0xa0 80044d0: 05db lsls r3, r3, #23 80044d2: 0011 movs r1, r2 80044d4: 0018 movs r0, r3 80044d6: f000 fa9f bl 8004a18 } 80044da: 46c0 nop @ (mov r8, r8) 80044dc: 46bd mov sp, r7 80044de: b00b add sp, #44 @ 0x2c 80044e0: bd90 pop {r4, r7, pc} 80044e2: 46c0 nop @ (mov r8, r8) 80044e4: 40012c00 .word 0x40012c00 80044e8: 40021000 .word 0x40021000 080044ec : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 80044ec: b580 push {r7, lr} 80044ee: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 80044f0: 46c0 nop @ (mov r8, r8) 80044f2: e7fd b.n 80044f0 080044f4 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 80044f4: b580 push {r7, lr} 80044f6: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 80044f8: 46c0 nop @ (mov r8, r8) 80044fa: e7fd b.n 80044f8 080044fc : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 80044fc: b580 push {r7, lr} 80044fe: af00 add r7, sp, #0 /* USER CODE END SVC_IRQn 0 */ /* USER CODE BEGIN SVC_IRQn 1 */ /* USER CODE END SVC_IRQn 1 */ } 8004500: 46c0 nop @ (mov r8, r8) 8004502: 46bd mov sp, r7 8004504: bd80 pop {r7, pc} 08004506 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8004506: b580 push {r7, lr} 8004508: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 800450a: 46c0 nop @ (mov r8, r8) 800450c: 46bd mov sp, r7 800450e: bd80 pop {r7, pc} 08004510 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 8004510: b580 push {r7, lr} 8004512: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 8004514: f000 f8ec bl 80046f0 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 8004518: 46c0 nop @ (mov r8, r8) 800451a: 46bd mov sp, r7 800451c: bd80 pop {r7, pc} ... 08004520 : /** * @brief This function handles I2C1 event global interrupt / I2C1 wake-up interrupt through EXTI line 23. */ void I2C1_IRQHandler(void) { 8004520: b580 push {r7, lr} 8004522: af00 add r7, sp, #0 /* USER CODE BEGIN I2C1_IRQn 0 */ /* USER CODE END I2C1_IRQn 0 */ if (hi2c1.Instance->ISR & (I2C_FLAG_BERR | I2C_FLAG_ARLO | I2C_FLAG_OVR)) { 8004524: 4b09 ldr r3, [pc, #36] @ (800454c ) 8004526: 681b ldr r3, [r3, #0] 8004528: 699a ldr r2, [r3, #24] 800452a: 23e0 movs r3, #224 @ 0xe0 800452c: 00db lsls r3, r3, #3 800452e: 4013 ands r3, r2 8004530: d004 beq.n 800453c HAL_I2C_ER_IRQHandler(&hi2c1); 8004532: 4b06 ldr r3, [pc, #24] @ (800454c ) 8004534: 0018 movs r0, r3 8004536: f000 ff79 bl 800542c HAL_I2C_EV_IRQHandler(&hi2c1); } /* USER CODE BEGIN I2C1_IRQn 1 */ /* USER CODE END I2C1_IRQn 1 */ } 800453a: e003 b.n 8004544 HAL_I2C_EV_IRQHandler(&hi2c1); 800453c: 4b03 ldr r3, [pc, #12] @ (800454c ) 800453e: 0018 movs r0, r3 8004540: f000 ff5a bl 80053f8 } 8004544: 46c0 nop @ (mov r8, r8) 8004546: 46bd mov sp, r7 8004548: bd80 pop {r7, pc} 800454a: 46c0 nop @ (mov r8, r8) 800454c: 20000900 .word 0x20000900 08004550 <_sbrk>: * * @param incr Memory size * @return Pointer to allocated memory */ void *_sbrk(ptrdiff_t incr) { 8004550: b580 push {r7, lr} 8004552: b086 sub sp, #24 8004554: af00 add r7, sp, #0 8004556: 6078 str r0, [r7, #4] extern uint8_t _end; /* Symbol defined in the linker script */ extern uint8_t _estack; /* Symbol defined in the linker script */ extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; 8004558: 4a14 ldr r2, [pc, #80] @ (80045ac <_sbrk+0x5c>) 800455a: 4b15 ldr r3, [pc, #84] @ (80045b0 <_sbrk+0x60>) 800455c: 1ad3 subs r3, r2, r3 800455e: 617b str r3, [r7, #20] const uint8_t *max_heap = (uint8_t *)stack_limit; 8004560: 697b ldr r3, [r7, #20] 8004562: 613b str r3, [r7, #16] uint8_t *prev_heap_end; /* Initialize heap end at first call */ if (NULL == __sbrk_heap_end) 8004564: 4b13 ldr r3, [pc, #76] @ (80045b4 <_sbrk+0x64>) 8004566: 681b ldr r3, [r3, #0] 8004568: 2b00 cmp r3, #0 800456a: d102 bne.n 8004572 <_sbrk+0x22> { __sbrk_heap_end = &_end; 800456c: 4b11 ldr r3, [pc, #68] @ (80045b4 <_sbrk+0x64>) 800456e: 4a12 ldr r2, [pc, #72] @ (80045b8 <_sbrk+0x68>) 8004570: 601a str r2, [r3, #0] } /* Protect heap from growing into the reserved MSP stack */ if (__sbrk_heap_end + incr > max_heap) 8004572: 4b10 ldr r3, [pc, #64] @ (80045b4 <_sbrk+0x64>) 8004574: 681a ldr r2, [r3, #0] 8004576: 687b ldr r3, [r7, #4] 8004578: 18d3 adds r3, r2, r3 800457a: 693a ldr r2, [r7, #16] 800457c: 429a cmp r2, r3 800457e: d207 bcs.n 8004590 <_sbrk+0x40> { errno = ENOMEM; 8004580: f004 fd42 bl 8009008 <__errno> 8004584: 0003 movs r3, r0 8004586: 220c movs r2, #12 8004588: 601a str r2, [r3, #0] return (void *)-1; 800458a: 2301 movs r3, #1 800458c: 425b negs r3, r3 800458e: e009 b.n 80045a4 <_sbrk+0x54> } prev_heap_end = __sbrk_heap_end; 8004590: 4b08 ldr r3, [pc, #32] @ (80045b4 <_sbrk+0x64>) 8004592: 681b ldr r3, [r3, #0] 8004594: 60fb str r3, [r7, #12] __sbrk_heap_end += incr; 8004596: 4b07 ldr r3, [pc, #28] @ (80045b4 <_sbrk+0x64>) 8004598: 681a ldr r2, [r3, #0] 800459a: 687b ldr r3, [r7, #4] 800459c: 18d2 adds r2, r2, r3 800459e: 4b05 ldr r3, [pc, #20] @ (80045b4 <_sbrk+0x64>) 80045a0: 601a str r2, [r3, #0] return (void *)prev_heap_end; 80045a2: 68fb ldr r3, [r7, #12] } 80045a4: 0018 movs r0, r3 80045a6: 46bd mov sp, r7 80045a8: b006 add sp, #24 80045aa: bd80 pop {r7, pc} 80045ac: 20002000 .word 0x20002000 80045b0: 00000400 .word 0x00000400 80045b4: 200009ec .word 0x200009ec 80045b8: 20000b40 .word 0x20000b40 080045bc : * @brief Setup the microcontroller system. * @param None * @retval None */ void SystemInit(void) { 80045bc: b580 push {r7, lr} 80045be: af00 add r7, sp, #0 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation */ #endif /* USER_VECT_TAB_ADDRESS */ } 80045c0: 46c0 nop @ (mov r8, r8) 80045c2: 46bd mov sp, r7 80045c4: bd80 pop {r7, pc} ... 080045c8 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr r0, =_estack 80045c8: 480d ldr r0, [pc, #52] @ (8004600 ) mov sp, r0 /* set stack pointer */ 80045ca: 4685 mov sp, r0 /* Call the clock system initialization function.*/ bl SystemInit 80045cc: f7ff fff6 bl 80045bc /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 80045d0: 480c ldr r0, [pc, #48] @ (8004604 ) ldr r1, =_edata 80045d2: 490d ldr r1, [pc, #52] @ (8004608 ) ldr r2, =_sidata 80045d4: 4a0d ldr r2, [pc, #52] @ (800460c ) movs r3, #0 80045d6: 2300 movs r3, #0 b LoopCopyDataInit 80045d8: e002 b.n 80045e0 080045da : CopyDataInit: ldr r4, [r2, r3] 80045da: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 80045dc: 50c4 str r4, [r0, r3] adds r3, r3, #4 80045de: 3304 adds r3, #4 080045e0 : LoopCopyDataInit: adds r4, r0, r3 80045e0: 18c4 adds r4, r0, r3 cmp r4, r1 80045e2: 428c cmp r4, r1 bcc CopyDataInit 80045e4: d3f9 bcc.n 80045da /* Zero fill the bss segment. */ ldr r2, =_sbss 80045e6: 4a0a ldr r2, [pc, #40] @ (8004610 ) ldr r4, =_ebss 80045e8: 4c0a ldr r4, [pc, #40] @ (8004614 ) movs r3, #0 80045ea: 2300 movs r3, #0 b LoopFillZerobss 80045ec: e001 b.n 80045f2 080045ee : FillZerobss: str r3, [r2] 80045ee: 6013 str r3, [r2, #0] adds r2, r2, #4 80045f0: 3204 adds r2, #4 080045f2 : LoopFillZerobss: cmp r2, r4 80045f2: 42a2 cmp r2, r4 bcc FillZerobss 80045f4: d3fb bcc.n 80045ee /* Call static constructors */ bl __libc_init_array 80045f6: f004 fd0d bl 8009014 <__libc_init_array> /* Call the application s entry point.*/ bl main 80045fa: f7ff fb8d bl 8003d18
080045fe : LoopForever: b LoopForever 80045fe: e7fe b.n 80045fe ldr r0, =_estack 8004600: 20002000 .word 0x20002000 ldr r0, =_sdata 8004604: 20000000 .word 0x20000000 ldr r1, =_edata 8004608: 20000070 .word 0x20000070 ldr r2, =_sidata 800460c: 08009fe8 .word 0x08009fe8 ldr r2, =_sbss 8004610: 20000070 .word 0x20000070 ldr r4, =_ebss 8004614: 20000b3c .word 0x20000b3c 08004618 : * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8004618: e7fe b.n 8004618 ... 0800461c : * each 1ms in the SysTick_Handler() interrupt handler. * * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 800461c: b580 push {r7, lr} 800461e: b082 sub sp, #8 8004620: af00 add r7, sp, #0 HAL_StatusTypeDef status = HAL_OK; 8004622: 1dfb adds r3, r7, #7 8004624: 2200 movs r2, #0 8004626: 701a strb r2, [r3, #0] #if (INSTRUCTION_CACHE_ENABLE == 0U) __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); #endif /* INSTRUCTION_CACHE_ENABLE */ #if (PREFETCH_ENABLE != 0U) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 8004628: 4b0b ldr r3, [pc, #44] @ (8004658 ) 800462a: 681a ldr r2, [r3, #0] 800462c: 4b0a ldr r3, [pc, #40] @ (8004658 ) 800462e: 2180 movs r1, #128 @ 0x80 8004630: 0049 lsls r1, r1, #1 8004632: 430a orrs r2, r1 8004634: 601a str r2, [r3, #0] #endif /* PREFETCH_ENABLE */ /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is HSI) */ if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) 8004636: 2003 movs r0, #3 8004638: f000 f810 bl 800465c 800463c: 1e03 subs r3, r0, #0 800463e: d003 beq.n 8004648 { status = HAL_ERROR; 8004640: 1dfb adds r3, r7, #7 8004642: 2201 movs r2, #1 8004644: 701a strb r2, [r3, #0] 8004646: e001 b.n 800464c } else { /* Init the low level hardware */ HAL_MspInit(); 8004648: f7ff fe0e bl 8004268 } /* Return function status */ return status; 800464c: 1dfb adds r3, r7, #7 800464e: 781b ldrb r3, [r3, #0] } 8004650: 0018 movs r0, r3 8004652: 46bd mov sp, r7 8004654: b002 add sp, #8 8004656: bd80 pop {r7, pc} 8004658: 40022000 .word 0x40022000 0800465c : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 800465c: b590 push {r4, r7, lr} 800465e: b085 sub sp, #20 8004660: af00 add r7, sp, #0 8004662: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8004664: 230f movs r3, #15 8004666: 18fb adds r3, r7, r3 8004668: 2200 movs r2, #0 800466a: 701a strb r2, [r3, #0] /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that doesn't take the value zero)*/ if ((uint32_t)uwTickFreq != 0U) 800466c: 4b1d ldr r3, [pc, #116] @ (80046e4 ) 800466e: 781b ldrb r3, [r3, #0] 8004670: 2b00 cmp r3, #0 8004672: d02b beq.n 80046cc { /*Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U /(uint32_t)uwTickFreq)) == 0U) 8004674: 4b1c ldr r3, [pc, #112] @ (80046e8 ) 8004676: 681c ldr r4, [r3, #0] 8004678: 4b1a ldr r3, [pc, #104] @ (80046e4 ) 800467a: 781b ldrb r3, [r3, #0] 800467c: 0019 movs r1, r3 800467e: 23fa movs r3, #250 @ 0xfa 8004680: 0098 lsls r0, r3, #2 8004682: f7fb fd3f bl 8000104 <__udivsi3> 8004686: 0003 movs r3, r0 8004688: 0019 movs r1, r3 800468a: 0020 movs r0, r4 800468c: f7fb fd3a bl 8000104 <__udivsi3> 8004690: 0003 movs r3, r0 8004692: 0018 movs r0, r3 8004694: f000 f93d bl 8004912 8004698: 1e03 subs r3, r0, #0 800469a: d112 bne.n 80046c2 { /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 800469c: 687b ldr r3, [r7, #4] 800469e: 2b03 cmp r3, #3 80046a0: d80a bhi.n 80046b8 { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 80046a2: 6879 ldr r1, [r7, #4] 80046a4: 2301 movs r3, #1 80046a6: 425b negs r3, r3 80046a8: 2200 movs r2, #0 80046aa: 0018 movs r0, r3 80046ac: f000 f90c bl 80048c8 uwTickPrio = TickPriority; 80046b0: 4b0e ldr r3, [pc, #56] @ (80046ec ) 80046b2: 687a ldr r2, [r7, #4] 80046b4: 601a str r2, [r3, #0] 80046b6: e00d b.n 80046d4 } else { status = HAL_ERROR; 80046b8: 230f movs r3, #15 80046ba: 18fb adds r3, r7, r3 80046bc: 2201 movs r2, #1 80046be: 701a strb r2, [r3, #0] 80046c0: e008 b.n 80046d4 } } else { status = HAL_ERROR; 80046c2: 230f movs r3, #15 80046c4: 18fb adds r3, r7, r3 80046c6: 2201 movs r2, #1 80046c8: 701a strb r2, [r3, #0] 80046ca: e003 b.n 80046d4 } } else { status = HAL_ERROR; 80046cc: 230f movs r3, #15 80046ce: 18fb adds r3, r7, r3 80046d0: 2201 movs r2, #1 80046d2: 701a strb r2, [r3, #0] } /* Return function status */ return status; 80046d4: 230f movs r3, #15 80046d6: 18fb adds r3, r7, r3 80046d8: 781b ldrb r3, [r3, #0] } 80046da: 0018 movs r0, r3 80046dc: 46bd mov sp, r7 80046de: b005 add sp, #20 80046e0: bd90 pop {r4, r7, pc} 80046e2: 46c0 nop @ (mov r8, r8) 80046e4: 20000008 .word 0x20000008 80046e8: 20000000 .word 0x20000000 80046ec: 20000004 .word 0x20000004 080046f0 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 80046f0: b580 push {r7, lr} 80046f2: af00 add r7, sp, #0 uwTick += (uint32_t)uwTickFreq; 80046f4: 4b05 ldr r3, [pc, #20] @ (800470c ) 80046f6: 781b ldrb r3, [r3, #0] 80046f8: 001a movs r2, r3 80046fa: 4b05 ldr r3, [pc, #20] @ (8004710 ) 80046fc: 681b ldr r3, [r3, #0] 80046fe: 18d2 adds r2, r2, r3 8004700: 4b03 ldr r3, [pc, #12] @ (8004710 ) 8004702: 601a str r2, [r3, #0] } 8004704: 46c0 nop @ (mov r8, r8) 8004706: 46bd mov sp, r7 8004708: bd80 pop {r7, pc} 800470a: 46c0 nop @ (mov r8, r8) 800470c: 20000008 .word 0x20000008 8004710: 200009f0 .word 0x200009f0 08004714 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8004714: b580 push {r7, lr} 8004716: af00 add r7, sp, #0 return uwTick; 8004718: 4b02 ldr r3, [pc, #8] @ (8004724 ) 800471a: 681b ldr r3, [r3, #0] } 800471c: 0018 movs r0, r3 800471e: 46bd mov sp, r7 8004720: bd80 pop {r7, pc} 8004722: 46c0 nop @ (mov r8, r8) 8004724: 200009f0 .word 0x200009f0 08004728 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 8004728: b580 push {r7, lr} 800472a: b084 sub sp, #16 800472c: af00 add r7, sp, #0 800472e: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 8004730: f7ff fff0 bl 8004714 8004734: 0003 movs r3, r0 8004736: 60bb str r3, [r7, #8] uint32_t wait = Delay; 8004738: 687b ldr r3, [r7, #4] 800473a: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 800473c: 68fb ldr r3, [r7, #12] 800473e: 3301 adds r3, #1 8004740: d005 beq.n 800474e { wait += (uint32_t)(uwTickFreq); 8004742: 4b0a ldr r3, [pc, #40] @ (800476c ) 8004744: 781b ldrb r3, [r3, #0] 8004746: 001a movs r2, r3 8004748: 68fb ldr r3, [r7, #12] 800474a: 189b adds r3, r3, r2 800474c: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) 800474e: 46c0 nop @ (mov r8, r8) 8004750: f7ff ffe0 bl 8004714 8004754: 0002 movs r2, r0 8004756: 68bb ldr r3, [r7, #8] 8004758: 1ad3 subs r3, r2, r3 800475a: 68fa ldr r2, [r7, #12] 800475c: 429a cmp r2, r3 800475e: d8f7 bhi.n 8004750 { } } 8004760: 46c0 nop @ (mov r8, r8) 8004762: 46c0 nop @ (mov r8, r8) 8004764: 46bd mov sp, r7 8004766: b004 add sp, #16 8004768: bd80 pop {r7, pc} 800476a: 46c0 nop @ (mov r8, r8) 800476c: 20000008 .word 0x20000008 08004770 <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { 8004770: b580 push {r7, lr} 8004772: b082 sub sp, #8 8004774: af00 add r7, sp, #0 8004776: 0002 movs r2, r0 8004778: 1dfb adds r3, r7, #7 800477a: 701a strb r2, [r3, #0] if ((int32_t)(IRQn) >= 0) 800477c: 1dfb adds r3, r7, #7 800477e: 781b ldrb r3, [r3, #0] 8004780: 2b7f cmp r3, #127 @ 0x7f 8004782: d809 bhi.n 8004798 <__NVIC_EnableIRQ+0x28> { __COMPILER_BARRIER(); NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8004784: 1dfb adds r3, r7, #7 8004786: 781b ldrb r3, [r3, #0] 8004788: 001a movs r2, r3 800478a: 231f movs r3, #31 800478c: 401a ands r2, r3 800478e: 4b04 ldr r3, [pc, #16] @ (80047a0 <__NVIC_EnableIRQ+0x30>) 8004790: 2101 movs r1, #1 8004792: 4091 lsls r1, r2 8004794: 000a movs r2, r1 8004796: 601a str r2, [r3, #0] __COMPILER_BARRIER(); } } 8004798: 46c0 nop @ (mov r8, r8) 800479a: 46bd mov sp, r7 800479c: b002 add sp, #8 800479e: bd80 pop {r7, pc} 80047a0: e000e100 .word 0xe000e100 080047a4 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 80047a4: b590 push {r4, r7, lr} 80047a6: b083 sub sp, #12 80047a8: af00 add r7, sp, #0 80047aa: 0002 movs r2, r0 80047ac: 6039 str r1, [r7, #0] 80047ae: 1dfb adds r3, r7, #7 80047b0: 701a strb r2, [r3, #0] if ((int32_t)(IRQn) >= 0) 80047b2: 1dfb adds r3, r7, #7 80047b4: 781b ldrb r3, [r3, #0] 80047b6: 2b7f cmp r3, #127 @ 0x7f 80047b8: d828 bhi.n 800480c <__NVIC_SetPriority+0x68> { NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 80047ba: 4a2f ldr r2, [pc, #188] @ (8004878 <__NVIC_SetPriority+0xd4>) 80047bc: 1dfb adds r3, r7, #7 80047be: 781b ldrb r3, [r3, #0] 80047c0: b25b sxtb r3, r3 80047c2: 089b lsrs r3, r3, #2 80047c4: 33c0 adds r3, #192 @ 0xc0 80047c6: 009b lsls r3, r3, #2 80047c8: 589b ldr r3, [r3, r2] 80047ca: 1dfa adds r2, r7, #7 80047cc: 7812 ldrb r2, [r2, #0] 80047ce: 0011 movs r1, r2 80047d0: 2203 movs r2, #3 80047d2: 400a ands r2, r1 80047d4: 00d2 lsls r2, r2, #3 80047d6: 21ff movs r1, #255 @ 0xff 80047d8: 4091 lsls r1, r2 80047da: 000a movs r2, r1 80047dc: 43d2 mvns r2, r2 80047de: 401a ands r2, r3 80047e0: 0011 movs r1, r2 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 80047e2: 683b ldr r3, [r7, #0] 80047e4: 019b lsls r3, r3, #6 80047e6: 22ff movs r2, #255 @ 0xff 80047e8: 401a ands r2, r3 80047ea: 1dfb adds r3, r7, #7 80047ec: 781b ldrb r3, [r3, #0] 80047ee: 0018 movs r0, r3 80047f0: 2303 movs r3, #3 80047f2: 4003 ands r3, r0 80047f4: 00db lsls r3, r3, #3 80047f6: 409a lsls r2, r3 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 80047f8: 481f ldr r0, [pc, #124] @ (8004878 <__NVIC_SetPriority+0xd4>) 80047fa: 1dfb adds r3, r7, #7 80047fc: 781b ldrb r3, [r3, #0] 80047fe: b25b sxtb r3, r3 8004800: 089b lsrs r3, r3, #2 8004802: 430a orrs r2, r1 8004804: 33c0 adds r3, #192 @ 0xc0 8004806: 009b lsls r3, r3, #2 8004808: 501a str r2, [r3, r0] else { SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } 800480a: e031 b.n 8004870 <__NVIC_SetPriority+0xcc> SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 800480c: 4a1b ldr r2, [pc, #108] @ (800487c <__NVIC_SetPriority+0xd8>) 800480e: 1dfb adds r3, r7, #7 8004810: 781b ldrb r3, [r3, #0] 8004812: 0019 movs r1, r3 8004814: 230f movs r3, #15 8004816: 400b ands r3, r1 8004818: 3b08 subs r3, #8 800481a: 089b lsrs r3, r3, #2 800481c: 3306 adds r3, #6 800481e: 009b lsls r3, r3, #2 8004820: 18d3 adds r3, r2, r3 8004822: 3304 adds r3, #4 8004824: 681b ldr r3, [r3, #0] 8004826: 1dfa adds r2, r7, #7 8004828: 7812 ldrb r2, [r2, #0] 800482a: 0011 movs r1, r2 800482c: 2203 movs r2, #3 800482e: 400a ands r2, r1 8004830: 00d2 lsls r2, r2, #3 8004832: 21ff movs r1, #255 @ 0xff 8004834: 4091 lsls r1, r2 8004836: 000a movs r2, r1 8004838: 43d2 mvns r2, r2 800483a: 401a ands r2, r3 800483c: 0011 movs r1, r2 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 800483e: 683b ldr r3, [r7, #0] 8004840: 019b lsls r3, r3, #6 8004842: 22ff movs r2, #255 @ 0xff 8004844: 401a ands r2, r3 8004846: 1dfb adds r3, r7, #7 8004848: 781b ldrb r3, [r3, #0] 800484a: 0018 movs r0, r3 800484c: 2303 movs r3, #3 800484e: 4003 ands r3, r0 8004850: 00db lsls r3, r3, #3 8004852: 409a lsls r2, r3 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 8004854: 4809 ldr r0, [pc, #36] @ (800487c <__NVIC_SetPriority+0xd8>) 8004856: 1dfb adds r3, r7, #7 8004858: 781b ldrb r3, [r3, #0] 800485a: 001c movs r4, r3 800485c: 230f movs r3, #15 800485e: 4023 ands r3, r4 8004860: 3b08 subs r3, #8 8004862: 089b lsrs r3, r3, #2 8004864: 430a orrs r2, r1 8004866: 3306 adds r3, #6 8004868: 009b lsls r3, r3, #2 800486a: 18c3 adds r3, r0, r3 800486c: 3304 adds r3, #4 800486e: 601a str r2, [r3, #0] } 8004870: 46c0 nop @ (mov r8, r8) 8004872: 46bd mov sp, r7 8004874: b003 add sp, #12 8004876: bd90 pop {r4, r7, pc} 8004878: e000e100 .word 0xe000e100 800487c: e000ed00 .word 0xe000ed00 08004880 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 8004880: b580 push {r7, lr} 8004882: b082 sub sp, #8 8004884: af00 add r7, sp, #0 8004886: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8004888: 687b ldr r3, [r7, #4] 800488a: 1e5a subs r2, r3, #1 800488c: 2380 movs r3, #128 @ 0x80 800488e: 045b lsls r3, r3, #17 8004890: 429a cmp r2, r3 8004892: d301 bcc.n 8004898 { return (1UL); /* Reload value impossible */ 8004894: 2301 movs r3, #1 8004896: e010 b.n 80048ba } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8004898: 4b0a ldr r3, [pc, #40] @ (80048c4 ) 800489a: 687a ldr r2, [r7, #4] 800489c: 3a01 subs r2, #1 800489e: 605a str r2, [r3, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 80048a0: 2301 movs r3, #1 80048a2: 425b negs r3, r3 80048a4: 2103 movs r1, #3 80048a6: 0018 movs r0, r3 80048a8: f7ff ff7c bl 80047a4 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 80048ac: 4b05 ldr r3, [pc, #20] @ (80048c4 ) 80048ae: 2200 movs r2, #0 80048b0: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 80048b2: 4b04 ldr r3, [pc, #16] @ (80048c4 ) 80048b4: 2207 movs r2, #7 80048b6: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 80048b8: 2300 movs r3, #0 } 80048ba: 0018 movs r0, r3 80048bc: 46bd mov sp, r7 80048be: b002 add sp, #8 80048c0: bd80 pop {r7, pc} 80048c2: 46c0 nop @ (mov r8, r8) 80048c4: e000e010 .word 0xe000e010 080048c8 : * with stm32g0xx devices, this parameter is a dummy value and it is ignored, because * no subpriority supported in Cortex M0+ based products. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 80048c8: b580 push {r7, lr} 80048ca: b084 sub sp, #16 80048cc: af00 add r7, sp, #0 80048ce: 60b9 str r1, [r7, #8] 80048d0: 607a str r2, [r7, #4] 80048d2: 210f movs r1, #15 80048d4: 187b adds r3, r7, r1 80048d6: 1c02 adds r2, r0, #0 80048d8: 701a strb r2, [r3, #0] /* Prevent unused argument(s) compilation warning */ UNUSED(SubPriority); /* Check the parameters */ assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); NVIC_SetPriority(IRQn, PreemptPriority); 80048da: 68ba ldr r2, [r7, #8] 80048dc: 187b adds r3, r7, r1 80048de: 781b ldrb r3, [r3, #0] 80048e0: b25b sxtb r3, r3 80048e2: 0011 movs r1, r2 80048e4: 0018 movs r0, r3 80048e6: f7ff ff5d bl 80047a4 <__NVIC_SetPriority> } 80048ea: 46c0 nop @ (mov r8, r8) 80048ec: 46bd mov sp, r7 80048ee: b004 add sp, #16 80048f0: bd80 pop {r7, pc} 080048f2 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g0xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 80048f2: b580 push {r7, lr} 80048f4: b082 sub sp, #8 80048f6: af00 add r7, sp, #0 80048f8: 0002 movs r2, r0 80048fa: 1dfb adds r3, r7, #7 80048fc: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 80048fe: 1dfb adds r3, r7, #7 8004900: 781b ldrb r3, [r3, #0] 8004902: b25b sxtb r3, r3 8004904: 0018 movs r0, r3 8004906: f7ff ff33 bl 8004770 <__NVIC_EnableIRQ> } 800490a: 46c0 nop @ (mov r8, r8) 800490c: 46bd mov sp, r7 800490e: b002 add sp, #8 8004910: bd80 pop {r7, pc} 08004912 : * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 8004912: b580 push {r7, lr} 8004914: b082 sub sp, #8 8004916: af00 add r7, sp, #0 8004918: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 800491a: 687b ldr r3, [r7, #4] 800491c: 0018 movs r0, r3 800491e: f7ff ffaf bl 8004880 8004922: 0003 movs r3, r0 } 8004924: 0018 movs r0, r3 8004926: 46bd mov sp, r7 8004928: b002 add sp, #8 800492a: bd80 pop {r7, pc} 0800492c : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 800492c: b580 push {r7, lr} 800492e: b084 sub sp, #16 8004930: af00 add r7, sp, #0 8004932: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8004934: 210f movs r1, #15 8004936: 187b adds r3, r7, r1 8004938: 2200 movs r2, #0 800493a: 701a strb r2, [r3, #0] if (hdma->State != HAL_DMA_STATE_BUSY) 800493c: 687b ldr r3, [r7, #4] 800493e: 2225 movs r2, #37 @ 0x25 8004940: 5c9b ldrb r3, [r3, r2] 8004942: b2db uxtb r3, r3 8004944: 2b02 cmp r3, #2 8004946: d006 beq.n 8004956 { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8004948: 687b ldr r3, [r7, #4] 800494a: 2204 movs r2, #4 800494c: 63da str r2, [r3, #60] @ 0x3c status = HAL_ERROR; 800494e: 187b adds r3, r7, r1 8004950: 2201 movs r2, #1 8004952: 701a strb r2, [r3, #0] 8004954: e049 b.n 80049ea } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8004956: 687b ldr r3, [r7, #4] 8004958: 681b ldr r3, [r3, #0] 800495a: 681a ldr r2, [r3, #0] 800495c: 687b ldr r3, [r7, #4] 800495e: 681b ldr r3, [r3, #0] 8004960: 210e movs r1, #14 8004962: 438a bics r2, r1 8004964: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 8004966: 687b ldr r3, [r7, #4] 8004968: 681b ldr r3, [r3, #0] 800496a: 681a ldr r2, [r3, #0] 800496c: 687b ldr r3, [r7, #4] 800496e: 681b ldr r3, [r3, #0] 8004970: 2101 movs r1, #1 8004972: 438a bics r2, r1 8004974: 601a str r2, [r3, #0] /* disable the DMAMUX sync overrun IT*/ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 8004976: 687b ldr r3, [r7, #4] 8004978: 6c5b ldr r3, [r3, #68] @ 0x44 800497a: 681a ldr r2, [r3, #0] 800497c: 687b ldr r3, [r7, #4] 800497e: 6c5b ldr r3, [r3, #68] @ 0x44 8004980: 491d ldr r1, [pc, #116] @ (80049f8 ) 8004982: 400a ands r2, r1 8004984: 601a str r2, [r3, #0] /* Clear all flags */ #if defined(DMA2) hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); #else __HAL_DMA_CLEAR_FLAG(hdma, ((DMA_FLAG_GI1) << (hdma->ChannelIndex & 0x1CU))); 8004986: 4b1d ldr r3, [pc, #116] @ (80049fc ) 8004988: 6859 ldr r1, [r3, #4] 800498a: 687b ldr r3, [r7, #4] 800498c: 6c1b ldr r3, [r3, #64] @ 0x40 800498e: 221c movs r2, #28 8004990: 4013 ands r3, r2 8004992: 2201 movs r2, #1 8004994: 409a lsls r2, r3 8004996: 4b19 ldr r3, [pc, #100] @ (80049fc ) 8004998: 430a orrs r2, r1 800499a: 605a str r2, [r3, #4] #endif /* DMA2 */ /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 800499c: 687b ldr r3, [r7, #4] 800499e: 6c9b ldr r3, [r3, #72] @ 0x48 80049a0: 687a ldr r2, [r7, #4] 80049a2: 6cd2 ldr r2, [r2, #76] @ 0x4c 80049a4: 605a str r2, [r3, #4] if (hdma->DMAmuxRequestGen != 0U) 80049a6: 687b ldr r3, [r7, #4] 80049a8: 6d1b ldr r3, [r3, #80] @ 0x50 80049aa: 2b00 cmp r3, #0 80049ac: d00c beq.n 80049c8 { /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ /* disable the request gen overrun IT*/ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; 80049ae: 687b ldr r3, [r7, #4] 80049b0: 6d1b ldr r3, [r3, #80] @ 0x50 80049b2: 681a ldr r2, [r3, #0] 80049b4: 687b ldr r3, [r7, #4] 80049b6: 6d1b ldr r3, [r3, #80] @ 0x50 80049b8: 490f ldr r1, [pc, #60] @ (80049f8 ) 80049ba: 400a ands r2, r1 80049bc: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 80049be: 687b ldr r3, [r7, #4] 80049c0: 6d5b ldr r3, [r3, #84] @ 0x54 80049c2: 687a ldr r2, [r7, #4] 80049c4: 6d92 ldr r2, [r2, #88] @ 0x58 80049c6: 605a str r2, [r3, #4] } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 80049c8: 687b ldr r3, [r7, #4] 80049ca: 2225 movs r2, #37 @ 0x25 80049cc: 2101 movs r1, #1 80049ce: 5499 strb r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(hdma); 80049d0: 687b ldr r3, [r7, #4] 80049d2: 2224 movs r2, #36 @ 0x24 80049d4: 2100 movs r1, #0 80049d6: 5499 strb r1, [r3, r2] /* Call User Abort callback */ if (hdma->XferAbortCallback != NULL) 80049d8: 687b ldr r3, [r7, #4] 80049da: 6b9b ldr r3, [r3, #56] @ 0x38 80049dc: 2b00 cmp r3, #0 80049de: d004 beq.n 80049ea { hdma->XferAbortCallback(hdma); 80049e0: 687b ldr r3, [r7, #4] 80049e2: 6b9b ldr r3, [r3, #56] @ 0x38 80049e4: 687a ldr r2, [r7, #4] 80049e6: 0010 movs r0, r2 80049e8: 4798 blx r3 } } return status; 80049ea: 230f movs r3, #15 80049ec: 18fb adds r3, r7, r3 80049ee: 781b ldrb r3, [r3, #0] } 80049f0: 0018 movs r0, r3 80049f2: 46bd mov sp, r7 80049f4: b004 add sp, #16 80049f6: bd80 pop {r7, pc} 80049f8: fffffeff .word 0xfffffeff 80049fc: 40020000 .word 0x40020000 08004a00 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL state */ HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) { 8004a00: b580 push {r7, lr} 8004a02: b082 sub sp, #8 8004a04: af00 add r7, sp, #0 8004a06: 6078 str r0, [r7, #4] /* Return DMA handle state */ return hdma->State; 8004a08: 687b ldr r3, [r7, #4] 8004a0a: 2225 movs r2, #37 @ 0x25 8004a0c: 5c9b ldrb r3, [r3, r2] 8004a0e: b2db uxtb r3, r3 } 8004a10: 0018 movs r0, r3 8004a12: 46bd mov sp, r7 8004a14: b002 add sp, #8 8004a16: bd80 pop {r7, pc} 08004a18 : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8004a18: b580 push {r7, lr} 8004a1a: b086 sub sp, #24 8004a1c: af00 add r7, sp, #0 8004a1e: 6078 str r0, [r7, #4] 8004a20: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 8004a22: 2300 movs r3, #0 8004a24: 617b str r3, [r7, #20] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 8004a26: e147 b.n 8004cb8 { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1uL << position); 8004a28: 683b ldr r3, [r7, #0] 8004a2a: 681b ldr r3, [r3, #0] 8004a2c: 2101 movs r1, #1 8004a2e: 697a ldr r2, [r7, #20] 8004a30: 4091 lsls r1, r2 8004a32: 000a movs r2, r1 8004a34: 4013 ands r3, r2 8004a36: 60fb str r3, [r7, #12] if (iocurrent != 0x00u) 8004a38: 68fb ldr r3, [r7, #12] 8004a3a: 2b00 cmp r3, #0 8004a3c: d100 bne.n 8004a40 8004a3e: e138 b.n 8004cb2 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) 8004a40: 683b ldr r3, [r7, #0] 8004a42: 685b ldr r3, [r3, #4] 8004a44: 2203 movs r2, #3 8004a46: 4013 ands r3, r2 8004a48: 2b01 cmp r3, #1 8004a4a: d005 beq.n 8004a58 8004a4c: 683b ldr r3, [r7, #0] 8004a4e: 685b ldr r3, [r3, #4] 8004a50: 2203 movs r2, #3 8004a52: 4013 ands r3, r2 8004a54: 2b02 cmp r3, #2 8004a56: d130 bne.n 8004aba { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 8004a58: 687b ldr r3, [r7, #4] 8004a5a: 689b ldr r3, [r3, #8] 8004a5c: 613b str r3, [r7, #16] temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u)); 8004a5e: 697b ldr r3, [r7, #20] 8004a60: 005b lsls r3, r3, #1 8004a62: 2203 movs r2, #3 8004a64: 409a lsls r2, r3 8004a66: 0013 movs r3, r2 8004a68: 43da mvns r2, r3 8004a6a: 693b ldr r3, [r7, #16] 8004a6c: 4013 ands r3, r2 8004a6e: 613b str r3, [r7, #16] temp |= (GPIO_Init->Speed << (position * 2u)); 8004a70: 683b ldr r3, [r7, #0] 8004a72: 68da ldr r2, [r3, #12] 8004a74: 697b ldr r3, [r7, #20] 8004a76: 005b lsls r3, r3, #1 8004a78: 409a lsls r2, r3 8004a7a: 0013 movs r3, r2 8004a7c: 693a ldr r2, [r7, #16] 8004a7e: 4313 orrs r3, r2 8004a80: 613b str r3, [r7, #16] GPIOx->OSPEEDR = temp; 8004a82: 687b ldr r3, [r7, #4] 8004a84: 693a ldr r2, [r7, #16] 8004a86: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 8004a88: 687b ldr r3, [r7, #4] 8004a8a: 685b ldr r3, [r3, #4] 8004a8c: 613b str r3, [r7, #16] temp &= ~(GPIO_OTYPER_OT0 << position) ; 8004a8e: 2201 movs r2, #1 8004a90: 697b ldr r3, [r7, #20] 8004a92: 409a lsls r2, r3 8004a94: 0013 movs r3, r2 8004a96: 43da mvns r2, r3 8004a98: 693b ldr r3, [r7, #16] 8004a9a: 4013 ands r3, r2 8004a9c: 613b str r3, [r7, #16] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 8004a9e: 683b ldr r3, [r7, #0] 8004aa0: 685b ldr r3, [r3, #4] 8004aa2: 091b lsrs r3, r3, #4 8004aa4: 2201 movs r2, #1 8004aa6: 401a ands r2, r3 8004aa8: 697b ldr r3, [r7, #20] 8004aaa: 409a lsls r2, r3 8004aac: 0013 movs r3, r2 8004aae: 693a ldr r2, [r7, #16] 8004ab0: 4313 orrs r3, r2 8004ab2: 613b str r3, [r7, #16] GPIOx->OTYPER = temp; 8004ab4: 687b ldr r3, [r7, #4] 8004ab6: 693a ldr r2, [r7, #16] 8004ab8: 605a str r2, [r3, #4] } if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 8004aba: 683b ldr r3, [r7, #0] 8004abc: 685b ldr r3, [r3, #4] 8004abe: 2203 movs r2, #3 8004ac0: 4013 ands r3, r2 8004ac2: 2b03 cmp r3, #3 8004ac4: d017 beq.n 8004af6 { /* Check the Pull parameter */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 8004ac6: 687b ldr r3, [r7, #4] 8004ac8: 68db ldr r3, [r3, #12] 8004aca: 613b str r3, [r7, #16] temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2u)); 8004acc: 697b ldr r3, [r7, #20] 8004ace: 005b lsls r3, r3, #1 8004ad0: 2203 movs r2, #3 8004ad2: 409a lsls r2, r3 8004ad4: 0013 movs r3, r2 8004ad6: 43da mvns r2, r3 8004ad8: 693b ldr r3, [r7, #16] 8004ada: 4013 ands r3, r2 8004adc: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Pull) << (position * 2u)); 8004ade: 683b ldr r3, [r7, #0] 8004ae0: 689a ldr r2, [r3, #8] 8004ae2: 697b ldr r3, [r7, #20] 8004ae4: 005b lsls r3, r3, #1 8004ae6: 409a lsls r2, r3 8004ae8: 0013 movs r3, r2 8004aea: 693a ldr r2, [r7, #16] 8004aec: 4313 orrs r3, r2 8004aee: 613b str r3, [r7, #16] GPIOx->PUPDR = temp; 8004af0: 687b ldr r3, [r7, #4] 8004af2: 693a ldr r2, [r7, #16] 8004af4: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8004af6: 683b ldr r3, [r7, #0] 8004af8: 685b ldr r3, [r3, #4] 8004afa: 2203 movs r2, #3 8004afc: 4013 ands r3, r2 8004afe: 2b02 cmp r3, #2 8004b00: d123 bne.n 8004b4a /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3u]; 8004b02: 697b ldr r3, [r7, #20] 8004b04: 08da lsrs r2, r3, #3 8004b06: 687b ldr r3, [r7, #4] 8004b08: 3208 adds r2, #8 8004b0a: 0092 lsls r2, r2, #2 8004b0c: 58d3 ldr r3, [r2, r3] 8004b0e: 613b str r3, [r7, #16] temp &= ~(0xFu << ((position & 0x07u) * 4u)); 8004b10: 697b ldr r3, [r7, #20] 8004b12: 2207 movs r2, #7 8004b14: 4013 ands r3, r2 8004b16: 009b lsls r3, r3, #2 8004b18: 220f movs r2, #15 8004b1a: 409a lsls r2, r3 8004b1c: 0013 movs r3, r2 8004b1e: 43da mvns r2, r3 8004b20: 693b ldr r3, [r7, #16] 8004b22: 4013 ands r3, r2 8004b24: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); 8004b26: 683b ldr r3, [r7, #0] 8004b28: 691a ldr r2, [r3, #16] 8004b2a: 697b ldr r3, [r7, #20] 8004b2c: 2107 movs r1, #7 8004b2e: 400b ands r3, r1 8004b30: 009b lsls r3, r3, #2 8004b32: 409a lsls r2, r3 8004b34: 0013 movs r3, r2 8004b36: 693a ldr r2, [r7, #16] 8004b38: 4313 orrs r3, r2 8004b3a: 613b str r3, [r7, #16] GPIOx->AFR[position >> 3u] = temp; 8004b3c: 697b ldr r3, [r7, #20] 8004b3e: 08da lsrs r2, r3, #3 8004b40: 687b ldr r3, [r7, #4] 8004b42: 3208 adds r2, #8 8004b44: 0092 lsls r2, r2, #2 8004b46: 6939 ldr r1, [r7, #16] 8004b48: 50d1 str r1, [r2, r3] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 8004b4a: 687b ldr r3, [r7, #4] 8004b4c: 681b ldr r3, [r3, #0] 8004b4e: 613b str r3, [r7, #16] temp &= ~(GPIO_MODER_MODE0 << (position * 2u)); 8004b50: 697b ldr r3, [r7, #20] 8004b52: 005b lsls r3, r3, #1 8004b54: 2203 movs r2, #3 8004b56: 409a lsls r2, r3 8004b58: 0013 movs r3, r2 8004b5a: 43da mvns r2, r3 8004b5c: 693b ldr r3, [r7, #16] 8004b5e: 4013 ands r3, r2 8004b60: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); 8004b62: 683b ldr r3, [r7, #0] 8004b64: 685b ldr r3, [r3, #4] 8004b66: 2203 movs r2, #3 8004b68: 401a ands r2, r3 8004b6a: 697b ldr r3, [r7, #20] 8004b6c: 005b lsls r3, r3, #1 8004b6e: 409a lsls r2, r3 8004b70: 0013 movs r3, r2 8004b72: 693a ldr r2, [r7, #16] 8004b74: 4313 orrs r3, r2 8004b76: 613b str r3, [r7, #16] GPIOx->MODER = temp; 8004b78: 687b ldr r3, [r7, #4] 8004b7a: 693a ldr r2, [r7, #16] 8004b7c: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u) 8004b7e: 683b ldr r3, [r7, #0] 8004b80: 685a ldr r2, [r3, #4] 8004b82: 23c0 movs r3, #192 @ 0xc0 8004b84: 029b lsls r3, r3, #10 8004b86: 4013 ands r3, r2 8004b88: d100 bne.n 8004b8c 8004b8a: e092 b.n 8004cb2 { temp = EXTI->EXTICR[position >> 2u]; 8004b8c: 4a50 ldr r2, [pc, #320] @ (8004cd0 ) 8004b8e: 697b ldr r3, [r7, #20] 8004b90: 089b lsrs r3, r3, #2 8004b92: 3318 adds r3, #24 8004b94: 009b lsls r3, r3, #2 8004b96: 589b ldr r3, [r3, r2] 8004b98: 613b str r3, [r7, #16] temp &= ~(0x0FuL << (8u * (position & 0x03u))); 8004b9a: 697b ldr r3, [r7, #20] 8004b9c: 2203 movs r2, #3 8004b9e: 4013 ands r3, r2 8004ba0: 00db lsls r3, r3, #3 8004ba2: 220f movs r2, #15 8004ba4: 409a lsls r2, r3 8004ba6: 0013 movs r3, r2 8004ba8: 43da mvns r2, r3 8004baa: 693b ldr r3, [r7, #16] 8004bac: 4013 ands r3, r2 8004bae: 613b str r3, [r7, #16] temp |= (GPIO_GET_INDEX(GPIOx) << (8u * (position & 0x03u))); 8004bb0: 687a ldr r2, [r7, #4] 8004bb2: 23a0 movs r3, #160 @ 0xa0 8004bb4: 05db lsls r3, r3, #23 8004bb6: 429a cmp r2, r3 8004bb8: d013 beq.n 8004be2 8004bba: 687b ldr r3, [r7, #4] 8004bbc: 4a45 ldr r2, [pc, #276] @ (8004cd4 ) 8004bbe: 4293 cmp r3, r2 8004bc0: d00d beq.n 8004bde 8004bc2: 687b ldr r3, [r7, #4] 8004bc4: 4a44 ldr r2, [pc, #272] @ (8004cd8 ) 8004bc6: 4293 cmp r3, r2 8004bc8: d007 beq.n 8004bda 8004bca: 687b ldr r3, [r7, #4] 8004bcc: 4a43 ldr r2, [pc, #268] @ (8004cdc ) 8004bce: 4293 cmp r3, r2 8004bd0: d101 bne.n 8004bd6 8004bd2: 2303 movs r3, #3 8004bd4: e006 b.n 8004be4 8004bd6: 2305 movs r3, #5 8004bd8: e004 b.n 8004be4 8004bda: 2302 movs r3, #2 8004bdc: e002 b.n 8004be4 8004bde: 2301 movs r3, #1 8004be0: e000 b.n 8004be4 8004be2: 2300 movs r3, #0 8004be4: 697a ldr r2, [r7, #20] 8004be6: 2103 movs r1, #3 8004be8: 400a ands r2, r1 8004bea: 00d2 lsls r2, r2, #3 8004bec: 4093 lsls r3, r2 8004bee: 693a ldr r2, [r7, #16] 8004bf0: 4313 orrs r3, r2 8004bf2: 613b str r3, [r7, #16] EXTI->EXTICR[position >> 2u] = temp; 8004bf4: 4936 ldr r1, [pc, #216] @ (8004cd0 ) 8004bf6: 697b ldr r3, [r7, #20] 8004bf8: 089b lsrs r3, r3, #2 8004bfa: 3318 adds r3, #24 8004bfc: 009b lsls r3, r3, #2 8004bfe: 693a ldr r2, [r7, #16] 8004c00: 505a str r2, [r3, r1] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR1; 8004c02: 4b33 ldr r3, [pc, #204] @ (8004cd0 ) 8004c04: 681b ldr r3, [r3, #0] 8004c06: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8004c08: 68fb ldr r3, [r7, #12] 8004c0a: 43da mvns r2, r3 8004c0c: 693b ldr r3, [r7, #16] 8004c0e: 4013 ands r3, r2 8004c10: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u) 8004c12: 683b ldr r3, [r7, #0] 8004c14: 685a ldr r2, [r3, #4] 8004c16: 2380 movs r3, #128 @ 0x80 8004c18: 035b lsls r3, r3, #13 8004c1a: 4013 ands r3, r2 8004c1c: d003 beq.n 8004c26 { temp |= iocurrent; 8004c1e: 693a ldr r2, [r7, #16] 8004c20: 68fb ldr r3, [r7, #12] 8004c22: 4313 orrs r3, r2 8004c24: 613b str r3, [r7, #16] } EXTI->RTSR1 = temp; 8004c26: 4b2a ldr r3, [pc, #168] @ (8004cd0 ) 8004c28: 693a ldr r2, [r7, #16] 8004c2a: 601a str r2, [r3, #0] temp = EXTI->FTSR1; 8004c2c: 4b28 ldr r3, [pc, #160] @ (8004cd0 ) 8004c2e: 685b ldr r3, [r3, #4] 8004c30: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8004c32: 68fb ldr r3, [r7, #12] 8004c34: 43da mvns r2, r3 8004c36: 693b ldr r3, [r7, #16] 8004c38: 4013 ands r3, r2 8004c3a: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u) 8004c3c: 683b ldr r3, [r7, #0] 8004c3e: 685a ldr r2, [r3, #4] 8004c40: 2380 movs r3, #128 @ 0x80 8004c42: 039b lsls r3, r3, #14 8004c44: 4013 ands r3, r2 8004c46: d003 beq.n 8004c50 { temp |= iocurrent; 8004c48: 693a ldr r2, [r7, #16] 8004c4a: 68fb ldr r3, [r7, #12] 8004c4c: 4313 orrs r3, r2 8004c4e: 613b str r3, [r7, #16] } EXTI->FTSR1 = temp; 8004c50: 4b1f ldr r3, [pc, #124] @ (8004cd0 ) 8004c52: 693a ldr r2, [r7, #16] 8004c54: 605a str r2, [r3, #4] /* Clear EXTI line configuration */ temp = EXTI->EMR1; 8004c56: 4a1e ldr r2, [pc, #120] @ (8004cd0 ) 8004c58: 2384 movs r3, #132 @ 0x84 8004c5a: 58d3 ldr r3, [r2, r3] 8004c5c: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8004c5e: 68fb ldr r3, [r7, #12] 8004c60: 43da mvns r2, r3 8004c62: 693b ldr r3, [r7, #16] 8004c64: 4013 ands r3, r2 8004c66: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u) 8004c68: 683b ldr r3, [r7, #0] 8004c6a: 685a ldr r2, [r3, #4] 8004c6c: 2380 movs r3, #128 @ 0x80 8004c6e: 029b lsls r3, r3, #10 8004c70: 4013 ands r3, r2 8004c72: d003 beq.n 8004c7c { temp |= iocurrent; 8004c74: 693a ldr r2, [r7, #16] 8004c76: 68fb ldr r3, [r7, #12] 8004c78: 4313 orrs r3, r2 8004c7a: 613b str r3, [r7, #16] } EXTI->EMR1 = temp; 8004c7c: 4914 ldr r1, [pc, #80] @ (8004cd0 ) 8004c7e: 2284 movs r2, #132 @ 0x84 8004c80: 693b ldr r3, [r7, #16] 8004c82: 508b str r3, [r1, r2] temp = EXTI->IMR1; 8004c84: 4a12 ldr r2, [pc, #72] @ (8004cd0 ) 8004c86: 2380 movs r3, #128 @ 0x80 8004c88: 58d3 ldr r3, [r2, r3] 8004c8a: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8004c8c: 68fb ldr r3, [r7, #12] 8004c8e: 43da mvns r2, r3 8004c90: 693b ldr r3, [r7, #16] 8004c92: 4013 ands r3, r2 8004c94: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & EXTI_IT) != 0x00u) 8004c96: 683b ldr r3, [r7, #0] 8004c98: 685a ldr r2, [r3, #4] 8004c9a: 2380 movs r3, #128 @ 0x80 8004c9c: 025b lsls r3, r3, #9 8004c9e: 4013 ands r3, r2 8004ca0: d003 beq.n 8004caa { temp |= iocurrent; 8004ca2: 693a ldr r2, [r7, #16] 8004ca4: 68fb ldr r3, [r7, #12] 8004ca6: 4313 orrs r3, r2 8004ca8: 613b str r3, [r7, #16] } EXTI->IMR1 = temp; 8004caa: 4909 ldr r1, [pc, #36] @ (8004cd0 ) 8004cac: 2280 movs r2, #128 @ 0x80 8004cae: 693b ldr r3, [r7, #16] 8004cb0: 508b str r3, [r1, r2] } } position++; 8004cb2: 697b ldr r3, [r7, #20] 8004cb4: 3301 adds r3, #1 8004cb6: 617b str r3, [r7, #20] while (((GPIO_Init->Pin) >> position) != 0x00u) 8004cb8: 683b ldr r3, [r7, #0] 8004cba: 681a ldr r2, [r3, #0] 8004cbc: 697b ldr r3, [r7, #20] 8004cbe: 40da lsrs r2, r3 8004cc0: 1e13 subs r3, r2, #0 8004cc2: d000 beq.n 8004cc6 8004cc4: e6b0 b.n 8004a28 } } 8004cc6: 46c0 nop @ (mov r8, r8) 8004cc8: 46c0 nop @ (mov r8, r8) 8004cca: 46bd mov sp, r7 8004ccc: b006 add sp, #24 8004cce: bd80 pop {r7, pc} 8004cd0: 40021800 .word 0x40021800 8004cd4: 50000400 .word 0x50000400 8004cd8: 50000800 .word 0x50000800 8004cdc: 50000c00 .word 0x50000c00 08004ce0 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 8004ce0: b580 push {r7, lr} 8004ce2: b082 sub sp, #8 8004ce4: af00 add r7, sp, #0 8004ce6: 6078 str r0, [r7, #4] 8004ce8: 0008 movs r0, r1 8004cea: 0011 movs r1, r2 8004cec: 1cbb adds r3, r7, #2 8004cee: 1c02 adds r2, r0, #0 8004cf0: 801a strh r2, [r3, #0] 8004cf2: 1c7b adds r3, r7, #1 8004cf4: 1c0a adds r2, r1, #0 8004cf6: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 8004cf8: 1c7b adds r3, r7, #1 8004cfa: 781b ldrb r3, [r3, #0] 8004cfc: 2b00 cmp r3, #0 8004cfe: d004 beq.n 8004d0a { GPIOx->BSRR = (uint32_t)GPIO_Pin; 8004d00: 1cbb adds r3, r7, #2 8004d02: 881a ldrh r2, [r3, #0] 8004d04: 687b ldr r3, [r7, #4] 8004d06: 619a str r2, [r3, #24] } else { GPIOx->BRR = (uint32_t)GPIO_Pin; } } 8004d08: e003 b.n 8004d12 GPIOx->BRR = (uint32_t)GPIO_Pin; 8004d0a: 1cbb adds r3, r7, #2 8004d0c: 881a ldrh r2, [r3, #0] 8004d0e: 687b ldr r3, [r7, #4] 8004d10: 629a str r2, [r3, #40] @ 0x28 } 8004d12: 46c0 nop @ (mov r8, r8) 8004d14: 46bd mov sp, r7 8004d16: b002 add sp, #8 8004d18: bd80 pop {r7, pc} ... 08004d1c : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) { 8004d1c: b580 push {r7, lr} 8004d1e: b082 sub sp, #8 8004d20: af00 add r7, sp, #0 8004d22: 6078 str r0, [r7, #4] /* Check the I2C handle allocation */ if (hi2c == NULL) 8004d24: 687b ldr r3, [r7, #4] 8004d26: 2b00 cmp r3, #0 8004d28: d101 bne.n 8004d2e { return HAL_ERROR; 8004d2a: 2301 movs r3, #1 8004d2c: e08f b.n 8004e4e assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); if (hi2c->State == HAL_I2C_STATE_RESET) 8004d2e: 687b ldr r3, [r7, #4] 8004d30: 2241 movs r2, #65 @ 0x41 8004d32: 5c9b ldrb r3, [r3, r2] 8004d34: b2db uxtb r3, r3 8004d36: 2b00 cmp r3, #0 8004d38: d107 bne.n 8004d4a { /* Allocate lock resource and initialize it */ hi2c->Lock = HAL_UNLOCKED; 8004d3a: 687b ldr r3, [r7, #4] 8004d3c: 2240 movs r2, #64 @ 0x40 8004d3e: 2100 movs r1, #0 8004d40: 5499 strb r1, [r3, r2] /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ hi2c->MspInitCallback(hi2c); #else /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ HAL_I2C_MspInit(hi2c); 8004d42: 687b ldr r3, [r7, #4] 8004d44: 0018 movs r0, r3 8004d46: f7ff fab3 bl 80042b0 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } hi2c->State = HAL_I2C_STATE_BUSY; 8004d4a: 687b ldr r3, [r7, #4] 8004d4c: 2241 movs r2, #65 @ 0x41 8004d4e: 2124 movs r1, #36 @ 0x24 8004d50: 5499 strb r1, [r3, r2] /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); 8004d52: 687b ldr r3, [r7, #4] 8004d54: 681b ldr r3, [r3, #0] 8004d56: 681a ldr r2, [r3, #0] 8004d58: 687b ldr r3, [r7, #4] 8004d5a: 681b ldr r3, [r3, #0] 8004d5c: 2101 movs r1, #1 8004d5e: 438a bics r2, r1 8004d60: 601a str r2, [r3, #0] /*---------------------------- I2Cx TIMINGR Configuration ------------------*/ /* Configure I2Cx: Frequency range */ hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK; 8004d62: 687b ldr r3, [r7, #4] 8004d64: 685a ldr r2, [r3, #4] 8004d66: 687b ldr r3, [r7, #4] 8004d68: 681b ldr r3, [r3, #0] 8004d6a: 493b ldr r1, [pc, #236] @ (8004e58 ) 8004d6c: 400a ands r2, r1 8004d6e: 611a str r2, [r3, #16] /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ /* Disable Own Address1 before set the Own Address1 configuration */ hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; 8004d70: 687b ldr r3, [r7, #4] 8004d72: 681b ldr r3, [r3, #0] 8004d74: 689a ldr r2, [r3, #8] 8004d76: 687b ldr r3, [r7, #4] 8004d78: 681b ldr r3, [r3, #0] 8004d7a: 4938 ldr r1, [pc, #224] @ (8004e5c ) 8004d7c: 400a ands r2, r1 8004d7e: 609a str r2, [r3, #8] /* Configure I2Cx: Own Address1 and ack own address1 mode */ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) 8004d80: 687b ldr r3, [r7, #4] 8004d82: 68db ldr r3, [r3, #12] 8004d84: 2b01 cmp r3, #1 8004d86: d108 bne.n 8004d9a { hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); 8004d88: 687b ldr r3, [r7, #4] 8004d8a: 689a ldr r2, [r3, #8] 8004d8c: 687b ldr r3, [r7, #4] 8004d8e: 681b ldr r3, [r3, #0] 8004d90: 2180 movs r1, #128 @ 0x80 8004d92: 0209 lsls r1, r1, #8 8004d94: 430a orrs r2, r1 8004d96: 609a str r2, [r3, #8] 8004d98: e007 b.n 8004daa } else /* I2C_ADDRESSINGMODE_10BIT */ { hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); 8004d9a: 687b ldr r3, [r7, #4] 8004d9c: 689a ldr r2, [r3, #8] 8004d9e: 687b ldr r3, [r7, #4] 8004da0: 681b ldr r3, [r3, #0] 8004da2: 2184 movs r1, #132 @ 0x84 8004da4: 0209 lsls r1, r1, #8 8004da6: 430a orrs r2, r1 8004da8: 609a str r2, [r3, #8] } /*---------------------------- I2Cx CR2 Configuration ----------------------*/ /* Configure I2Cx: Addressing Master mode */ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) 8004daa: 687b ldr r3, [r7, #4] 8004dac: 68db ldr r3, [r3, #12] 8004dae: 2b02 cmp r3, #2 8004db0: d109 bne.n 8004dc6 { SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10); 8004db2: 687b ldr r3, [r7, #4] 8004db4: 681b ldr r3, [r3, #0] 8004db6: 685a ldr r2, [r3, #4] 8004db8: 687b ldr r3, [r7, #4] 8004dba: 681b ldr r3, [r3, #0] 8004dbc: 2180 movs r1, #128 @ 0x80 8004dbe: 0109 lsls r1, r1, #4 8004dc0: 430a orrs r2, r1 8004dc2: 605a str r2, [r3, #4] 8004dc4: e007 b.n 8004dd6 } else { /* Clear the I2C ADD10 bit */ CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10); 8004dc6: 687b ldr r3, [r7, #4] 8004dc8: 681b ldr r3, [r3, #0] 8004dca: 685a ldr r2, [r3, #4] 8004dcc: 687b ldr r3, [r7, #4] 8004dce: 681b ldr r3, [r3, #0] 8004dd0: 4923 ldr r1, [pc, #140] @ (8004e60 ) 8004dd2: 400a ands r2, r1 8004dd4: 605a str r2, [r3, #4] } /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); 8004dd6: 687b ldr r3, [r7, #4] 8004dd8: 681b ldr r3, [r3, #0] 8004dda: 685a ldr r2, [r3, #4] 8004ddc: 687b ldr r3, [r7, #4] 8004dde: 681b ldr r3, [r3, #0] 8004de0: 4920 ldr r1, [pc, #128] @ (8004e64 ) 8004de2: 430a orrs r2, r1 8004de4: 605a str r2, [r3, #4] /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ /* Disable Own Address2 before set the Own Address2 configuration */ hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; 8004de6: 687b ldr r3, [r7, #4] 8004de8: 681b ldr r3, [r3, #0] 8004dea: 68da ldr r2, [r3, #12] 8004dec: 687b ldr r3, [r7, #4] 8004dee: 681b ldr r3, [r3, #0] 8004df0: 491a ldr r1, [pc, #104] @ (8004e5c ) 8004df2: 400a ands r2, r1 8004df4: 60da str r2, [r3, #12] /* Configure I2Cx: Dual mode and Own Address2 */ hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ 8004df6: 687b ldr r3, [r7, #4] 8004df8: 691a ldr r2, [r3, #16] 8004dfa: 687b ldr r3, [r7, #4] 8004dfc: 695b ldr r3, [r3, #20] 8004dfe: 431a orrs r2, r3 8004e00: 0011 movs r1, r2 (hi2c->Init.OwnAddress2Masks << 8)); 8004e02: 687b ldr r3, [r7, #4] 8004e04: 699b ldr r3, [r3, #24] 8004e06: 021a lsls r2, r3, #8 hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ 8004e08: 687b ldr r3, [r7, #4] 8004e0a: 681b ldr r3, [r3, #0] 8004e0c: 430a orrs r2, r1 8004e0e: 60da str r2, [r3, #12] /*---------------------------- I2Cx CR1 Configuration ----------------------*/ /* Configure I2Cx: Generalcall and NoStretch mode */ hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); 8004e10: 687b ldr r3, [r7, #4] 8004e12: 69d9 ldr r1, [r3, #28] 8004e14: 687b ldr r3, [r7, #4] 8004e16: 6a1a ldr r2, [r3, #32] 8004e18: 687b ldr r3, [r7, #4] 8004e1a: 681b ldr r3, [r3, #0] 8004e1c: 430a orrs r2, r1 8004e1e: 601a str r2, [r3, #0] /* Enable the selected I2C peripheral */ __HAL_I2C_ENABLE(hi2c); 8004e20: 687b ldr r3, [r7, #4] 8004e22: 681b ldr r3, [r3, #0] 8004e24: 681a ldr r2, [r3, #0] 8004e26: 687b ldr r3, [r7, #4] 8004e28: 681b ldr r3, [r3, #0] 8004e2a: 2101 movs r1, #1 8004e2c: 430a orrs r2, r1 8004e2e: 601a str r2, [r3, #0] hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 8004e30: 687b ldr r3, [r7, #4] 8004e32: 2200 movs r2, #0 8004e34: 645a str r2, [r3, #68] @ 0x44 hi2c->State = HAL_I2C_STATE_READY; 8004e36: 687b ldr r3, [r7, #4] 8004e38: 2241 movs r2, #65 @ 0x41 8004e3a: 2120 movs r1, #32 8004e3c: 5499 strb r1, [r3, r2] hi2c->PreviousState = I2C_STATE_NONE; 8004e3e: 687b ldr r3, [r7, #4] 8004e40: 2200 movs r2, #0 8004e42: 631a str r2, [r3, #48] @ 0x30 hi2c->Mode = HAL_I2C_MODE_NONE; 8004e44: 687b ldr r3, [r7, #4] 8004e46: 2242 movs r2, #66 @ 0x42 8004e48: 2100 movs r1, #0 8004e4a: 5499 strb r1, [r3, r2] return HAL_OK; 8004e4c: 2300 movs r3, #0 } 8004e4e: 0018 movs r0, r3 8004e50: 46bd mov sp, r7 8004e52: b002 add sp, #8 8004e54: bd80 pop {r7, pc} 8004e56: 46c0 nop @ (mov r8, r8) 8004e58: f0ffffff .word 0xf0ffffff 8004e5c: ffff7fff .word 0xffff7fff 8004e60: fffff7ff .word 0xfffff7ff 8004e64: 02008000 .word 0x02008000 08004e68 : * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) { 8004e68: b590 push {r4, r7, lr} 8004e6a: b089 sub sp, #36 @ 0x24 8004e6c: af02 add r7, sp, #8 8004e6e: 60f8 str r0, [r7, #12] 8004e70: 000c movs r4, r1 8004e72: 0010 movs r0, r2 8004e74: 0019 movs r1, r3 8004e76: 230a movs r3, #10 8004e78: 18fb adds r3, r7, r3 8004e7a: 1c22 adds r2, r4, #0 8004e7c: 801a strh r2, [r3, #0] 8004e7e: 2308 movs r3, #8 8004e80: 18fb adds r3, r7, r3 8004e82: 1c02 adds r2, r0, #0 8004e84: 801a strh r2, [r3, #0] 8004e86: 1dbb adds r3, r7, #6 8004e88: 1c0a adds r2, r1, #0 8004e8a: 801a strh r2, [r3, #0] uint32_t tickstart; /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); if (hi2c->State == HAL_I2C_STATE_READY) 8004e8c: 68fb ldr r3, [r7, #12] 8004e8e: 2241 movs r2, #65 @ 0x41 8004e90: 5c9b ldrb r3, [r3, r2] 8004e92: b2db uxtb r3, r3 8004e94: 2b20 cmp r3, #32 8004e96: d000 beq.n 8004e9a 8004e98: e10c b.n 80050b4 { if ((pData == NULL) || (Size == 0U)) 8004e9a: 6abb ldr r3, [r7, #40] @ 0x28 8004e9c: 2b00 cmp r3, #0 8004e9e: d004 beq.n 8004eaa 8004ea0: 232c movs r3, #44 @ 0x2c 8004ea2: 18fb adds r3, r7, r3 8004ea4: 881b ldrh r3, [r3, #0] 8004ea6: 2b00 cmp r3, #0 8004ea8: d105 bne.n 8004eb6 { hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; 8004eaa: 68fb ldr r3, [r7, #12] 8004eac: 2280 movs r2, #128 @ 0x80 8004eae: 0092 lsls r2, r2, #2 8004eb0: 645a str r2, [r3, #68] @ 0x44 return HAL_ERROR; 8004eb2: 2301 movs r3, #1 8004eb4: e0ff b.n 80050b6 } /* Process Locked */ __HAL_LOCK(hi2c); 8004eb6: 68fb ldr r3, [r7, #12] 8004eb8: 2240 movs r2, #64 @ 0x40 8004eba: 5c9b ldrb r3, [r3, r2] 8004ebc: 2b01 cmp r3, #1 8004ebe: d101 bne.n 8004ec4 8004ec0: 2302 movs r3, #2 8004ec2: e0f8 b.n 80050b6 8004ec4: 68fb ldr r3, [r7, #12] 8004ec6: 2240 movs r2, #64 @ 0x40 8004ec8: 2101 movs r1, #1 8004eca: 5499 strb r1, [r3, r2] /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); 8004ecc: f7ff fc22 bl 8004714 8004ed0: 0003 movs r3, r0 8004ed2: 617b str r3, [r7, #20] if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) 8004ed4: 2380 movs r3, #128 @ 0x80 8004ed6: 0219 lsls r1, r3, #8 8004ed8: 68f8 ldr r0, [r7, #12] 8004eda: 697b ldr r3, [r7, #20] 8004edc: 9300 str r3, [sp, #0] 8004ede: 2319 movs r3, #25 8004ee0: 2201 movs r2, #1 8004ee2: f001 fe47 bl 8006b74 8004ee6: 1e03 subs r3, r0, #0 8004ee8: d001 beq.n 8004eee { return HAL_ERROR; 8004eea: 2301 movs r3, #1 8004eec: e0e3 b.n 80050b6 } hi2c->State = HAL_I2C_STATE_BUSY_TX; 8004eee: 68fb ldr r3, [r7, #12] 8004ef0: 2241 movs r2, #65 @ 0x41 8004ef2: 2121 movs r1, #33 @ 0x21 8004ef4: 5499 strb r1, [r3, r2] hi2c->Mode = HAL_I2C_MODE_MEM; 8004ef6: 68fb ldr r3, [r7, #12] 8004ef8: 2242 movs r2, #66 @ 0x42 8004efa: 2140 movs r1, #64 @ 0x40 8004efc: 5499 strb r1, [r3, r2] hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 8004efe: 68fb ldr r3, [r7, #12] 8004f00: 2200 movs r2, #0 8004f02: 645a str r2, [r3, #68] @ 0x44 /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; 8004f04: 68fb ldr r3, [r7, #12] 8004f06: 6aba ldr r2, [r7, #40] @ 0x28 8004f08: 625a str r2, [r3, #36] @ 0x24 hi2c->XferCount = Size; 8004f0a: 68fb ldr r3, [r7, #12] 8004f0c: 222c movs r2, #44 @ 0x2c 8004f0e: 18ba adds r2, r7, r2 8004f10: 8812 ldrh r2, [r2, #0] 8004f12: 855a strh r2, [r3, #42] @ 0x2a hi2c->XferISR = NULL; 8004f14: 68fb ldr r3, [r7, #12] 8004f16: 2200 movs r2, #0 8004f18: 635a str r2, [r3, #52] @ 0x34 /* Send Slave Address and Memory Address */ if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) 8004f1a: 1dbb adds r3, r7, #6 8004f1c: 881c ldrh r4, [r3, #0] 8004f1e: 2308 movs r3, #8 8004f20: 18fb adds r3, r7, r3 8004f22: 881a ldrh r2, [r3, #0] 8004f24: 230a movs r3, #10 8004f26: 18fb adds r3, r7, r3 8004f28: 8819 ldrh r1, [r3, #0] 8004f2a: 68f8 ldr r0, [r7, #12] 8004f2c: 697b ldr r3, [r7, #20] 8004f2e: 9301 str r3, [sp, #4] 8004f30: 6b3b ldr r3, [r7, #48] @ 0x30 8004f32: 9300 str r3, [sp, #0] 8004f34: 0023 movs r3, r4 8004f36: f001 f855 bl 8005fe4 8004f3a: 1e03 subs r3, r0, #0 8004f3c: d005 beq.n 8004f4a { /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8004f3e: 68fb ldr r3, [r7, #12] 8004f40: 2240 movs r2, #64 @ 0x40 8004f42: 2100 movs r1, #0 8004f44: 5499 strb r1, [r3, r2] return HAL_ERROR; 8004f46: 2301 movs r3, #1 8004f48: e0b5 b.n 80050b6 } /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ if (hi2c->XferCount > MAX_NBYTE_SIZE) 8004f4a: 68fb ldr r3, [r7, #12] 8004f4c: 8d5b ldrh r3, [r3, #42] @ 0x2a 8004f4e: b29b uxth r3, r3 8004f50: 2bff cmp r3, #255 @ 0xff 8004f52: d911 bls.n 8004f78 { hi2c->XferSize = MAX_NBYTE_SIZE; 8004f54: 68fb ldr r3, [r7, #12] 8004f56: 22ff movs r2, #255 @ 0xff 8004f58: 851a strh r2, [r3, #40] @ 0x28 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); 8004f5a: 68fb ldr r3, [r7, #12] 8004f5c: 8d1b ldrh r3, [r3, #40] @ 0x28 8004f5e: b2da uxtb r2, r3 8004f60: 2380 movs r3, #128 @ 0x80 8004f62: 045c lsls r4, r3, #17 8004f64: 230a movs r3, #10 8004f66: 18fb adds r3, r7, r3 8004f68: 8819 ldrh r1, [r3, #0] 8004f6a: 68f8 ldr r0, [r7, #12] 8004f6c: 2300 movs r3, #0 8004f6e: 9300 str r3, [sp, #0] 8004f70: 0023 movs r3, r4 8004f72: f001 ffd9 bl 8006f28 8004f76: e012 b.n 8004f9e } else { hi2c->XferSize = hi2c->XferCount; 8004f78: 68fb ldr r3, [r7, #12] 8004f7a: 8d5b ldrh r3, [r3, #42] @ 0x2a 8004f7c: b29a uxth r2, r3 8004f7e: 68fb ldr r3, [r7, #12] 8004f80: 851a strh r2, [r3, #40] @ 0x28 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); 8004f82: 68fb ldr r3, [r7, #12] 8004f84: 8d1b ldrh r3, [r3, #40] @ 0x28 8004f86: b2da uxtb r2, r3 8004f88: 2380 movs r3, #128 @ 0x80 8004f8a: 049c lsls r4, r3, #18 8004f8c: 230a movs r3, #10 8004f8e: 18fb adds r3, r7, r3 8004f90: 8819 ldrh r1, [r3, #0] 8004f92: 68f8 ldr r0, [r7, #12] 8004f94: 2300 movs r3, #0 8004f96: 9300 str r3, [sp, #0] 8004f98: 0023 movs r3, r4 8004f9a: f001 ffc5 bl 8006f28 } do { /* Wait until TXIS flag is set */ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 8004f9e: 697a ldr r2, [r7, #20] 8004fa0: 6b39 ldr r1, [r7, #48] @ 0x30 8004fa2: 68fb ldr r3, [r7, #12] 8004fa4: 0018 movs r0, r3 8004fa6: f001 fe3d bl 8006c24 8004faa: 1e03 subs r3, r0, #0 8004fac: d001 beq.n 8004fb2 { return HAL_ERROR; 8004fae: 2301 movs r3, #1 8004fb0: e081 b.n 80050b6 } /* Write data to TXDR */ hi2c->Instance->TXDR = *hi2c->pBuffPtr; 8004fb2: 68fb ldr r3, [r7, #12] 8004fb4: 6a5b ldr r3, [r3, #36] @ 0x24 8004fb6: 781a ldrb r2, [r3, #0] 8004fb8: 68fb ldr r3, [r7, #12] 8004fba: 681b ldr r3, [r3, #0] 8004fbc: 629a str r2, [r3, #40] @ 0x28 /* Increment Buffer pointer */ hi2c->pBuffPtr++; 8004fbe: 68fb ldr r3, [r7, #12] 8004fc0: 6a5b ldr r3, [r3, #36] @ 0x24 8004fc2: 1c5a adds r2, r3, #1 8004fc4: 68fb ldr r3, [r7, #12] 8004fc6: 625a str r2, [r3, #36] @ 0x24 hi2c->XferCount--; 8004fc8: 68fb ldr r3, [r7, #12] 8004fca: 8d5b ldrh r3, [r3, #42] @ 0x2a 8004fcc: b29b uxth r3, r3 8004fce: 3b01 subs r3, #1 8004fd0: b29a uxth r2, r3 8004fd2: 68fb ldr r3, [r7, #12] 8004fd4: 855a strh r2, [r3, #42] @ 0x2a hi2c->XferSize--; 8004fd6: 68fb ldr r3, [r7, #12] 8004fd8: 8d1b ldrh r3, [r3, #40] @ 0x28 8004fda: 3b01 subs r3, #1 8004fdc: b29a uxth r2, r3 8004fde: 68fb ldr r3, [r7, #12] 8004fe0: 851a strh r2, [r3, #40] @ 0x28 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) 8004fe2: 68fb ldr r3, [r7, #12] 8004fe4: 8d5b ldrh r3, [r3, #42] @ 0x2a 8004fe6: b29b uxth r3, r3 8004fe8: 2b00 cmp r3, #0 8004fea: d03a beq.n 8005062 8004fec: 68fb ldr r3, [r7, #12] 8004fee: 8d1b ldrh r3, [r3, #40] @ 0x28 8004ff0: 2b00 cmp r3, #0 8004ff2: d136 bne.n 8005062 { /* Wait until TCR flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) 8004ff4: 6b3a ldr r2, [r7, #48] @ 0x30 8004ff6: 68f8 ldr r0, [r7, #12] 8004ff8: 697b ldr r3, [r7, #20] 8004ffa: 9300 str r3, [sp, #0] 8004ffc: 0013 movs r3, r2 8004ffe: 2200 movs r2, #0 8005000: 2180 movs r1, #128 @ 0x80 8005002: f001 fdb7 bl 8006b74 8005006: 1e03 subs r3, r0, #0 8005008: d001 beq.n 800500e { return HAL_ERROR; 800500a: 2301 movs r3, #1 800500c: e053 b.n 80050b6 } if (hi2c->XferCount > MAX_NBYTE_SIZE) 800500e: 68fb ldr r3, [r7, #12] 8005010: 8d5b ldrh r3, [r3, #42] @ 0x2a 8005012: b29b uxth r3, r3 8005014: 2bff cmp r3, #255 @ 0xff 8005016: d911 bls.n 800503c { hi2c->XferSize = MAX_NBYTE_SIZE; 8005018: 68fb ldr r3, [r7, #12] 800501a: 22ff movs r2, #255 @ 0xff 800501c: 851a strh r2, [r3, #40] @ 0x28 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, 800501e: 68fb ldr r3, [r7, #12] 8005020: 8d1b ldrh r3, [r3, #40] @ 0x28 8005022: b2da uxtb r2, r3 8005024: 2380 movs r3, #128 @ 0x80 8005026: 045c lsls r4, r3, #17 8005028: 230a movs r3, #10 800502a: 18fb adds r3, r7, r3 800502c: 8819 ldrh r1, [r3, #0] 800502e: 68f8 ldr r0, [r7, #12] 8005030: 2300 movs r3, #0 8005032: 9300 str r3, [sp, #0] 8005034: 0023 movs r3, r4 8005036: f001 ff77 bl 8006f28 800503a: e012 b.n 8005062 I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; 800503c: 68fb ldr r3, [r7, #12] 800503e: 8d5b ldrh r3, [r3, #42] @ 0x2a 8005040: b29a uxth r2, r3 8005042: 68fb ldr r3, [r7, #12] 8005044: 851a strh r2, [r3, #40] @ 0x28 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, 8005046: 68fb ldr r3, [r7, #12] 8005048: 8d1b ldrh r3, [r3, #40] @ 0x28 800504a: b2da uxtb r2, r3 800504c: 2380 movs r3, #128 @ 0x80 800504e: 049c lsls r4, r3, #18 8005050: 230a movs r3, #10 8005052: 18fb adds r3, r7, r3 8005054: 8819 ldrh r1, [r3, #0] 8005056: 68f8 ldr r0, [r7, #12] 8005058: 2300 movs r3, #0 800505a: 9300 str r3, [sp, #0] 800505c: 0023 movs r3, r4 800505e: f001 ff63 bl 8006f28 I2C_NO_STARTSTOP); } } } while (hi2c->XferCount > 0U); 8005062: 68fb ldr r3, [r7, #12] 8005064: 8d5b ldrh r3, [r3, #42] @ 0x2a 8005066: b29b uxth r3, r3 8005068: 2b00 cmp r3, #0 800506a: d198 bne.n 8004f9e /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is reset */ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 800506c: 697a ldr r2, [r7, #20] 800506e: 6b39 ldr r1, [r7, #48] @ 0x30 8005070: 68fb ldr r3, [r7, #12] 8005072: 0018 movs r0, r3 8005074: f001 fe1c bl 8006cb0 8005078: 1e03 subs r3, r0, #0 800507a: d001 beq.n 8005080 { return HAL_ERROR; 800507c: 2301 movs r3, #1 800507e: e01a b.n 80050b6 } /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); 8005080: 68fb ldr r3, [r7, #12] 8005082: 681b ldr r3, [r3, #0] 8005084: 2220 movs r2, #32 8005086: 61da str r2, [r3, #28] /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); 8005088: 68fb ldr r3, [r7, #12] 800508a: 681b ldr r3, [r3, #0] 800508c: 685a ldr r2, [r3, #4] 800508e: 68fb ldr r3, [r7, #12] 8005090: 681b ldr r3, [r3, #0] 8005092: 490b ldr r1, [pc, #44] @ (80050c0 ) 8005094: 400a ands r2, r1 8005096: 605a str r2, [r3, #4] hi2c->State = HAL_I2C_STATE_READY; 8005098: 68fb ldr r3, [r7, #12] 800509a: 2241 movs r2, #65 @ 0x41 800509c: 2120 movs r1, #32 800509e: 5499 strb r1, [r3, r2] hi2c->Mode = HAL_I2C_MODE_NONE; 80050a0: 68fb ldr r3, [r7, #12] 80050a2: 2242 movs r2, #66 @ 0x42 80050a4: 2100 movs r1, #0 80050a6: 5499 strb r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(hi2c); 80050a8: 68fb ldr r3, [r7, #12] 80050aa: 2240 movs r2, #64 @ 0x40 80050ac: 2100 movs r1, #0 80050ae: 5499 strb r1, [r3, r2] return HAL_OK; 80050b0: 2300 movs r3, #0 80050b2: e000 b.n 80050b6 } else { return HAL_BUSY; 80050b4: 2302 movs r3, #2 } } 80050b6: 0018 movs r0, r3 80050b8: 46bd mov sp, r7 80050ba: b007 add sp, #28 80050bc: bd90 pop {r4, r7, pc} 80050be: 46c0 nop @ (mov r8, r8) 80050c0: fe00e800 .word 0xfe00e800 080050c4 : * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { 80050c4: b590 push {r4, r7, lr} 80050c6: b087 sub sp, #28 80050c8: af02 add r7, sp, #8 80050ca: 60f8 str r0, [r7, #12] 80050cc: 000c movs r4, r1 80050ce: 0010 movs r0, r2 80050d0: 0019 movs r1, r3 80050d2: 230a movs r3, #10 80050d4: 18fb adds r3, r7, r3 80050d6: 1c22 adds r2, r4, #0 80050d8: 801a strh r2, [r3, #0] 80050da: 2308 movs r3, #8 80050dc: 18fb adds r3, r7, r3 80050de: 1c02 adds r2, r0, #0 80050e0: 801a strh r2, [r3, #0] 80050e2: 1dbb adds r3, r7, #6 80050e4: 1c0a adds r2, r1, #0 80050e6: 801a strh r2, [r3, #0] /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); if (hi2c->State == HAL_I2C_STATE_READY) 80050e8: 68fb ldr r3, [r7, #12] 80050ea: 2241 movs r2, #65 @ 0x41 80050ec: 5c9b ldrb r3, [r3, r2] 80050ee: b2db uxtb r3, r3 80050f0: 2b20 cmp r3, #32 80050f2: d000 beq.n 80050f6 80050f4: e078 b.n 80051e8 { if ((pData == NULL) || (Size == 0U)) 80050f6: 6a3b ldr r3, [r7, #32] 80050f8: 2b00 cmp r3, #0 80050fa: d004 beq.n 8005106 80050fc: 2324 movs r3, #36 @ 0x24 80050fe: 18fb adds r3, r7, r3 8005100: 881b ldrh r3, [r3, #0] 8005102: 2b00 cmp r3, #0 8005104: d105 bne.n 8005112 { hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; 8005106: 68fb ldr r3, [r7, #12] 8005108: 2280 movs r2, #128 @ 0x80 800510a: 0092 lsls r2, r2, #2 800510c: 645a str r2, [r3, #68] @ 0x44 return HAL_ERROR; 800510e: 2301 movs r3, #1 8005110: e06b b.n 80051ea } if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) 8005112: 68fb ldr r3, [r7, #12] 8005114: 681b ldr r3, [r3, #0] 8005116: 699a ldr r2, [r3, #24] 8005118: 2380 movs r3, #128 @ 0x80 800511a: 021b lsls r3, r3, #8 800511c: 401a ands r2, r3 800511e: 2380 movs r3, #128 @ 0x80 8005120: 021b lsls r3, r3, #8 8005122: 429a cmp r2, r3 8005124: d101 bne.n 800512a { return HAL_BUSY; 8005126: 2302 movs r3, #2 8005128: e05f b.n 80051ea } /* Process Locked */ __HAL_LOCK(hi2c); 800512a: 68fb ldr r3, [r7, #12] 800512c: 2240 movs r2, #64 @ 0x40 800512e: 5c9b ldrb r3, [r3, r2] 8005130: 2b01 cmp r3, #1 8005132: d101 bne.n 8005138 8005134: 2302 movs r3, #2 8005136: e058 b.n 80051ea 8005138: 68fb ldr r3, [r7, #12] 800513a: 2240 movs r2, #64 @ 0x40 800513c: 2101 movs r1, #1 800513e: 5499 strb r1, [r3, r2] hi2c->State = HAL_I2C_STATE_BUSY_RX; 8005140: 68fb ldr r3, [r7, #12] 8005142: 2241 movs r2, #65 @ 0x41 8005144: 2122 movs r1, #34 @ 0x22 8005146: 5499 strb r1, [r3, r2] hi2c->Mode = HAL_I2C_MODE_MEM; 8005148: 68fb ldr r3, [r7, #12] 800514a: 2242 movs r2, #66 @ 0x42 800514c: 2140 movs r1, #64 @ 0x40 800514e: 5499 strb r1, [r3, r2] hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 8005150: 68fb ldr r3, [r7, #12] 8005152: 2200 movs r2, #0 8005154: 645a str r2, [r3, #68] @ 0x44 /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; 8005156: 68fb ldr r3, [r7, #12] 8005158: 6a3a ldr r2, [r7, #32] 800515a: 625a str r2, [r3, #36] @ 0x24 hi2c->XferCount = Size; 800515c: 68fb ldr r3, [r7, #12] 800515e: 2224 movs r2, #36 @ 0x24 8005160: 18ba adds r2, r7, r2 8005162: 8812 ldrh r2, [r2, #0] 8005164: 855a strh r2, [r3, #42] @ 0x2a hi2c->XferOptions = I2C_NO_OPTION_FRAME; 8005166: 68fb ldr r3, [r7, #12] 8005168: 4a22 ldr r2, [pc, #136] @ (80051f4 ) 800516a: 62da str r2, [r3, #44] @ 0x2c hi2c->XferISR = I2C_Mem_ISR_IT; 800516c: 68fb ldr r3, [r7, #12] 800516e: 4a22 ldr r2, [pc, #136] @ (80051f8 ) 8005170: 635a str r2, [r3, #52] @ 0x34 hi2c->Devaddress = DevAddress; 8005172: 230a movs r3, #10 8005174: 18fb adds r3, r7, r3 8005176: 881a ldrh r2, [r3, #0] 8005178: 68fb ldr r3, [r7, #12] 800517a: 64da str r2, [r3, #76] @ 0x4c /* If Memory address size is 8Bit */ if (MemAddSize == I2C_MEMADD_SIZE_8BIT) 800517c: 1dbb adds r3, r7, #6 800517e: 881b ldrh r3, [r3, #0] 8005180: 2b01 cmp r3, #1 8005182: d10b bne.n 800519c { /* Prefetch Memory Address */ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); 8005184: 2308 movs r3, #8 8005186: 18fb adds r3, r7, r3 8005188: 881b ldrh r3, [r3, #0] 800518a: b2da uxtb r2, r3 800518c: 68fb ldr r3, [r7, #12] 800518e: 681b ldr r3, [r3, #0] 8005190: 629a str r2, [r3, #40] @ 0x28 /* Reset Memaddress content */ hi2c->Memaddress = 0xFFFFFFFFU; 8005192: 68fb ldr r3, [r7, #12] 8005194: 2201 movs r2, #1 8005196: 4252 negs r2, r2 8005198: 651a str r2, [r3, #80] @ 0x50 800519a: e00e b.n 80051ba } /* If Memory address size is 16Bit */ else { /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); 800519c: 2108 movs r1, #8 800519e: 187b adds r3, r7, r1 80051a0: 881b ldrh r3, [r3, #0] 80051a2: 0a1b lsrs r3, r3, #8 80051a4: b29b uxth r3, r3 80051a6: b2da uxtb r2, r3 80051a8: 68fb ldr r3, [r7, #12] 80051aa: 681b ldr r3, [r3, #0] 80051ac: 629a str r2, [r3, #40] @ 0x28 /* Prepare Memaddress buffer for LSB part */ hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); 80051ae: 187b adds r3, r7, r1 80051b0: 881b ldrh r3, [r3, #0] 80051b2: b2db uxtb r3, r3 80051b4: 001a movs r2, r3 80051b6: 68fb ldr r3, [r7, #12] 80051b8: 651a str r2, [r3, #80] @ 0x50 } /* Send Slave Address and Memory Address */ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); 80051ba: 1dbb adds r3, r7, #6 80051bc: 881b ldrh r3, [r3, #0] 80051be: b2da uxtb r2, r3 80051c0: 230a movs r3, #10 80051c2: 18fb adds r3, r7, r3 80051c4: 8819 ldrh r1, [r3, #0] 80051c6: 68f8 ldr r0, [r7, #12] 80051c8: 4b0c ldr r3, [pc, #48] @ (80051fc ) 80051ca: 9300 str r3, [sp, #0] 80051cc: 2300 movs r3, #0 80051ce: f001 feab bl 8006f28 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 80051d2: 68fb ldr r3, [r7, #12] 80051d4: 2240 movs r2, #64 @ 0x40 80051d6: 2100 movs r1, #0 80051d8: 5499 strb r1, [r3, r2] /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); 80051da: 68fb ldr r3, [r7, #12] 80051dc: 2101 movs r1, #1 80051de: 0018 movs r0, r3 80051e0: f001 fedc bl 8006f9c return HAL_OK; 80051e4: 2300 movs r3, #0 80051e6: e000 b.n 80051ea } else { return HAL_BUSY; 80051e8: 2302 movs r3, #2 } } 80051ea: 0018 movs r0, r3 80051ec: 46bd mov sp, r7 80051ee: b005 add sp, #20 80051f0: bd90 pop {r4, r7, pc} 80051f2: 46c0 nop @ (mov r8, r8) 80051f4: ffff0000 .word 0xffff0000 80051f8: 08005581 .word 0x08005581 80051fc: 80002000 .word 0x80002000 08005200 : * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) { 8005200: b580 push {r7, lr} 8005202: b08a sub sp, #40 @ 0x28 8005204: af02 add r7, sp, #8 8005206: 60f8 str r0, [r7, #12] 8005208: 607a str r2, [r7, #4] 800520a: 603b str r3, [r7, #0] 800520c: 230a movs r3, #10 800520e: 18fb adds r3, r7, r3 8005210: 1c0a adds r2, r1, #0 8005212: 801a strh r2, [r3, #0] uint32_t tickstart; __IO uint32_t I2C_Trials = 0UL; 8005214: 2300 movs r3, #0 8005216: 617b str r3, [r7, #20] FlagStatus tmp1; FlagStatus tmp2; if (hi2c->State == HAL_I2C_STATE_READY) 8005218: 68fb ldr r3, [r7, #12] 800521a: 2241 movs r2, #65 @ 0x41 800521c: 5c9b ldrb r3, [r3, r2] 800521e: b2db uxtb r3, r3 8005220: 2b20 cmp r3, #32 8005222: d000 beq.n 8005226 8005224: e0df b.n 80053e6 { if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) 8005226: 68fb ldr r3, [r7, #12] 8005228: 681b ldr r3, [r3, #0] 800522a: 699a ldr r2, [r3, #24] 800522c: 2380 movs r3, #128 @ 0x80 800522e: 021b lsls r3, r3, #8 8005230: 401a ands r2, r3 8005232: 2380 movs r3, #128 @ 0x80 8005234: 021b lsls r3, r3, #8 8005236: 429a cmp r2, r3 8005238: d101 bne.n 800523e { return HAL_BUSY; 800523a: 2302 movs r3, #2 800523c: e0d4 b.n 80053e8 } /* Process Locked */ __HAL_LOCK(hi2c); 800523e: 68fb ldr r3, [r7, #12] 8005240: 2240 movs r2, #64 @ 0x40 8005242: 5c9b ldrb r3, [r3, r2] 8005244: 2b01 cmp r3, #1 8005246: d101 bne.n 800524c 8005248: 2302 movs r3, #2 800524a: e0cd b.n 80053e8 800524c: 68fb ldr r3, [r7, #12] 800524e: 2240 movs r2, #64 @ 0x40 8005250: 2101 movs r1, #1 8005252: 5499 strb r1, [r3, r2] hi2c->State = HAL_I2C_STATE_BUSY; 8005254: 68fb ldr r3, [r7, #12] 8005256: 2241 movs r2, #65 @ 0x41 8005258: 2124 movs r1, #36 @ 0x24 800525a: 5499 strb r1, [r3, r2] hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 800525c: 68fb ldr r3, [r7, #12] 800525e: 2200 movs r2, #0 8005260: 645a str r2, [r3, #68] @ 0x44 do { /* Generate Start */ hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress); 8005262: 68fb ldr r3, [r7, #12] 8005264: 68db ldr r3, [r3, #12] 8005266: 2b01 cmp r3, #1 8005268: d107 bne.n 800527a 800526a: 230a movs r3, #10 800526c: 18fb adds r3, r7, r3 800526e: 881b ldrh r3, [r3, #0] 8005270: 059b lsls r3, r3, #22 8005272: 0d9b lsrs r3, r3, #22 8005274: 4a5e ldr r2, [pc, #376] @ (80053f0 ) 8005276: 431a orrs r2, r3 8005278: e006 b.n 8005288 800527a: 230a movs r3, #10 800527c: 18fb adds r3, r7, r3 800527e: 881b ldrh r3, [r3, #0] 8005280: 059b lsls r3, r3, #22 8005282: 0d9b lsrs r3, r3, #22 8005284: 4a5b ldr r2, [pc, #364] @ (80053f4 ) 8005286: 431a orrs r2, r3 8005288: 68fb ldr r3, [r7, #12] 800528a: 681b ldr r3, [r3, #0] 800528c: 605a str r2, [r3, #4] /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set or a NACK flag is set*/ tickstart = HAL_GetTick(); 800528e: f7ff fa41 bl 8004714 8005292: 0003 movs r3, r0 8005294: 61bb str r3, [r7, #24] tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF); 8005296: 68fb ldr r3, [r7, #12] 8005298: 681b ldr r3, [r3, #0] 800529a: 699b ldr r3, [r3, #24] 800529c: 2220 movs r2, #32 800529e: 4013 ands r3, r2 80052a0: 3b20 subs r3, #32 80052a2: 425a negs r2, r3 80052a4: 4153 adcs r3, r2 80052a6: b2da uxtb r2, r3 80052a8: 231f movs r3, #31 80052aa: 18fb adds r3, r7, r3 80052ac: 701a strb r2, [r3, #0] tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); 80052ae: 68fb ldr r3, [r7, #12] 80052b0: 681b ldr r3, [r3, #0] 80052b2: 699b ldr r3, [r3, #24] 80052b4: 2210 movs r2, #16 80052b6: 4013 ands r3, r2 80052b8: 3b10 subs r3, #16 80052ba: 425a negs r2, r3 80052bc: 4153 adcs r3, r2 80052be: b2da uxtb r2, r3 80052c0: 231e movs r3, #30 80052c2: 18fb adds r3, r7, r3 80052c4: 701a strb r2, [r3, #0] while ((tmp1 == RESET) && (tmp2 == RESET)) 80052c6: e035 b.n 8005334 { if (Timeout != HAL_MAX_DELAY) 80052c8: 683b ldr r3, [r7, #0] 80052ca: 3301 adds r3, #1 80052cc: d01a beq.n 8005304 { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) 80052ce: f7ff fa21 bl 8004714 80052d2: 0002 movs r2, r0 80052d4: 69bb ldr r3, [r7, #24] 80052d6: 1ad3 subs r3, r2, r3 80052d8: 683a ldr r2, [r7, #0] 80052da: 429a cmp r2, r3 80052dc: d302 bcc.n 80052e4 80052de: 683b ldr r3, [r7, #0] 80052e0: 2b00 cmp r3, #0 80052e2: d10f bne.n 8005304 { /* Update I2C state */ hi2c->State = HAL_I2C_STATE_READY; 80052e4: 68fb ldr r3, [r7, #12] 80052e6: 2241 movs r2, #65 @ 0x41 80052e8: 2120 movs r1, #32 80052ea: 5499 strb r1, [r3, r2] /* Update I2C error code */ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 80052ec: 68fb ldr r3, [r7, #12] 80052ee: 6c5b ldr r3, [r3, #68] @ 0x44 80052f0: 2220 movs r2, #32 80052f2: 431a orrs r2, r3 80052f4: 68fb ldr r3, [r7, #12] 80052f6: 645a str r2, [r3, #68] @ 0x44 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 80052f8: 68fb ldr r3, [r7, #12] 80052fa: 2240 movs r2, #64 @ 0x40 80052fc: 2100 movs r1, #0 80052fe: 5499 strb r1, [r3, r2] return HAL_ERROR; 8005300: 2301 movs r3, #1 8005302: e071 b.n 80053e8 } } tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF); 8005304: 68fb ldr r3, [r7, #12] 8005306: 681b ldr r3, [r3, #0] 8005308: 699b ldr r3, [r3, #24] 800530a: 2220 movs r2, #32 800530c: 4013 ands r3, r2 800530e: 3b20 subs r3, #32 8005310: 425a negs r2, r3 8005312: 4153 adcs r3, r2 8005314: b2da uxtb r2, r3 8005316: 231f movs r3, #31 8005318: 18fb adds r3, r7, r3 800531a: 701a strb r2, [r3, #0] tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); 800531c: 68fb ldr r3, [r7, #12] 800531e: 681b ldr r3, [r3, #0] 8005320: 699b ldr r3, [r3, #24] 8005322: 2210 movs r2, #16 8005324: 4013 ands r3, r2 8005326: 3b10 subs r3, #16 8005328: 425a negs r2, r3 800532a: 4153 adcs r3, r2 800532c: b2da uxtb r2, r3 800532e: 231e movs r3, #30 8005330: 18fb adds r3, r7, r3 8005332: 701a strb r2, [r3, #0] while ((tmp1 == RESET) && (tmp2 == RESET)) 8005334: 231f movs r3, #31 8005336: 18fb adds r3, r7, r3 8005338: 781b ldrb r3, [r3, #0] 800533a: 2b00 cmp r3, #0 800533c: d104 bne.n 8005348 800533e: 231e movs r3, #30 8005340: 18fb adds r3, r7, r3 8005342: 781b ldrb r3, [r3, #0] 8005344: 2b00 cmp r3, #0 8005346: d0bf beq.n 80052c8 } /* Check if the NACKF flag has not been set */ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) 8005348: 68fb ldr r3, [r7, #12] 800534a: 681b ldr r3, [r3, #0] 800534c: 699b ldr r3, [r3, #24] 800534e: 2210 movs r2, #16 8005350: 4013 ands r3, r2 8005352: 2b10 cmp r3, #16 8005354: d01a beq.n 800538c { /* Wait until STOPF flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) 8005356: 683a ldr r2, [r7, #0] 8005358: 68f8 ldr r0, [r7, #12] 800535a: 69bb ldr r3, [r7, #24] 800535c: 9300 str r3, [sp, #0] 800535e: 0013 movs r3, r2 8005360: 2200 movs r2, #0 8005362: 2120 movs r1, #32 8005364: f001 fc06 bl 8006b74 8005368: 1e03 subs r3, r0, #0 800536a: d001 beq.n 8005370 { return HAL_ERROR; 800536c: 2301 movs r3, #1 800536e: e03b b.n 80053e8 } /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); 8005370: 68fb ldr r3, [r7, #12] 8005372: 681b ldr r3, [r3, #0] 8005374: 2220 movs r2, #32 8005376: 61da str r2, [r3, #28] /* Device is ready */ hi2c->State = HAL_I2C_STATE_READY; 8005378: 68fb ldr r3, [r7, #12] 800537a: 2241 movs r2, #65 @ 0x41 800537c: 2120 movs r1, #32 800537e: 5499 strb r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8005380: 68fb ldr r3, [r7, #12] 8005382: 2240 movs r2, #64 @ 0x40 8005384: 2100 movs r1, #0 8005386: 5499 strb r1, [r3, r2] return HAL_OK; 8005388: 2300 movs r3, #0 800538a: e02d b.n 80053e8 } else { /* Wait until STOPF flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) 800538c: 683a ldr r2, [r7, #0] 800538e: 68f8 ldr r0, [r7, #12] 8005390: 69bb ldr r3, [r7, #24] 8005392: 9300 str r3, [sp, #0] 8005394: 0013 movs r3, r2 8005396: 2200 movs r2, #0 8005398: 2120 movs r1, #32 800539a: f001 fbeb bl 8006b74 800539e: 1e03 subs r3, r0, #0 80053a0: d001 beq.n 80053a6 { return HAL_ERROR; 80053a2: 2301 movs r3, #1 80053a4: e020 b.n 80053e8 } /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 80053a6: 68fb ldr r3, [r7, #12] 80053a8: 681b ldr r3, [r3, #0] 80053aa: 2210 movs r2, #16 80053ac: 61da str r2, [r3, #28] /* Clear STOP Flag, auto generated with autoend*/ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); 80053ae: 68fb ldr r3, [r7, #12] 80053b0: 681b ldr r3, [r3, #0] 80053b2: 2220 movs r2, #32 80053b4: 61da str r2, [r3, #28] } /* Increment Trials */ I2C_Trials++; 80053b6: 697b ldr r3, [r7, #20] 80053b8: 3301 adds r3, #1 80053ba: 617b str r3, [r7, #20] } while (I2C_Trials < Trials); 80053bc: 697b ldr r3, [r7, #20] 80053be: 687a ldr r2, [r7, #4] 80053c0: 429a cmp r2, r3 80053c2: d900 bls.n 80053c6 80053c4: e74d b.n 8005262 /* Update I2C state */ hi2c->State = HAL_I2C_STATE_READY; 80053c6: 68fb ldr r3, [r7, #12] 80053c8: 2241 movs r2, #65 @ 0x41 80053ca: 2120 movs r1, #32 80053cc: 5499 strb r1, [r3, r2] /* Update I2C error code */ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 80053ce: 68fb ldr r3, [r7, #12] 80053d0: 6c5b ldr r3, [r3, #68] @ 0x44 80053d2: 2220 movs r2, #32 80053d4: 431a orrs r2, r3 80053d6: 68fb ldr r3, [r7, #12] 80053d8: 645a str r2, [r3, #68] @ 0x44 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 80053da: 68fb ldr r3, [r7, #12] 80053dc: 2240 movs r2, #64 @ 0x40 80053de: 2100 movs r1, #0 80053e0: 5499 strb r1, [r3, r2] return HAL_ERROR; 80053e2: 2301 movs r3, #1 80053e4: e000 b.n 80053e8 } else { return HAL_BUSY; 80053e6: 2302 movs r3, #2 } } 80053e8: 0018 movs r0, r3 80053ea: 46bd mov sp, r7 80053ec: b008 add sp, #32 80053ee: bd80 pop {r7, pc} 80053f0: 02002000 .word 0x02002000 80053f4: 02002800 .word 0x02002800 080053f8 : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* Derogation MISRAC2012-Rule-8.13 */ { 80053f8: b580 push {r7, lr} 80053fa: b084 sub sp, #16 80053fc: af00 add r7, sp, #0 80053fe: 6078 str r0, [r7, #4] /* Get current IT Flags and IT sources value */ uint32_t itflags = READ_REG(hi2c->Instance->ISR); 8005400: 687b ldr r3, [r7, #4] 8005402: 681b ldr r3, [r3, #0] 8005404: 699b ldr r3, [r3, #24] 8005406: 60fb str r3, [r7, #12] uint32_t itsources = READ_REG(hi2c->Instance->CR1); 8005408: 687b ldr r3, [r7, #4] 800540a: 681b ldr r3, [r3, #0] 800540c: 681b ldr r3, [r3, #0] 800540e: 60bb str r3, [r7, #8] /* I2C events treatment -------------------------------------*/ if (hi2c->XferISR != NULL) 8005410: 687b ldr r3, [r7, #4] 8005412: 6b5b ldr r3, [r3, #52] @ 0x34 8005414: 2b00 cmp r3, #0 8005416: d005 beq.n 8005424 { hi2c->XferISR(hi2c, itflags, itsources); 8005418: 687b ldr r3, [r7, #4] 800541a: 6b5b ldr r3, [r3, #52] @ 0x34 800541c: 68ba ldr r2, [r7, #8] 800541e: 68f9 ldr r1, [r7, #12] 8005420: 6878 ldr r0, [r7, #4] 8005422: 4798 blx r3 } } 8005424: 46c0 nop @ (mov r8, r8) 8005426: 46bd mov sp, r7 8005428: b004 add sp, #16 800542a: bd80 pop {r7, pc} 0800542c : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) { 800542c: b580 push {r7, lr} 800542e: b086 sub sp, #24 8005430: af00 add r7, sp, #0 8005432: 6078 str r0, [r7, #4] uint32_t itflags = READ_REG(hi2c->Instance->ISR); 8005434: 687b ldr r3, [r7, #4] 8005436: 681b ldr r3, [r3, #0] 8005438: 699b ldr r3, [r3, #24] 800543a: 617b str r3, [r7, #20] uint32_t itsources = READ_REG(hi2c->Instance->CR1); 800543c: 687b ldr r3, [r7, #4] 800543e: 681b ldr r3, [r3, #0] 8005440: 681b ldr r3, [r3, #0] 8005442: 613b str r3, [r7, #16] uint32_t tmperror; /* I2C Bus error interrupt occurred ------------------------------------*/ if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \ 8005444: 697a ldr r2, [r7, #20] 8005446: 2380 movs r3, #128 @ 0x80 8005448: 005b lsls r3, r3, #1 800544a: 4013 ands r3, r2 800544c: d00e beq.n 800546c (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) 800544e: 693b ldr r3, [r7, #16] 8005450: 2280 movs r2, #128 @ 0x80 8005452: 4013 ands r3, r2 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \ 8005454: d00a beq.n 800546c { hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; 8005456: 687b ldr r3, [r7, #4] 8005458: 6c5b ldr r3, [r3, #68] @ 0x44 800545a: 2201 movs r2, #1 800545c: 431a orrs r2, r3 800545e: 687b ldr r3, [r7, #4] 8005460: 645a str r2, [r3, #68] @ 0x44 /* Clear BERR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); 8005462: 687b ldr r3, [r7, #4] 8005464: 681b ldr r3, [r3, #0] 8005466: 2280 movs r2, #128 @ 0x80 8005468: 0052 lsls r2, r2, #1 800546a: 61da str r2, [r3, #28] } /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \ 800546c: 697a ldr r2, [r7, #20] 800546e: 2380 movs r3, #128 @ 0x80 8005470: 00db lsls r3, r3, #3 8005472: 4013 ands r3, r2 8005474: d00e beq.n 8005494 (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) 8005476: 693b ldr r3, [r7, #16] 8005478: 2280 movs r2, #128 @ 0x80 800547a: 4013 ands r3, r2 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \ 800547c: d00a beq.n 8005494 { hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; 800547e: 687b ldr r3, [r7, #4] 8005480: 6c5b ldr r3, [r3, #68] @ 0x44 8005482: 2208 movs r2, #8 8005484: 431a orrs r2, r3 8005486: 687b ldr r3, [r7, #4] 8005488: 645a str r2, [r3, #68] @ 0x44 /* Clear OVR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); 800548a: 687b ldr r3, [r7, #4] 800548c: 681b ldr r3, [r3, #0] 800548e: 2280 movs r2, #128 @ 0x80 8005490: 00d2 lsls r2, r2, #3 8005492: 61da str r2, [r3, #28] } /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \ 8005494: 697a ldr r2, [r7, #20] 8005496: 2380 movs r3, #128 @ 0x80 8005498: 009b lsls r3, r3, #2 800549a: 4013 ands r3, r2 800549c: d00e beq.n 80054bc (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) 800549e: 693b ldr r3, [r7, #16] 80054a0: 2280 movs r2, #128 @ 0x80 80054a2: 4013 ands r3, r2 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \ 80054a4: d00a beq.n 80054bc { hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; 80054a6: 687b ldr r3, [r7, #4] 80054a8: 6c5b ldr r3, [r3, #68] @ 0x44 80054aa: 2202 movs r2, #2 80054ac: 431a orrs r2, r3 80054ae: 687b ldr r3, [r7, #4] 80054b0: 645a str r2, [r3, #68] @ 0x44 /* Clear ARLO flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); 80054b2: 687b ldr r3, [r7, #4] 80054b4: 681b ldr r3, [r3, #0] 80054b6: 2280 movs r2, #128 @ 0x80 80054b8: 0092 lsls r2, r2, #2 80054ba: 61da str r2, [r3, #28] } /* Store current volatile hi2c->ErrorCode, misra rule */ tmperror = hi2c->ErrorCode; 80054bc: 687b ldr r3, [r7, #4] 80054be: 6c5b ldr r3, [r3, #68] @ 0x44 80054c0: 60fb str r3, [r7, #12] /* Call the Error Callback in case of Error detected */ if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE) 80054c2: 68fb ldr r3, [r7, #12] 80054c4: 220b movs r2, #11 80054c6: 4013 ands r3, r2 80054c8: d005 beq.n 80054d6 { I2C_ITError(hi2c, tmperror); 80054ca: 68fa ldr r2, [r7, #12] 80054cc: 687b ldr r3, [r7, #4] 80054ce: 0011 movs r1, r2 80054d0: 0018 movs r0, r3 80054d2: f001 f9e3 bl 800689c } } 80054d6: 46c0 nop @ (mov r8, r8) 80054d8: 46bd mov sp, r7 80054da: b006 add sp, #24 80054dc: bd80 pop {r7, pc} 080054de : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) { 80054de: b580 push {r7, lr} 80054e0: b082 sub sp, #8 80054e2: af00 add r7, sp, #0 80054e4: 6078 str r0, [r7, #4] UNUSED(hi2c); /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_MasterTxCpltCallback could be implemented in the user file */ } 80054e6: 46c0 nop @ (mov r8, r8) 80054e8: 46bd mov sp, r7 80054ea: b002 add sp, #8 80054ec: bd80 pop {r7, pc} 080054ee : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) { 80054ee: b580 push {r7, lr} 80054f0: b082 sub sp, #8 80054f2: af00 add r7, sp, #0 80054f4: 6078 str r0, [r7, #4] UNUSED(hi2c); /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_MasterRxCpltCallback could be implemented in the user file */ } 80054f6: 46c0 nop @ (mov r8, r8) 80054f8: 46bd mov sp, r7 80054fa: b002 add sp, #8 80054fc: bd80 pop {r7, pc} 080054fe : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) { 80054fe: b580 push {r7, lr} 8005500: b082 sub sp, #8 8005502: af00 add r7, sp, #0 8005504: 6078 str r0, [r7, #4] UNUSED(hi2c); /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file */ } 8005506: 46c0 nop @ (mov r8, r8) 8005508: 46bd mov sp, r7 800550a: b002 add sp, #8 800550c: bd80 pop {r7, pc} 0800550e : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) { 800550e: b580 push {r7, lr} 8005510: b082 sub sp, #8 8005512: af00 add r7, sp, #0 8005514: 6078 str r0, [r7, #4] UNUSED(hi2c); /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file */ } 8005516: 46c0 nop @ (mov r8, r8) 8005518: 46bd mov sp, r7 800551a: b002 add sp, #8 800551c: bd80 pop {r7, pc} 0800551e : * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION * @param AddrMatchCode Address Match Code * @retval None */ __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) { 800551e: b580 push {r7, lr} 8005520: b082 sub sp, #8 8005522: af00 add r7, sp, #0 8005524: 6078 str r0, [r7, #4] 8005526: 0008 movs r0, r1 8005528: 0011 movs r1, r2 800552a: 1cfb adds r3, r7, #3 800552c: 1c02 adds r2, r0, #0 800552e: 701a strb r2, [r3, #0] 8005530: 003b movs r3, r7 8005532: 1c0a adds r2, r1, #0 8005534: 801a strh r2, [r3, #0] UNUSED(AddrMatchCode); /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_AddrCallback() could be implemented in the user file */ } 8005536: 46c0 nop @ (mov r8, r8) 8005538: 46bd mov sp, r7 800553a: b002 add sp, #8 800553c: bd80 pop {r7, pc} 0800553e : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) { 800553e: b580 push {r7, lr} 8005540: b082 sub sp, #8 8005542: af00 add r7, sp, #0 8005544: 6078 str r0, [r7, #4] UNUSED(hi2c); /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_ListenCpltCallback() could be implemented in the user file */ } 8005546: 46c0 nop @ (mov r8, r8) 8005548: 46bd mov sp, r7 800554a: b002 add sp, #8 800554c: bd80 pop {r7, pc} 0800554e : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) { 800554e: b580 push {r7, lr} 8005550: b082 sub sp, #8 8005552: af00 add r7, sp, #0 8005554: 6078 str r0, [r7, #4] UNUSED(hi2c); /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_MemTxCpltCallback could be implemented in the user file */ } 8005556: 46c0 nop @ (mov r8, r8) 8005558: 46bd mov sp, r7 800555a: b002 add sp, #8 800555c: bd80 pop {r7, pc} 0800555e : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) { 800555e: b580 push {r7, lr} 8005560: b082 sub sp, #8 8005562: af00 add r7, sp, #0 8005564: 6078 str r0, [r7, #4] UNUSED(hi2c); /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_ErrorCallback could be implemented in the user file */ } 8005566: 46c0 nop @ (mov r8, r8) 8005568: 46bd mov sp, r7 800556a: b002 add sp, #8 800556c: bd80 pop {r7, pc} 0800556e : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) { 800556e: b580 push {r7, lr} 8005570: b082 sub sp, #8 8005572: af00 add r7, sp, #0 8005574: 6078 str r0, [r7, #4] UNUSED(hi2c); /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_AbortCpltCallback could be implemented in the user file */ } 8005576: 46c0 nop @ (mov r8, r8) 8005578: 46bd mov sp, r7 800557a: b002 add sp, #8 800557c: bd80 pop {r7, pc} ... 08005580 : * @param ITSources Interrupt sources enabled. * @retval HAL status */ static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { 8005580: b590 push {r4, r7, lr} 8005582: b089 sub sp, #36 @ 0x24 8005584: af02 add r7, sp, #8 8005586: 60f8 str r0, [r7, #12] 8005588: 60b9 str r1, [r7, #8] 800558a: 607a str r2, [r7, #4] uint32_t direction = I2C_GENERATE_START_WRITE; 800558c: 4b8b ldr r3, [pc, #556] @ (80057bc ) 800558e: 617b str r3, [r7, #20] uint32_t tmpITFlags = ITFlags; 8005590: 68bb ldr r3, [r7, #8] 8005592: 613b str r3, [r7, #16] /* Process Locked */ __HAL_LOCK(hi2c); 8005594: 68fb ldr r3, [r7, #12] 8005596: 2240 movs r2, #64 @ 0x40 8005598: 5c9b ldrb r3, [r3, r2] 800559a: 2b01 cmp r3, #1 800559c: d101 bne.n 80055a2 800559e: 2302 movs r3, #2 80055a0: e107 b.n 80057b2 80055a2: 68fb ldr r3, [r7, #12] 80055a4: 2240 movs r2, #64 @ 0x40 80055a6: 2101 movs r1, #1 80055a8: 5499 strb r1, [r3, r2] if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ 80055aa: 693b ldr r3, [r7, #16] 80055ac: 2210 movs r2, #16 80055ae: 4013 ands r3, r2 80055b0: d012 beq.n 80055d8 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) 80055b2: 687b ldr r3, [r7, #4] 80055b4: 2210 movs r2, #16 80055b6: 4013 ands r3, r2 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ 80055b8: d00e beq.n 80055d8 { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 80055ba: 68fb ldr r3, [r7, #12] 80055bc: 681b ldr r3, [r3, #0] 80055be: 2210 movs r2, #16 80055c0: 61da str r2, [r3, #28] /* Set corresponding Error Code */ /* No need to generate STOP, it is automatically done */ /* Error callback will be send during stop flag treatment */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 80055c2: 68fb ldr r3, [r7, #12] 80055c4: 6c5b ldr r3, [r3, #68] @ 0x44 80055c6: 2204 movs r2, #4 80055c8: 431a orrs r2, r3 80055ca: 68fb ldr r3, [r7, #12] 80055cc: 645a str r2, [r3, #68] @ 0x44 /* Flush TX register */ I2C_Flush_TXDR(hi2c); 80055ce: 68fb ldr r3, [r7, #12] 80055d0: 0018 movs r0, r3 80055d2: f001 fa8e bl 8006af2 80055d6: e0d9 b.n 800578c } else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ 80055d8: 693b ldr r3, [r7, #16] 80055da: 2204 movs r2, #4 80055dc: 4013 ands r3, r2 80055de: d021 beq.n 8005624 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) 80055e0: 687b ldr r3, [r7, #4] 80055e2: 2204 movs r2, #4 80055e4: 4013 ands r3, r2 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ 80055e6: d01d beq.n 8005624 { /* Remove RXNE flag on temporary variable as read done */ tmpITFlags &= ~I2C_FLAG_RXNE; 80055e8: 693b ldr r3, [r7, #16] 80055ea: 2204 movs r2, #4 80055ec: 4393 bics r3, r2 80055ee: 613b str r3, [r7, #16] /* Read data from RXDR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; 80055f0: 68fb ldr r3, [r7, #12] 80055f2: 681b ldr r3, [r3, #0] 80055f4: 6a5a ldr r2, [r3, #36] @ 0x24 80055f6: 68fb ldr r3, [r7, #12] 80055f8: 6a5b ldr r3, [r3, #36] @ 0x24 80055fa: b2d2 uxtb r2, r2 80055fc: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 80055fe: 68fb ldr r3, [r7, #12] 8005600: 6a5b ldr r3, [r3, #36] @ 0x24 8005602: 1c5a adds r2, r3, #1 8005604: 68fb ldr r3, [r7, #12] 8005606: 625a str r2, [r3, #36] @ 0x24 hi2c->XferSize--; 8005608: 68fb ldr r3, [r7, #12] 800560a: 8d1b ldrh r3, [r3, #40] @ 0x28 800560c: 3b01 subs r3, #1 800560e: b29a uxth r2, r3 8005610: 68fb ldr r3, [r7, #12] 8005612: 851a strh r2, [r3, #40] @ 0x28 hi2c->XferCount--; 8005614: 68fb ldr r3, [r7, #12] 8005616: 8d5b ldrh r3, [r3, #42] @ 0x2a 8005618: b29b uxth r3, r3 800561a: 3b01 subs r3, #1 800561c: b29a uxth r2, r3 800561e: 68fb ldr r3, [r7, #12] 8005620: 855a strh r2, [r3, #42] @ 0x2a 8005622: e0b3 b.n 800578c } else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ 8005624: 693b ldr r3, [r7, #16] 8005626: 2202 movs r2, #2 8005628: 4013 ands r3, r2 800562a: d02a beq.n 8005682 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) 800562c: 687b ldr r3, [r7, #4] 800562e: 2202 movs r2, #2 8005630: 4013 ands r3, r2 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ 8005632: d026 beq.n 8005682 { if (hi2c->Memaddress == 0xFFFFFFFFU) 8005634: 68fb ldr r3, [r7, #12] 8005636: 6d1b ldr r3, [r3, #80] @ 0x50 8005638: 3301 adds r3, #1 800563a: d118 bne.n 800566e { /* Write data to TXDR */ hi2c->Instance->TXDR = *hi2c->pBuffPtr; 800563c: 68fb ldr r3, [r7, #12] 800563e: 6a5b ldr r3, [r3, #36] @ 0x24 8005640: 781a ldrb r2, [r3, #0] 8005642: 68fb ldr r3, [r7, #12] 8005644: 681b ldr r3, [r3, #0] 8005646: 629a str r2, [r3, #40] @ 0x28 /* Increment Buffer pointer */ hi2c->pBuffPtr++; 8005648: 68fb ldr r3, [r7, #12] 800564a: 6a5b ldr r3, [r3, #36] @ 0x24 800564c: 1c5a adds r2, r3, #1 800564e: 68fb ldr r3, [r7, #12] 8005650: 625a str r2, [r3, #36] @ 0x24 hi2c->XferSize--; 8005652: 68fb ldr r3, [r7, #12] 8005654: 8d1b ldrh r3, [r3, #40] @ 0x28 8005656: 3b01 subs r3, #1 8005658: b29a uxth r2, r3 800565a: 68fb ldr r3, [r7, #12] 800565c: 851a strh r2, [r3, #40] @ 0x28 hi2c->XferCount--; 800565e: 68fb ldr r3, [r7, #12] 8005660: 8d5b ldrh r3, [r3, #42] @ 0x2a 8005662: b29b uxth r3, r3 8005664: 3b01 subs r3, #1 8005666: b29a uxth r2, r3 8005668: 68fb ldr r3, [r7, #12] 800566a: 855a strh r2, [r3, #42] @ 0x2a if (hi2c->Memaddress == 0xFFFFFFFFU) 800566c: e08e b.n 800578c } else { /* Write LSB part of Memory Address */ hi2c->Instance->TXDR = hi2c->Memaddress; 800566e: 68fb ldr r3, [r7, #12] 8005670: 681b ldr r3, [r3, #0] 8005672: 68fa ldr r2, [r7, #12] 8005674: 6d12 ldr r2, [r2, #80] @ 0x50 8005676: 629a str r2, [r3, #40] @ 0x28 /* Reset Memaddress content */ hi2c->Memaddress = 0xFFFFFFFFU; 8005678: 68fb ldr r3, [r7, #12] 800567a: 2201 movs r2, #1 800567c: 4252 negs r2, r2 800567e: 651a str r2, [r3, #80] @ 0x50 if (hi2c->Memaddress == 0xFFFFFFFFU) 8005680: e084 b.n 800578c } } else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \ 8005682: 693b ldr r3, [r7, #16] 8005684: 2280 movs r2, #128 @ 0x80 8005686: 4013 ands r3, r2 8005688: d03c beq.n 8005704 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) 800568a: 687b ldr r3, [r7, #4] 800568c: 2240 movs r2, #64 @ 0x40 800568e: 4013 ands r3, r2 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \ 8005690: d038 beq.n 8005704 { if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) 8005692: 68fb ldr r3, [r7, #12] 8005694: 8d5b ldrh r3, [r3, #42] @ 0x2a 8005696: b29b uxth r3, r3 8005698: 2b00 cmp r3, #0 800569a: d02c beq.n 80056f6 800569c: 68fb ldr r3, [r7, #12] 800569e: 8d1b ldrh r3, [r3, #40] @ 0x28 80056a0: 2b00 cmp r3, #0 80056a2: d128 bne.n 80056f6 { if (hi2c->XferCount > MAX_NBYTE_SIZE) 80056a4: 68fb ldr r3, [r7, #12] 80056a6: 8d5b ldrh r3, [r3, #42] @ 0x2a 80056a8: b29b uxth r3, r3 80056aa: 2bff cmp r3, #255 @ 0xff 80056ac: d910 bls.n 80056d0 { hi2c->XferSize = MAX_NBYTE_SIZE; 80056ae: 68fb ldr r3, [r7, #12] 80056b0: 22ff movs r2, #255 @ 0xff 80056b2: 851a strh r2, [r3, #40] @ 0x28 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, 80056b4: 68fb ldr r3, [r7, #12] 80056b6: 6cdb ldr r3, [r3, #76] @ 0x4c 80056b8: b299 uxth r1, r3 80056ba: 68fb ldr r3, [r7, #12] 80056bc: 8d1b ldrh r3, [r3, #40] @ 0x28 80056be: b2da uxtb r2, r3 80056c0: 2380 movs r3, #128 @ 0x80 80056c2: 045b lsls r3, r3, #17 80056c4: 68f8 ldr r0, [r7, #12] 80056c6: 2400 movs r4, #0 80056c8: 9400 str r4, [sp, #0] 80056ca: f001 fc2d bl 8006f28 if (hi2c->XferCount > MAX_NBYTE_SIZE) 80056ce: e018 b.n 8005702 I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; 80056d0: 68fb ldr r3, [r7, #12] 80056d2: 8d5b ldrh r3, [r3, #42] @ 0x2a 80056d4: b29a uxth r2, r3 80056d6: 68fb ldr r3, [r7, #12] 80056d8: 851a strh r2, [r3, #40] @ 0x28 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, 80056da: 68fb ldr r3, [r7, #12] 80056dc: 6cdb ldr r3, [r3, #76] @ 0x4c 80056de: b299 uxth r1, r3 80056e0: 68fb ldr r3, [r7, #12] 80056e2: 8d1b ldrh r3, [r3, #40] @ 0x28 80056e4: b2da uxtb r2, r3 80056e6: 2380 movs r3, #128 @ 0x80 80056e8: 049b lsls r3, r3, #18 80056ea: 68f8 ldr r0, [r7, #12] 80056ec: 2400 movs r4, #0 80056ee: 9400 str r4, [sp, #0] 80056f0: f001 fc1a bl 8006f28 if (hi2c->XferCount > MAX_NBYTE_SIZE) 80056f4: e005 b.n 8005702 } else { /* Wrong size Status regarding TCR flag event */ /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); 80056f6: 68fb ldr r3, [r7, #12] 80056f8: 2140 movs r1, #64 @ 0x40 80056fa: 0018 movs r0, r3 80056fc: f001 f8ce bl 800689c if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) 8005700: e044 b.n 800578c 8005702: e043 b.n 800578c } } else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \ 8005704: 693b ldr r3, [r7, #16] 8005706: 2240 movs r2, #64 @ 0x40 8005708: 4013 ands r3, r2 800570a: d03f beq.n 800578c (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) 800570c: 687b ldr r3, [r7, #4] 800570e: 2240 movs r2, #64 @ 0x40 8005710: 4013 ands r3, r2 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \ 8005712: d03b beq.n 800578c { /* Disable Interrupt related to address step */ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); 8005714: 68fb ldr r3, [r7, #12] 8005716: 2101 movs r1, #1 8005718: 0018 movs r0, r3 800571a: f001 fcc9 bl 80070b0 /* Enable ERR, TC, STOP, NACK and RXI interrupts */ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); 800571e: 68fb ldr r3, [r7, #12] 8005720: 2102 movs r1, #2 8005722: 0018 movs r0, r3 8005724: f001 fc3a bl 8006f9c if (hi2c->State == HAL_I2C_STATE_BUSY_RX) 8005728: 68fb ldr r3, [r7, #12] 800572a: 2241 movs r2, #65 @ 0x41 800572c: 5c9b ldrb r3, [r3, r2] 800572e: b2db uxtb r3, r3 8005730: 2b22 cmp r3, #34 @ 0x22 8005732: d101 bne.n 8005738 { direction = I2C_GENERATE_START_READ; 8005734: 4b22 ldr r3, [pc, #136] @ (80057c0 ) 8005736: 617b str r3, [r7, #20] } if (hi2c->XferCount > MAX_NBYTE_SIZE) 8005738: 68fb ldr r3, [r7, #12] 800573a: 8d5b ldrh r3, [r3, #42] @ 0x2a 800573c: b29b uxth r3, r3 800573e: 2bff cmp r3, #255 @ 0xff 8005740: d911 bls.n 8005766 { hi2c->XferSize = MAX_NBYTE_SIZE; 8005742: 68fb ldr r3, [r7, #12] 8005744: 22ff movs r2, #255 @ 0xff 8005746: 851a strh r2, [r3, #40] @ 0x28 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, 8005748: 68fb ldr r3, [r7, #12] 800574a: 6cdb ldr r3, [r3, #76] @ 0x4c 800574c: b299 uxth r1, r3 800574e: 68fb ldr r3, [r7, #12] 8005750: 8d1b ldrh r3, [r3, #40] @ 0x28 8005752: b2da uxtb r2, r3 8005754: 2380 movs r3, #128 @ 0x80 8005756: 045c lsls r4, r3, #17 8005758: 68f8 ldr r0, [r7, #12] 800575a: 697b ldr r3, [r7, #20] 800575c: 9300 str r3, [sp, #0] 800575e: 0023 movs r3, r4 8005760: f001 fbe2 bl 8006f28 8005764: e012 b.n 800578c I2C_RELOAD_MODE, direction); } else { hi2c->XferSize = hi2c->XferCount; 8005766: 68fb ldr r3, [r7, #12] 8005768: 8d5b ldrh r3, [r3, #42] @ 0x2a 800576a: b29a uxth r2, r3 800576c: 68fb ldr r3, [r7, #12] 800576e: 851a strh r2, [r3, #40] @ 0x28 /* Set NBYTES to write and generate RESTART */ I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, 8005770: 68fb ldr r3, [r7, #12] 8005772: 6cdb ldr r3, [r3, #76] @ 0x4c 8005774: b299 uxth r1, r3 8005776: 68fb ldr r3, [r7, #12] 8005778: 8d1b ldrh r3, [r3, #40] @ 0x28 800577a: b2da uxtb r2, r3 800577c: 2380 movs r3, #128 @ 0x80 800577e: 049c lsls r4, r3, #18 8005780: 68f8 ldr r0, [r7, #12] 8005782: 697b ldr r3, [r7, #20] 8005784: 9300 str r3, [sp, #0] 8005786: 0023 movs r3, r4 8005788: f001 fbce bl 8006f28 else { /* Nothing to do */ } if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ 800578c: 693b ldr r3, [r7, #16] 800578e: 2220 movs r2, #32 8005790: 4013 ands r3, r2 8005792: d009 beq.n 80057a8 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) 8005794: 687b ldr r3, [r7, #4] 8005796: 2220 movs r2, #32 8005798: 4013 ands r3, r2 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ 800579a: d005 beq.n 80057a8 { /* Call I2C Master complete process */ I2C_ITMasterCplt(hi2c, tmpITFlags); 800579c: 693a ldr r2, [r7, #16] 800579e: 68fb ldr r3, [r7, #12] 80057a0: 0011 movs r1, r2 80057a2: 0018 movs r0, r3 80057a4: f000 fdcc bl 8006340 } /* Process Unlocked */ __HAL_UNLOCK(hi2c); 80057a8: 68fb ldr r3, [r7, #12] 80057aa: 2240 movs r2, #64 @ 0x40 80057ac: 2100 movs r1, #0 80057ae: 5499 strb r1, [r3, r2] return HAL_OK; 80057b0: 2300 movs r3, #0 } 80057b2: 0018 movs r0, r3 80057b4: 46bd mov sp, r7 80057b6: b007 add sp, #28 80057b8: bd90 pop {r4, r7, pc} 80057ba: 46c0 nop @ (mov r8, r8) 80057bc: 80002000 .word 0x80002000 80057c0: 80002400 .word 0x80002400 080057c4 : * @param ITSources Interrupt sources enabled. * @retval HAL status */ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { 80057c4: b580 push {r7, lr} 80057c6: b086 sub sp, #24 80057c8: af00 add r7, sp, #0 80057ca: 60f8 str r0, [r7, #12] 80057cc: 60b9 str r1, [r7, #8] 80057ce: 607a str r2, [r7, #4] uint32_t tmpoptions = hi2c->XferOptions; 80057d0: 68fb ldr r3, [r7, #12] 80057d2: 6adb ldr r3, [r3, #44] @ 0x2c 80057d4: 617b str r3, [r7, #20] uint32_t tmpITFlags = ITFlags; 80057d6: 68bb ldr r3, [r7, #8] 80057d8: 613b str r3, [r7, #16] /* Process locked */ __HAL_LOCK(hi2c); 80057da: 68fb ldr r3, [r7, #12] 80057dc: 2240 movs r2, #64 @ 0x40 80057de: 5c9b ldrb r3, [r3, r2] 80057e0: 2b01 cmp r3, #1 80057e2: d101 bne.n 80057e8 80057e4: 2302 movs r3, #2 80057e6: e0e7 b.n 80059b8 80057e8: 68fb ldr r3, [r7, #12] 80057ea: 2240 movs r2, #64 @ 0x40 80057ec: 2101 movs r1, #1 80057ee: 5499 strb r1, [r3, r2] /* Check if STOPF is set */ if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ 80057f0: 693b ldr r3, [r7, #16] 80057f2: 2220 movs r2, #32 80057f4: 4013 ands r3, r2 80057f6: d00a beq.n 800580e (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) 80057f8: 687b ldr r3, [r7, #4] 80057fa: 2220 movs r2, #32 80057fc: 4013 ands r3, r2 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ 80057fe: d006 beq.n 800580e { /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, tmpITFlags); 8005800: 693a ldr r2, [r7, #16] 8005802: 68fb ldr r3, [r7, #12] 8005804: 0011 movs r1, r2 8005806: 0018 movs r0, r3 8005808: f000 fe68 bl 80064dc 800580c: e0cf b.n 80059ae } else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ 800580e: 693b ldr r3, [r7, #16] 8005810: 2210 movs r2, #16 8005812: 4013 ands r3, r2 8005814: d052 beq.n 80058bc (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) 8005816: 687b ldr r3, [r7, #4] 8005818: 2210 movs r2, #16 800581a: 4013 ands r3, r2 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ 800581c: d04e beq.n 80058bc { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ /* Mean XferCount == 0*/ /* So clear Flag NACKF only */ if (hi2c->XferCount == 0U) 800581e: 68fb ldr r3, [r7, #12] 8005820: 8d5b ldrh r3, [r3, #42] @ 0x2a 8005822: b29b uxth r3, r3 8005824: 2b00 cmp r3, #0 8005826: d12d bne.n 8005884 { if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) 8005828: 68fb ldr r3, [r7, #12] 800582a: 2241 movs r2, #65 @ 0x41 800582c: 5c9b ldrb r3, [r3, r2] 800582e: b2db uxtb r3, r3 8005830: 2b28 cmp r3, #40 @ 0x28 8005832: d10b bne.n 800584c 8005834: 697a ldr r2, [r7, #20] 8005836: 2380 movs r3, #128 @ 0x80 8005838: 049b lsls r3, r3, #18 800583a: 429a cmp r2, r3 800583c: d106 bne.n 800584c /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ { /* Call I2C Listen complete process */ I2C_ITListenCplt(hi2c, tmpITFlags); 800583e: 693a ldr r2, [r7, #16] 8005840: 68fb ldr r3, [r7, #12] 8005842: 0011 movs r1, r2 8005844: 0018 movs r0, r3 8005846: f000 ffd1 bl 80067ec 800584a: e036 b.n 80058ba } else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) 800584c: 68fb ldr r3, [r7, #12] 800584e: 2241 movs r2, #65 @ 0x41 8005850: 5c9b ldrb r3, [r3, r2] 8005852: b2db uxtb r3, r3 8005854: 2b29 cmp r3, #41 @ 0x29 8005856: d110 bne.n 800587a 8005858: 697b ldr r3, [r7, #20] 800585a: 4a59 ldr r2, [pc, #356] @ (80059c0 ) 800585c: 4293 cmp r3, r2 800585e: d00c beq.n 800587a { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 8005860: 68fb ldr r3, [r7, #12] 8005862: 681b ldr r3, [r3, #0] 8005864: 2210 movs r2, #16 8005866: 61da str r2, [r3, #28] /* Flush TX register */ I2C_Flush_TXDR(hi2c); 8005868: 68fb ldr r3, [r7, #12] 800586a: 0018 movs r0, r3 800586c: f001 f941 bl 8006af2 /* Last Byte is Transmitted */ /* Call I2C Slave Sequential complete process */ I2C_ITSlaveSeqCplt(hi2c); 8005870: 68fb ldr r3, [r7, #12] 8005872: 0018 movs r0, r3 8005874: f000 fd00 bl 8006278 8005878: e01f b.n 80058ba } else { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 800587a: 68fb ldr r3, [r7, #12] 800587c: 681b ldr r3, [r3, #0] 800587e: 2210 movs r2, #16 8005880: 61da str r2, [r3, #28] if (hi2c->XferCount == 0U) 8005882: e091 b.n 80059a8 } else { /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 8005884: 68fb ldr r3, [r7, #12] 8005886: 681b ldr r3, [r3, #0] 8005888: 2210 movs r2, #16 800588a: 61da str r2, [r3, #28] /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 800588c: 68fb ldr r3, [r7, #12] 800588e: 6c5b ldr r3, [r3, #68] @ 0x44 8005890: 2204 movs r2, #4 8005892: 431a orrs r2, r3 8005894: 68fb ldr r3, [r7, #12] 8005896: 645a str r2, [r3, #68] @ 0x44 if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) 8005898: 697b ldr r3, [r7, #20] 800589a: 2b00 cmp r3, #0 800589c: d005 beq.n 80058aa 800589e: 697a ldr r2, [r7, #20] 80058a0: 2380 movs r3, #128 @ 0x80 80058a2: 045b lsls r3, r3, #17 80058a4: 429a cmp r2, r3 80058a6: d000 beq.n 80058aa 80058a8: e07e b.n 80059a8 { /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, hi2c->ErrorCode); 80058aa: 68fb ldr r3, [r7, #12] 80058ac: 6c5a ldr r2, [r3, #68] @ 0x44 80058ae: 68fb ldr r3, [r7, #12] 80058b0: 0011 movs r1, r2 80058b2: 0018 movs r0, r3 80058b4: f000 fff2 bl 800689c if (hi2c->XferCount == 0U) 80058b8: e076 b.n 80059a8 80058ba: e075 b.n 80059a8 } } } else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ 80058bc: 693b ldr r3, [r7, #16] 80058be: 2204 movs r2, #4 80058c0: 4013 ands r3, r2 80058c2: d02f beq.n 8005924 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) 80058c4: 687b ldr r3, [r7, #4] 80058c6: 2204 movs r2, #4 80058c8: 4013 ands r3, r2 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ 80058ca: d02b beq.n 8005924 { if (hi2c->XferCount > 0U) 80058cc: 68fb ldr r3, [r7, #12] 80058ce: 8d5b ldrh r3, [r3, #42] @ 0x2a 80058d0: b29b uxth r3, r3 80058d2: 2b00 cmp r3, #0 80058d4: d018 beq.n 8005908 { /* Read data from RXDR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; 80058d6: 68fb ldr r3, [r7, #12] 80058d8: 681b ldr r3, [r3, #0] 80058da: 6a5a ldr r2, [r3, #36] @ 0x24 80058dc: 68fb ldr r3, [r7, #12] 80058de: 6a5b ldr r3, [r3, #36] @ 0x24 80058e0: b2d2 uxtb r2, r2 80058e2: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 80058e4: 68fb ldr r3, [r7, #12] 80058e6: 6a5b ldr r3, [r3, #36] @ 0x24 80058e8: 1c5a adds r2, r3, #1 80058ea: 68fb ldr r3, [r7, #12] 80058ec: 625a str r2, [r3, #36] @ 0x24 hi2c->XferSize--; 80058ee: 68fb ldr r3, [r7, #12] 80058f0: 8d1b ldrh r3, [r3, #40] @ 0x28 80058f2: 3b01 subs r3, #1 80058f4: b29a uxth r2, r3 80058f6: 68fb ldr r3, [r7, #12] 80058f8: 851a strh r2, [r3, #40] @ 0x28 hi2c->XferCount--; 80058fa: 68fb ldr r3, [r7, #12] 80058fc: 8d5b ldrh r3, [r3, #42] @ 0x2a 80058fe: b29b uxth r3, r3 8005900: 3b01 subs r3, #1 8005902: b29a uxth r2, r3 8005904: 68fb ldr r3, [r7, #12] 8005906: 855a strh r2, [r3, #42] @ 0x2a } if ((hi2c->XferCount == 0U) && \ 8005908: 68fb ldr r3, [r7, #12] 800590a: 8d5b ldrh r3, [r3, #42] @ 0x2a 800590c: b29b uxth r3, r3 800590e: 2b00 cmp r3, #0 8005910: d14c bne.n 80059ac 8005912: 697b ldr r3, [r7, #20] 8005914: 4a2a ldr r2, [pc, #168] @ (80059c0 ) 8005916: 4293 cmp r3, r2 8005918: d048 beq.n 80059ac (tmpoptions != I2C_NO_OPTION_FRAME)) { /* Call I2C Slave Sequential complete process */ I2C_ITSlaveSeqCplt(hi2c); 800591a: 68fb ldr r3, [r7, #12] 800591c: 0018 movs r0, r3 800591e: f000 fcab bl 8006278 if ((hi2c->XferCount == 0U) && \ 8005922: e043 b.n 80059ac } } else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \ 8005924: 693b ldr r3, [r7, #16] 8005926: 2208 movs r2, #8 8005928: 4013 ands r3, r2 800592a: d00a beq.n 8005942 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) 800592c: 687b ldr r3, [r7, #4] 800592e: 2208 movs r2, #8 8005930: 4013 ands r3, r2 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \ 8005932: d006 beq.n 8005942 { I2C_ITAddrCplt(hi2c, tmpITFlags); 8005934: 693a ldr r2, [r7, #16] 8005936: 68fb ldr r3, [r7, #12] 8005938: 0011 movs r1, r2 800593a: 0018 movs r0, r3 800593c: f000 fbb6 bl 80060ac 8005940: e035 b.n 80059ae } else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ 8005942: 693b ldr r3, [r7, #16] 8005944: 2202 movs r2, #2 8005946: 4013 ands r3, r2 8005948: d031 beq.n 80059ae (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) 800594a: 687b ldr r3, [r7, #4] 800594c: 2202 movs r2, #2 800594e: 4013 ands r3, r2 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ 8005950: d02d beq.n 80059ae { /* Write data to TXDR only if XferCount not reach "0" */ /* A TXIS flag can be set, during STOP treatment */ /* Check if all Data have already been sent */ /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ if (hi2c->XferCount > 0U) 8005952: 68fb ldr r3, [r7, #12] 8005954: 8d5b ldrh r3, [r3, #42] @ 0x2a 8005956: b29b uxth r3, r3 8005958: 2b00 cmp r3, #0 800595a: d018 beq.n 800598e { /* Write data to TXDR */ hi2c->Instance->TXDR = *hi2c->pBuffPtr; 800595c: 68fb ldr r3, [r7, #12] 800595e: 6a5b ldr r3, [r3, #36] @ 0x24 8005960: 781a ldrb r2, [r3, #0] 8005962: 68fb ldr r3, [r7, #12] 8005964: 681b ldr r3, [r3, #0] 8005966: 629a str r2, [r3, #40] @ 0x28 /* Increment Buffer pointer */ hi2c->pBuffPtr++; 8005968: 68fb ldr r3, [r7, #12] 800596a: 6a5b ldr r3, [r3, #36] @ 0x24 800596c: 1c5a adds r2, r3, #1 800596e: 68fb ldr r3, [r7, #12] 8005970: 625a str r2, [r3, #36] @ 0x24 hi2c->XferCount--; 8005972: 68fb ldr r3, [r7, #12] 8005974: 8d5b ldrh r3, [r3, #42] @ 0x2a 8005976: b29b uxth r3, r3 8005978: 3b01 subs r3, #1 800597a: b29a uxth r2, r3 800597c: 68fb ldr r3, [r7, #12] 800597e: 855a strh r2, [r3, #42] @ 0x2a hi2c->XferSize--; 8005980: 68fb ldr r3, [r7, #12] 8005982: 8d1b ldrh r3, [r3, #40] @ 0x28 8005984: 3b01 subs r3, #1 8005986: b29a uxth r2, r3 8005988: 68fb ldr r3, [r7, #12] 800598a: 851a strh r2, [r3, #40] @ 0x28 800598c: e00f b.n 80059ae } else { if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) 800598e: 697a ldr r2, [r7, #20] 8005990: 2380 movs r3, #128 @ 0x80 8005992: 045b lsls r3, r3, #17 8005994: 429a cmp r2, r3 8005996: d002 beq.n 800599e 8005998: 697b ldr r3, [r7, #20] 800599a: 2b00 cmp r3, #0 800599c: d107 bne.n 80059ae { /* Last Byte is Transmitted */ /* Call I2C Slave Sequential complete process */ I2C_ITSlaveSeqCplt(hi2c); 800599e: 68fb ldr r3, [r7, #12] 80059a0: 0018 movs r0, r3 80059a2: f000 fc69 bl 8006278 80059a6: e002 b.n 80059ae if (hi2c->XferCount == 0U) 80059a8: 46c0 nop @ (mov r8, r8) 80059aa: e000 b.n 80059ae if ((hi2c->XferCount == 0U) && \ 80059ac: 46c0 nop @ (mov r8, r8) { /* Nothing to do */ } /* Process Unlocked */ __HAL_UNLOCK(hi2c); 80059ae: 68fb ldr r3, [r7, #12] 80059b0: 2240 movs r2, #64 @ 0x40 80059b2: 2100 movs r1, #0 80059b4: 5499 strb r1, [r3, r2] return HAL_OK; 80059b6: 2300 movs r3, #0 } 80059b8: 0018 movs r0, r3 80059ba: 46bd mov sp, r7 80059bc: b006 add sp, #24 80059be: bd80 pop {r7, pc} 80059c0: ffff0000 .word 0xffff0000 080059c4 : * @param ITSources Interrupt sources enabled. * @retval HAL status */ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { 80059c4: b590 push {r4, r7, lr} 80059c6: b089 sub sp, #36 @ 0x24 80059c8: af02 add r7, sp, #8 80059ca: 60f8 str r0, [r7, #12] 80059cc: 60b9 str r1, [r7, #8] 80059ce: 607a str r2, [r7, #4] uint16_t devaddress; uint32_t xfermode; /* Process Locked */ __HAL_LOCK(hi2c); 80059d0: 68fb ldr r3, [r7, #12] 80059d2: 2240 movs r2, #64 @ 0x40 80059d4: 5c9b ldrb r3, [r3, r2] 80059d6: 2b01 cmp r3, #1 80059d8: d101 bne.n 80059de 80059da: 2302 movs r3, #2 80059dc: e0e7 b.n 8005bae 80059de: 68fb ldr r3, [r7, #12] 80059e0: 2240 movs r2, #64 @ 0x40 80059e2: 2101 movs r1, #1 80059e4: 5499 strb r1, [r3, r2] if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ 80059e6: 68bb ldr r3, [r7, #8] 80059e8: 2210 movs r2, #16 80059ea: 4013 ands r3, r2 80059ec: d017 beq.n 8005a1e (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) 80059ee: 687b ldr r3, [r7, #4] 80059f0: 2210 movs r2, #16 80059f2: 4013 ands r3, r2 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ 80059f4: d013 beq.n 8005a1e { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 80059f6: 68fb ldr r3, [r7, #12] 80059f8: 681b ldr r3, [r3, #0] 80059fa: 2210 movs r2, #16 80059fc: 61da str r2, [r3, #28] /* Set corresponding Error Code */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 80059fe: 68fb ldr r3, [r7, #12] 8005a00: 6c5b ldr r3, [r3, #68] @ 0x44 8005a02: 2204 movs r2, #4 8005a04: 431a orrs r2, r3 8005a06: 68fb ldr r3, [r7, #12] 8005a08: 645a str r2, [r3, #68] @ 0x44 /* No need to generate STOP, it is automatically done */ /* But enable STOP interrupt, to treat it */ /* Error callback will be send during stop flag treatment */ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); 8005a0a: 68fb ldr r3, [r7, #12] 8005a0c: 2120 movs r1, #32 8005a0e: 0018 movs r0, r3 8005a10: f001 fac4 bl 8006f9c /* Flush TX register */ I2C_Flush_TXDR(hi2c); 8005a14: 68fb ldr r3, [r7, #12] 8005a16: 0018 movs r0, r3 8005a18: f001 f86b bl 8006af2 8005a1c: e0c2 b.n 8005ba4 } else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ 8005a1e: 68bb ldr r3, [r7, #8] 8005a20: 2280 movs r2, #128 @ 0x80 8005a22: 4013 ands r3, r2 8005a24: d100 bne.n 8005a28 8005a26: e07c b.n 8005b22 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) 8005a28: 687b ldr r3, [r7, #4] 8005a2a: 2240 movs r2, #64 @ 0x40 8005a2c: 4013 ands r3, r2 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ 8005a2e: d100 bne.n 8005a32 8005a30: e077 b.n 8005b22 { /* Disable TC interrupt */ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); 8005a32: 68fb ldr r3, [r7, #12] 8005a34: 681b ldr r3, [r3, #0] 8005a36: 681a ldr r2, [r3, #0] 8005a38: 68fb ldr r3, [r7, #12] 8005a3a: 681b ldr r3, [r3, #0] 8005a3c: 2140 movs r1, #64 @ 0x40 8005a3e: 438a bics r2, r1 8005a40: 601a str r2, [r3, #0] if (hi2c->XferCount != 0U) 8005a42: 68fb ldr r3, [r7, #12] 8005a44: 8d5b ldrh r3, [r3, #42] @ 0x2a 8005a46: b29b uxth r3, r3 8005a48: 2b00 cmp r3, #0 8005a4a: d055 beq.n 8005af8 { /* Recover Slave address */ devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); 8005a4c: 68fb ldr r3, [r7, #12] 8005a4e: 681b ldr r3, [r3, #0] 8005a50: 685b ldr r3, [r3, #4] 8005a52: b29a uxth r2, r3 8005a54: 2312 movs r3, #18 8005a56: 18fb adds r3, r7, r3 8005a58: 0592 lsls r2, r2, #22 8005a5a: 0d92 lsrs r2, r2, #22 8005a5c: 801a strh r2, [r3, #0] /* Prepare the new XferSize to transfer */ if (hi2c->XferCount > MAX_NBYTE_SIZE) 8005a5e: 68fb ldr r3, [r7, #12] 8005a60: 8d5b ldrh r3, [r3, #42] @ 0x2a 8005a62: b29b uxth r3, r3 8005a64: 2bff cmp r3, #255 @ 0xff 8005a66: d906 bls.n 8005a76 { hi2c->XferSize = MAX_NBYTE_SIZE; 8005a68: 68fb ldr r3, [r7, #12] 8005a6a: 22ff movs r2, #255 @ 0xff 8005a6c: 851a strh r2, [r3, #40] @ 0x28 xfermode = I2C_RELOAD_MODE; 8005a6e: 2380 movs r3, #128 @ 0x80 8005a70: 045b lsls r3, r3, #17 8005a72: 617b str r3, [r7, #20] 8005a74: e010 b.n 8005a98 } else { hi2c->XferSize = hi2c->XferCount; 8005a76: 68fb ldr r3, [r7, #12] 8005a78: 8d5b ldrh r3, [r3, #42] @ 0x2a 8005a7a: b29a uxth r2, r3 8005a7c: 68fb ldr r3, [r7, #12] 8005a7e: 851a strh r2, [r3, #40] @ 0x28 if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) 8005a80: 68fb ldr r3, [r7, #12] 8005a82: 6adb ldr r3, [r3, #44] @ 0x2c 8005a84: 4a4c ldr r2, [pc, #304] @ (8005bb8 ) 8005a86: 4293 cmp r3, r2 8005a88: d003 beq.n 8005a92 { xfermode = hi2c->XferOptions; 8005a8a: 68fb ldr r3, [r7, #12] 8005a8c: 6adb ldr r3, [r3, #44] @ 0x2c 8005a8e: 617b str r3, [r7, #20] 8005a90: e002 b.n 8005a98 } else { xfermode = I2C_AUTOEND_MODE; 8005a92: 2380 movs r3, #128 @ 0x80 8005a94: 049b lsls r3, r3, #18 8005a96: 617b str r3, [r7, #20] } } /* Set the new XferSize in Nbytes register */ I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); 8005a98: 68fb ldr r3, [r7, #12] 8005a9a: 8d1b ldrh r3, [r3, #40] @ 0x28 8005a9c: b2da uxtb r2, r3 8005a9e: 697c ldr r4, [r7, #20] 8005aa0: 2312 movs r3, #18 8005aa2: 18fb adds r3, r7, r3 8005aa4: 8819 ldrh r1, [r3, #0] 8005aa6: 68f8 ldr r0, [r7, #12] 8005aa8: 2300 movs r3, #0 8005aaa: 9300 str r3, [sp, #0] 8005aac: 0023 movs r3, r4 8005aae: f001 fa3b bl 8006f28 /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; 8005ab2: 68fb ldr r3, [r7, #12] 8005ab4: 8d5b ldrh r3, [r3, #42] @ 0x2a 8005ab6: b29a uxth r2, r3 8005ab8: 68fb ldr r3, [r7, #12] 8005aba: 8d1b ldrh r3, [r3, #40] @ 0x28 8005abc: 1ad3 subs r3, r2, r3 8005abe: b29a uxth r2, r3 8005ac0: 68fb ldr r3, [r7, #12] 8005ac2: 855a strh r2, [r3, #42] @ 0x2a /* Enable DMA Request */ if (hi2c->State == HAL_I2C_STATE_BUSY_RX) 8005ac4: 68fb ldr r3, [r7, #12] 8005ac6: 2241 movs r2, #65 @ 0x41 8005ac8: 5c9b ldrb r3, [r3, r2] 8005aca: b2db uxtb r3, r3 8005acc: 2b22 cmp r3, #34 @ 0x22 8005ace: d109 bne.n 8005ae4 { hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; 8005ad0: 68fb ldr r3, [r7, #12] 8005ad2: 681b ldr r3, [r3, #0] 8005ad4: 681a ldr r2, [r3, #0] 8005ad6: 68fb ldr r3, [r7, #12] 8005ad8: 681b ldr r3, [r3, #0] 8005ada: 2180 movs r1, #128 @ 0x80 8005adc: 0209 lsls r1, r1, #8 8005ade: 430a orrs r2, r1 8005ae0: 601a str r2, [r3, #0] if (hi2c->XferCount != 0U) 8005ae2: e05f b.n 8005ba4 } else { hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; 8005ae4: 68fb ldr r3, [r7, #12] 8005ae6: 681b ldr r3, [r3, #0] 8005ae8: 681a ldr r2, [r3, #0] 8005aea: 68fb ldr r3, [r7, #12] 8005aec: 681b ldr r3, [r3, #0] 8005aee: 2180 movs r1, #128 @ 0x80 8005af0: 01c9 lsls r1, r1, #7 8005af2: 430a orrs r2, r1 8005af4: 601a str r2, [r3, #0] if (hi2c->XferCount != 0U) 8005af6: e055 b.n 8005ba4 } } else { /* Call TxCpltCallback() if no stop mode is set */ if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) 8005af8: 68fb ldr r3, [r7, #12] 8005afa: 681b ldr r3, [r3, #0] 8005afc: 685a ldr r2, [r3, #4] 8005afe: 2380 movs r3, #128 @ 0x80 8005b00: 049b lsls r3, r3, #18 8005b02: 401a ands r2, r3 8005b04: 2380 movs r3, #128 @ 0x80 8005b06: 049b lsls r3, r3, #18 8005b08: 429a cmp r2, r3 8005b0a: d004 beq.n 8005b16 { /* Call I2C Master Sequential complete process */ I2C_ITMasterSeqCplt(hi2c); 8005b0c: 68fb ldr r3, [r7, #12] 8005b0e: 0018 movs r0, r3 8005b10: f000 fb70 bl 80061f4 if (hi2c->XferCount != 0U) 8005b14: e046 b.n 8005ba4 } else { /* Wrong size Status regarding TCR flag event */ /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); 8005b16: 68fb ldr r3, [r7, #12] 8005b18: 2140 movs r1, #64 @ 0x40 8005b1a: 0018 movs r0, r3 8005b1c: f000 febe bl 800689c if (hi2c->XferCount != 0U) 8005b20: e040 b.n 8005ba4 } } } else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ 8005b22: 68bb ldr r3, [r7, #8] 8005b24: 2240 movs r2, #64 @ 0x40 8005b26: 4013 ands r3, r2 8005b28: d02c beq.n 8005b84 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) 8005b2a: 687b ldr r3, [r7, #4] 8005b2c: 2240 movs r2, #64 @ 0x40 8005b2e: 4013 ands r3, r2 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ 8005b30: d028 beq.n 8005b84 { if (hi2c->XferCount == 0U) 8005b32: 68fb ldr r3, [r7, #12] 8005b34: 8d5b ldrh r3, [r3, #42] @ 0x2a 8005b36: b29b uxth r3, r3 8005b38: 2b00 cmp r3, #0 8005b3a: d11d bne.n 8005b78 { if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) 8005b3c: 68fb ldr r3, [r7, #12] 8005b3e: 681b ldr r3, [r3, #0] 8005b40: 685a ldr r2, [r3, #4] 8005b42: 2380 movs r3, #128 @ 0x80 8005b44: 049b lsls r3, r3, #18 8005b46: 401a ands r2, r3 8005b48: 2380 movs r3, #128 @ 0x80 8005b4a: 049b lsls r3, r3, #18 8005b4c: 429a cmp r2, r3 8005b4e: d028 beq.n 8005ba2 { /* Generate a stop condition in case of no transfer option */ if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) 8005b50: 68fb ldr r3, [r7, #12] 8005b52: 6adb ldr r3, [r3, #44] @ 0x2c 8005b54: 4a18 ldr r2, [pc, #96] @ (8005bb8 ) 8005b56: 4293 cmp r3, r2 8005b58: d109 bne.n 8005b6e { /* Generate Stop */ hi2c->Instance->CR2 |= I2C_CR2_STOP; 8005b5a: 68fb ldr r3, [r7, #12] 8005b5c: 681b ldr r3, [r3, #0] 8005b5e: 685a ldr r2, [r3, #4] 8005b60: 68fb ldr r3, [r7, #12] 8005b62: 681b ldr r3, [r3, #0] 8005b64: 2180 movs r1, #128 @ 0x80 8005b66: 01c9 lsls r1, r1, #7 8005b68: 430a orrs r2, r1 8005b6a: 605a str r2, [r3, #4] if (hi2c->XferCount == 0U) 8005b6c: e019 b.n 8005ba2 } else { /* Call I2C Master Sequential complete process */ I2C_ITMasterSeqCplt(hi2c); 8005b6e: 68fb ldr r3, [r7, #12] 8005b70: 0018 movs r0, r3 8005b72: f000 fb3f bl 80061f4 if (hi2c->XferCount == 0U) 8005b76: e014 b.n 8005ba2 } else { /* Wrong size Status regarding TC flag event */ /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); 8005b78: 68fb ldr r3, [r7, #12] 8005b7a: 2140 movs r1, #64 @ 0x40 8005b7c: 0018 movs r0, r3 8005b7e: f000 fe8d bl 800689c if (hi2c->XferCount == 0U) 8005b82: e00e b.n 8005ba2 } } else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ 8005b84: 68bb ldr r3, [r7, #8] 8005b86: 2220 movs r2, #32 8005b88: 4013 ands r3, r2 8005b8a: d00b beq.n 8005ba4 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) 8005b8c: 687b ldr r3, [r7, #4] 8005b8e: 2220 movs r2, #32 8005b90: 4013 ands r3, r2 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ 8005b92: d007 beq.n 8005ba4 { /* Call I2C Master complete process */ I2C_ITMasterCplt(hi2c, ITFlags); 8005b94: 68ba ldr r2, [r7, #8] 8005b96: 68fb ldr r3, [r7, #12] 8005b98: 0011 movs r1, r2 8005b9a: 0018 movs r0, r3 8005b9c: f000 fbd0 bl 8006340 8005ba0: e000 b.n 8005ba4 if (hi2c->XferCount == 0U) 8005ba2: 46c0 nop @ (mov r8, r8) { /* Nothing to do */ } /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8005ba4: 68fb ldr r3, [r7, #12] 8005ba6: 2240 movs r2, #64 @ 0x40 8005ba8: 2100 movs r1, #0 8005baa: 5499 strb r1, [r3, r2] return HAL_OK; 8005bac: 2300 movs r3, #0 } 8005bae: 0018 movs r0, r3 8005bb0: 46bd mov sp, r7 8005bb2: b007 add sp, #28 8005bb4: bd90 pop {r4, r7, pc} 8005bb6: 46c0 nop @ (mov r8, r8) 8005bb8: ffff0000 .word 0xffff0000 08005bbc : * @param ITSources Interrupt sources enabled. * @retval HAL status */ static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { 8005bbc: b590 push {r4, r7, lr} 8005bbe: b089 sub sp, #36 @ 0x24 8005bc0: af02 add r7, sp, #8 8005bc2: 60f8 str r0, [r7, #12] 8005bc4: 60b9 str r1, [r7, #8] 8005bc6: 607a str r2, [r7, #4] uint32_t direction = I2C_GENERATE_START_WRITE; 8005bc8: 4b90 ldr r3, [pc, #576] @ (8005e0c ) 8005bca: 617b str r3, [r7, #20] /* Process Locked */ __HAL_LOCK(hi2c); 8005bcc: 68fb ldr r3, [r7, #12] 8005bce: 2240 movs r2, #64 @ 0x40 8005bd0: 5c9b ldrb r3, [r3, r2] 8005bd2: 2b01 cmp r3, #1 8005bd4: d101 bne.n 8005bda 8005bd6: 2302 movs r3, #2 8005bd8: e113 b.n 8005e02 8005bda: 68fb ldr r3, [r7, #12] 8005bdc: 2240 movs r2, #64 @ 0x40 8005bde: 2101 movs r1, #1 8005be0: 5499 strb r1, [r3, r2] if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ 8005be2: 68bb ldr r3, [r7, #8] 8005be4: 2210 movs r2, #16 8005be6: 4013 ands r3, r2 8005be8: d017 beq.n 8005c1a (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) 8005bea: 687b ldr r3, [r7, #4] 8005bec: 2210 movs r2, #16 8005bee: 4013 ands r3, r2 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ 8005bf0: d013 beq.n 8005c1a { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 8005bf2: 68fb ldr r3, [r7, #12] 8005bf4: 681b ldr r3, [r3, #0] 8005bf6: 2210 movs r2, #16 8005bf8: 61da str r2, [r3, #28] /* Set corresponding Error Code */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 8005bfa: 68fb ldr r3, [r7, #12] 8005bfc: 6c5b ldr r3, [r3, #68] @ 0x44 8005bfe: 2204 movs r2, #4 8005c00: 431a orrs r2, r3 8005c02: 68fb ldr r3, [r7, #12] 8005c04: 645a str r2, [r3, #68] @ 0x44 /* No need to generate STOP, it is automatically done */ /* But enable STOP interrupt, to treat it */ /* Error callback will be send during stop flag treatment */ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); 8005c06: 68fb ldr r3, [r7, #12] 8005c08: 2120 movs r1, #32 8005c0a: 0018 movs r0, r3 8005c0c: f001 f9c6 bl 8006f9c /* Flush TX register */ I2C_Flush_TXDR(hi2c); 8005c10: 68fb ldr r3, [r7, #12] 8005c12: 0018 movs r0, r3 8005c14: f000 ff6d bl 8006af2 8005c18: e0ee b.n 8005df8 } else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \ 8005c1a: 68bb ldr r3, [r7, #8] 8005c1c: 2202 movs r2, #2 8005c1e: 4013 ands r3, r2 8005c20: d00d beq.n 8005c3e (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) 8005c22: 687b ldr r3, [r7, #4] 8005c24: 2202 movs r2, #2 8005c26: 4013 ands r3, r2 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \ 8005c28: d009 beq.n 8005c3e { /* Write LSB part of Memory Address */ hi2c->Instance->TXDR = hi2c->Memaddress; 8005c2a: 68fb ldr r3, [r7, #12] 8005c2c: 681b ldr r3, [r3, #0] 8005c2e: 68fa ldr r2, [r7, #12] 8005c30: 6d12 ldr r2, [r2, #80] @ 0x50 8005c32: 629a str r2, [r3, #40] @ 0x28 /* Reset Memaddress content */ hi2c->Memaddress = 0xFFFFFFFFU; 8005c34: 68fb ldr r3, [r7, #12] 8005c36: 2201 movs r2, #1 8005c38: 4252 negs r2, r2 8005c3a: 651a str r2, [r3, #80] @ 0x50 8005c3c: e0dc b.n 8005df8 } else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ 8005c3e: 68bb ldr r3, [r7, #8] 8005c40: 2280 movs r2, #128 @ 0x80 8005c42: 4013 ands r3, r2 8005c44: d063 beq.n 8005d0e (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) 8005c46: 687b ldr r3, [r7, #4] 8005c48: 2240 movs r2, #64 @ 0x40 8005c4a: 4013 ands r3, r2 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ 8005c4c: d05f beq.n 8005d0e { /* Disable Interrupt related to address step */ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); 8005c4e: 68fb ldr r3, [r7, #12] 8005c50: 2101 movs r1, #1 8005c52: 0018 movs r0, r3 8005c54: f001 fa2c bl 80070b0 /* Enable only Error interrupt */ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); 8005c58: 68fb ldr r3, [r7, #12] 8005c5a: 2110 movs r1, #16 8005c5c: 0018 movs r0, r3 8005c5e: f001 f99d bl 8006f9c if (hi2c->XferCount != 0U) 8005c62: 68fb ldr r3, [r7, #12] 8005c64: 8d5b ldrh r3, [r3, #42] @ 0x2a 8005c66: b29b uxth r3, r3 8005c68: 2b00 cmp r3, #0 8005c6a: d04a beq.n 8005d02 { /* Prepare the new XferSize to transfer */ if (hi2c->XferCount > MAX_NBYTE_SIZE) 8005c6c: 68fb ldr r3, [r7, #12] 8005c6e: 8d5b ldrh r3, [r3, #42] @ 0x2a 8005c70: b29b uxth r3, r3 8005c72: 2bff cmp r3, #255 @ 0xff 8005c74: d910 bls.n 8005c98 { hi2c->XferSize = MAX_NBYTE_SIZE; 8005c76: 68fb ldr r3, [r7, #12] 8005c78: 22ff movs r2, #255 @ 0xff 8005c7a: 851a strh r2, [r3, #40] @ 0x28 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, 8005c7c: 68fb ldr r3, [r7, #12] 8005c7e: 6cdb ldr r3, [r3, #76] @ 0x4c 8005c80: b299 uxth r1, r3 8005c82: 68fb ldr r3, [r7, #12] 8005c84: 8d1b ldrh r3, [r3, #40] @ 0x28 8005c86: b2da uxtb r2, r3 8005c88: 2380 movs r3, #128 @ 0x80 8005c8a: 045b lsls r3, r3, #17 8005c8c: 68f8 ldr r0, [r7, #12] 8005c8e: 2400 movs r4, #0 8005c90: 9400 str r4, [sp, #0] 8005c92: f001 f949 bl 8006f28 8005c96: e011 b.n 8005cbc I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; 8005c98: 68fb ldr r3, [r7, #12] 8005c9a: 8d5b ldrh r3, [r3, #42] @ 0x2a 8005c9c: b29a uxth r2, r3 8005c9e: 68fb ldr r3, [r7, #12] 8005ca0: 851a strh r2, [r3, #40] @ 0x28 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, 8005ca2: 68fb ldr r3, [r7, #12] 8005ca4: 6cdb ldr r3, [r3, #76] @ 0x4c 8005ca6: b299 uxth r1, r3 8005ca8: 68fb ldr r3, [r7, #12] 8005caa: 8d1b ldrh r3, [r3, #40] @ 0x28 8005cac: b2da uxtb r2, r3 8005cae: 2380 movs r3, #128 @ 0x80 8005cb0: 049b lsls r3, r3, #18 8005cb2: 68f8 ldr r0, [r7, #12] 8005cb4: 2400 movs r4, #0 8005cb6: 9400 str r4, [sp, #0] 8005cb8: f001 f936 bl 8006f28 I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; 8005cbc: 68fb ldr r3, [r7, #12] 8005cbe: 8d5b ldrh r3, [r3, #42] @ 0x2a 8005cc0: b29a uxth r2, r3 8005cc2: 68fb ldr r3, [r7, #12] 8005cc4: 8d1b ldrh r3, [r3, #40] @ 0x28 8005cc6: 1ad3 subs r3, r2, r3 8005cc8: b29a uxth r2, r3 8005cca: 68fb ldr r3, [r7, #12] 8005ccc: 855a strh r2, [r3, #42] @ 0x2a /* Enable DMA Request */ if (hi2c->State == HAL_I2C_STATE_BUSY_RX) 8005cce: 68fb ldr r3, [r7, #12] 8005cd0: 2241 movs r2, #65 @ 0x41 8005cd2: 5c9b ldrb r3, [r3, r2] 8005cd4: b2db uxtb r3, r3 8005cd6: 2b22 cmp r3, #34 @ 0x22 8005cd8: d109 bne.n 8005cee { hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; 8005cda: 68fb ldr r3, [r7, #12] 8005cdc: 681b ldr r3, [r3, #0] 8005cde: 681a ldr r2, [r3, #0] 8005ce0: 68fb ldr r3, [r7, #12] 8005ce2: 681b ldr r3, [r3, #0] 8005ce4: 2180 movs r1, #128 @ 0x80 8005ce6: 0209 lsls r1, r1, #8 8005ce8: 430a orrs r2, r1 8005cea: 601a str r2, [r3, #0] if (hi2c->XferCount != 0U) 8005cec: e084 b.n 8005df8 } else { hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; 8005cee: 68fb ldr r3, [r7, #12] 8005cf0: 681b ldr r3, [r3, #0] 8005cf2: 681a ldr r2, [r3, #0] 8005cf4: 68fb ldr r3, [r7, #12] 8005cf6: 681b ldr r3, [r3, #0] 8005cf8: 2180 movs r1, #128 @ 0x80 8005cfa: 01c9 lsls r1, r1, #7 8005cfc: 430a orrs r2, r1 8005cfe: 601a str r2, [r3, #0] if (hi2c->XferCount != 0U) 8005d00: e07a b.n 8005df8 } else { /* Wrong size Status regarding TCR flag event */ /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); 8005d02: 68fb ldr r3, [r7, #12] 8005d04: 2140 movs r1, #64 @ 0x40 8005d06: 0018 movs r0, r3 8005d08: f000 fdc8 bl 800689c if (hi2c->XferCount != 0U) 8005d0c: e074 b.n 8005df8 } } else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ 8005d0e: 68bb ldr r3, [r7, #8] 8005d10: 2240 movs r2, #64 @ 0x40 8005d12: 4013 ands r3, r2 8005d14: d062 beq.n 8005ddc (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) 8005d16: 687b ldr r3, [r7, #4] 8005d18: 2240 movs r2, #64 @ 0x40 8005d1a: 4013 ands r3, r2 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ 8005d1c: d05e beq.n 8005ddc { /* Disable Interrupt related to address step */ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); 8005d1e: 68fb ldr r3, [r7, #12] 8005d20: 2101 movs r1, #1 8005d22: 0018 movs r0, r3 8005d24: f001 f9c4 bl 80070b0 /* Enable only Error and NACK interrupt for data transfer */ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); 8005d28: 68fb ldr r3, [r7, #12] 8005d2a: 2110 movs r1, #16 8005d2c: 0018 movs r0, r3 8005d2e: f001 f935 bl 8006f9c if (hi2c->State == HAL_I2C_STATE_BUSY_RX) 8005d32: 68fb ldr r3, [r7, #12] 8005d34: 2241 movs r2, #65 @ 0x41 8005d36: 5c9b ldrb r3, [r3, r2] 8005d38: b2db uxtb r3, r3 8005d3a: 2b22 cmp r3, #34 @ 0x22 8005d3c: d101 bne.n 8005d42 { direction = I2C_GENERATE_START_READ; 8005d3e: 4b34 ldr r3, [pc, #208] @ (8005e10 ) 8005d40: 617b str r3, [r7, #20] } if (hi2c->XferCount > MAX_NBYTE_SIZE) 8005d42: 68fb ldr r3, [r7, #12] 8005d44: 8d5b ldrh r3, [r3, #42] @ 0x2a 8005d46: b29b uxth r3, r3 8005d48: 2bff cmp r3, #255 @ 0xff 8005d4a: d911 bls.n 8005d70 { hi2c->XferSize = MAX_NBYTE_SIZE; 8005d4c: 68fb ldr r3, [r7, #12] 8005d4e: 22ff movs r2, #255 @ 0xff 8005d50: 851a strh r2, [r3, #40] @ 0x28 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, 8005d52: 68fb ldr r3, [r7, #12] 8005d54: 6cdb ldr r3, [r3, #76] @ 0x4c 8005d56: b299 uxth r1, r3 8005d58: 68fb ldr r3, [r7, #12] 8005d5a: 8d1b ldrh r3, [r3, #40] @ 0x28 8005d5c: b2da uxtb r2, r3 8005d5e: 2380 movs r3, #128 @ 0x80 8005d60: 045c lsls r4, r3, #17 8005d62: 68f8 ldr r0, [r7, #12] 8005d64: 697b ldr r3, [r7, #20] 8005d66: 9300 str r3, [sp, #0] 8005d68: 0023 movs r3, r4 8005d6a: f001 f8dd bl 8006f28 8005d6e: e012 b.n 8005d96 I2C_RELOAD_MODE, direction); } else { hi2c->XferSize = hi2c->XferCount; 8005d70: 68fb ldr r3, [r7, #12] 8005d72: 8d5b ldrh r3, [r3, #42] @ 0x2a 8005d74: b29a uxth r2, r3 8005d76: 68fb ldr r3, [r7, #12] 8005d78: 851a strh r2, [r3, #40] @ 0x28 /* Set NBYTES to write and generate RESTART */ I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, 8005d7a: 68fb ldr r3, [r7, #12] 8005d7c: 6cdb ldr r3, [r3, #76] @ 0x4c 8005d7e: b299 uxth r1, r3 8005d80: 68fb ldr r3, [r7, #12] 8005d82: 8d1b ldrh r3, [r3, #40] @ 0x28 8005d84: b2da uxtb r2, r3 8005d86: 2380 movs r3, #128 @ 0x80 8005d88: 049c lsls r4, r3, #18 8005d8a: 68f8 ldr r0, [r7, #12] 8005d8c: 697b ldr r3, [r7, #20] 8005d8e: 9300 str r3, [sp, #0] 8005d90: 0023 movs r3, r4 8005d92: f001 f8c9 bl 8006f28 I2C_AUTOEND_MODE, direction); } /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; 8005d96: 68fb ldr r3, [r7, #12] 8005d98: 8d5b ldrh r3, [r3, #42] @ 0x2a 8005d9a: b29a uxth r2, r3 8005d9c: 68fb ldr r3, [r7, #12] 8005d9e: 8d1b ldrh r3, [r3, #40] @ 0x28 8005da0: 1ad3 subs r3, r2, r3 8005da2: b29a uxth r2, r3 8005da4: 68fb ldr r3, [r7, #12] 8005da6: 855a strh r2, [r3, #42] @ 0x2a /* Enable DMA Request */ if (hi2c->State == HAL_I2C_STATE_BUSY_RX) 8005da8: 68fb ldr r3, [r7, #12] 8005daa: 2241 movs r2, #65 @ 0x41 8005dac: 5c9b ldrb r3, [r3, r2] 8005dae: b2db uxtb r3, r3 8005db0: 2b22 cmp r3, #34 @ 0x22 8005db2: d109 bne.n 8005dc8 { hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; 8005db4: 68fb ldr r3, [r7, #12] 8005db6: 681b ldr r3, [r3, #0] 8005db8: 681a ldr r2, [r3, #0] 8005dba: 68fb ldr r3, [r7, #12] 8005dbc: 681b ldr r3, [r3, #0] 8005dbe: 2180 movs r1, #128 @ 0x80 8005dc0: 0209 lsls r1, r1, #8 8005dc2: 430a orrs r2, r1 8005dc4: 601a str r2, [r3, #0] if (hi2c->State == HAL_I2C_STATE_BUSY_RX) 8005dc6: e017 b.n 8005df8 } else { hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; 8005dc8: 68fb ldr r3, [r7, #12] 8005dca: 681b ldr r3, [r3, #0] 8005dcc: 681a ldr r2, [r3, #0] 8005dce: 68fb ldr r3, [r7, #12] 8005dd0: 681b ldr r3, [r3, #0] 8005dd2: 2180 movs r1, #128 @ 0x80 8005dd4: 01c9 lsls r1, r1, #7 8005dd6: 430a orrs r2, r1 8005dd8: 601a str r2, [r3, #0] if (hi2c->State == HAL_I2C_STATE_BUSY_RX) 8005dda: e00d b.n 8005df8 } } else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ 8005ddc: 68bb ldr r3, [r7, #8] 8005dde: 2220 movs r2, #32 8005de0: 4013 ands r3, r2 8005de2: d009 beq.n 8005df8 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) 8005de4: 687b ldr r3, [r7, #4] 8005de6: 2220 movs r2, #32 8005de8: 4013 ands r3, r2 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ 8005dea: d005 beq.n 8005df8 { /* Call I2C Master complete process */ I2C_ITMasterCplt(hi2c, ITFlags); 8005dec: 68ba ldr r2, [r7, #8] 8005dee: 68fb ldr r3, [r7, #12] 8005df0: 0011 movs r1, r2 8005df2: 0018 movs r0, r3 8005df4: f000 faa4 bl 8006340 { /* Nothing to do */ } /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8005df8: 68fb ldr r3, [r7, #12] 8005dfa: 2240 movs r2, #64 @ 0x40 8005dfc: 2100 movs r1, #0 8005dfe: 5499 strb r1, [r3, r2] return HAL_OK; 8005e00: 2300 movs r3, #0 } 8005e02: 0018 movs r0, r3 8005e04: 46bd mov sp, r7 8005e06: b007 add sp, #28 8005e08: bd90 pop {r4, r7, pc} 8005e0a: 46c0 nop @ (mov r8, r8) 8005e0c: 80002000 .word 0x80002000 8005e10: 80002400 .word 0x80002400 08005e14 : * @param ITSources Interrupt sources enabled. * @retval HAL status */ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { 8005e14: b580 push {r7, lr} 8005e16: b088 sub sp, #32 8005e18: af00 add r7, sp, #0 8005e1a: 60f8 str r0, [r7, #12] 8005e1c: 60b9 str r1, [r7, #8] 8005e1e: 607a str r2, [r7, #4] uint32_t tmpoptions = hi2c->XferOptions; 8005e20: 68fb ldr r3, [r7, #12] 8005e22: 6adb ldr r3, [r3, #44] @ 0x2c 8005e24: 61bb str r3, [r7, #24] uint32_t treatdmanack = 0U; 8005e26: 2300 movs r3, #0 8005e28: 61fb str r3, [r7, #28] HAL_I2C_StateTypeDef tmpstate; /* Process locked */ __HAL_LOCK(hi2c); 8005e2a: 68fb ldr r3, [r7, #12] 8005e2c: 2240 movs r2, #64 @ 0x40 8005e2e: 5c9b ldrb r3, [r3, r2] 8005e30: 2b01 cmp r3, #1 8005e32: d101 bne.n 8005e38 8005e34: 2302 movs r3, #2 8005e36: e0ce b.n 8005fd6 8005e38: 68fb ldr r3, [r7, #12] 8005e3a: 2240 movs r2, #64 @ 0x40 8005e3c: 2101 movs r1, #1 8005e3e: 5499 strb r1, [r3, r2] /* Check if STOPF is set */ if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ 8005e40: 68bb ldr r3, [r7, #8] 8005e42: 2220 movs r2, #32 8005e44: 4013 ands r3, r2 8005e46: d00a beq.n 8005e5e (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) 8005e48: 687b ldr r3, [r7, #4] 8005e4a: 2220 movs r2, #32 8005e4c: 4013 ands r3, r2 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ 8005e4e: d006 beq.n 8005e5e { /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, ITFlags); 8005e50: 68ba ldr r2, [r7, #8] 8005e52: 68fb ldr r3, [r7, #12] 8005e54: 0011 movs r1, r2 8005e56: 0018 movs r0, r3 8005e58: f000 fb40 bl 80064dc 8005e5c: e0b6 b.n 8005fcc } else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ 8005e5e: 68bb ldr r3, [r7, #8] 8005e60: 2210 movs r2, #16 8005e62: 4013 ands r3, r2 8005e64: d100 bne.n 8005e68 8005e66: e0a3 b.n 8005fb0 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) 8005e68: 687b ldr r3, [r7, #4] 8005e6a: 2210 movs r2, #16 8005e6c: 4013 ands r3, r2 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ 8005e6e: d100 bne.n 8005e72 8005e70: e09e b.n 8005fb0 { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ /* Mean XferCount == 0 */ /* So clear Flag NACKF only */ if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) || 8005e72: 687a ldr r2, [r7, #4] 8005e74: 2380 movs r3, #128 @ 0x80 8005e76: 01db lsls r3, r3, #7 8005e78: 4013 ands r3, r2 8005e7a: d105 bne.n 8005e88 (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)) 8005e7c: 687a ldr r2, [r7, #4] 8005e7e: 2380 movs r3, #128 @ 0x80 8005e80: 021b lsls r3, r3, #8 8005e82: 4013 ands r3, r2 if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) || 8005e84: d100 bne.n 8005e88 8005e86: e08c b.n 8005fa2 { /* Split check of hdmarx, for MISRA compliance */ if (hi2c->hdmarx != NULL) 8005e88: 68fb ldr r3, [r7, #12] 8005e8a: 6bdb ldr r3, [r3, #60] @ 0x3c 8005e8c: 2b00 cmp r3, #0 8005e8e: d00c beq.n 8005eaa { if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET) 8005e90: 687a ldr r2, [r7, #4] 8005e92: 2380 movs r3, #128 @ 0x80 8005e94: 021b lsls r3, r3, #8 8005e96: 4013 ands r3, r2 8005e98: d007 beq.n 8005eaa { if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) 8005e9a: 68fb ldr r3, [r7, #12] 8005e9c: 6bdb ldr r3, [r3, #60] @ 0x3c 8005e9e: 681b ldr r3, [r3, #0] 8005ea0: 685b ldr r3, [r3, #4] 8005ea2: 2b00 cmp r3, #0 8005ea4: d101 bne.n 8005eaa { treatdmanack = 1U; 8005ea6: 2301 movs r3, #1 8005ea8: 61fb str r3, [r7, #28] } } } /* Split check of hdmatx, for MISRA compliance */ if (hi2c->hdmatx != NULL) 8005eaa: 68fb ldr r3, [r7, #12] 8005eac: 6b9b ldr r3, [r3, #56] @ 0x38 8005eae: 2b00 cmp r3, #0 8005eb0: d00c beq.n 8005ecc { if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) 8005eb2: 687a ldr r2, [r7, #4] 8005eb4: 2380 movs r3, #128 @ 0x80 8005eb6: 01db lsls r3, r3, #7 8005eb8: 4013 ands r3, r2 8005eba: d007 beq.n 8005ecc { if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U) 8005ebc: 68fb ldr r3, [r7, #12] 8005ebe: 6b9b ldr r3, [r3, #56] @ 0x38 8005ec0: 681b ldr r3, [r3, #0] 8005ec2: 685b ldr r3, [r3, #4] 8005ec4: 2b00 cmp r3, #0 8005ec6: d101 bne.n 8005ecc { treatdmanack = 1U; 8005ec8: 2301 movs r3, #1 8005eca: 61fb str r3, [r7, #28] } } } if (treatdmanack == 1U) 8005ecc: 69fb ldr r3, [r7, #28] 8005ece: 2b01 cmp r3, #1 8005ed0: d12d bne.n 8005f2e { if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) 8005ed2: 68fb ldr r3, [r7, #12] 8005ed4: 2241 movs r2, #65 @ 0x41 8005ed6: 5c9b ldrb r3, [r3, r2] 8005ed8: b2db uxtb r3, r3 8005eda: 2b28 cmp r3, #40 @ 0x28 8005edc: d10b bne.n 8005ef6 8005ede: 69ba ldr r2, [r7, #24] 8005ee0: 2380 movs r3, #128 @ 0x80 8005ee2: 049b lsls r3, r3, #18 8005ee4: 429a cmp r2, r3 8005ee6: d106 bne.n 8005ef6 /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ { /* Call I2C Listen complete process */ I2C_ITListenCplt(hi2c, ITFlags); 8005ee8: 68ba ldr r2, [r7, #8] 8005eea: 68fb ldr r3, [r7, #12] 8005eec: 0011 movs r1, r2 8005eee: 0018 movs r0, r3 8005ef0: f000 fc7c bl 80067ec 8005ef4: e054 b.n 8005fa0 } else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) 8005ef6: 68fb ldr r3, [r7, #12] 8005ef8: 2241 movs r2, #65 @ 0x41 8005efa: 5c9b ldrb r3, [r3, r2] 8005efc: b2db uxtb r3, r3 8005efe: 2b29 cmp r3, #41 @ 0x29 8005f00: d110 bne.n 8005f24 8005f02: 69bb ldr r3, [r7, #24] 8005f04: 4a36 ldr r2, [pc, #216] @ (8005fe0 ) 8005f06: 4293 cmp r3, r2 8005f08: d00c beq.n 8005f24 { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 8005f0a: 68fb ldr r3, [r7, #12] 8005f0c: 681b ldr r3, [r3, #0] 8005f0e: 2210 movs r2, #16 8005f10: 61da str r2, [r3, #28] /* Flush TX register */ I2C_Flush_TXDR(hi2c); 8005f12: 68fb ldr r3, [r7, #12] 8005f14: 0018 movs r0, r3 8005f16: f000 fdec bl 8006af2 /* Last Byte is Transmitted */ /* Call I2C Slave Sequential complete process */ I2C_ITSlaveSeqCplt(hi2c); 8005f1a: 68fb ldr r3, [r7, #12] 8005f1c: 0018 movs r0, r3 8005f1e: f000 f9ab bl 8006278 8005f22: e03d b.n 8005fa0 } else { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 8005f24: 68fb ldr r3, [r7, #12] 8005f26: 681b ldr r3, [r3, #0] 8005f28: 2210 movs r2, #16 8005f2a: 61da str r2, [r3, #28] if (treatdmanack == 1U) 8005f2c: e03e b.n 8005fac } else { /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 8005f2e: 68fb ldr r3, [r7, #12] 8005f30: 681b ldr r3, [r3, #0] 8005f32: 2210 movs r2, #16 8005f34: 61da str r2, [r3, #28] /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 8005f36: 68fb ldr r3, [r7, #12] 8005f38: 6c5b ldr r3, [r3, #68] @ 0x44 8005f3a: 2204 movs r2, #4 8005f3c: 431a orrs r2, r3 8005f3e: 68fb ldr r3, [r7, #12] 8005f40: 645a str r2, [r3, #68] @ 0x44 /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */ tmpstate = hi2c->State; 8005f42: 2317 movs r3, #23 8005f44: 18fb adds r3, r7, r3 8005f46: 68fa ldr r2, [r7, #12] 8005f48: 2141 movs r1, #65 @ 0x41 8005f4a: 5c52 ldrb r2, [r2, r1] 8005f4c: 701a strb r2, [r3, #0] if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) 8005f4e: 69bb ldr r3, [r7, #24] 8005f50: 2b00 cmp r3, #0 8005f52: d004 beq.n 8005f5e 8005f54: 69ba ldr r2, [r7, #24] 8005f56: 2380 movs r3, #128 @ 0x80 8005f58: 045b lsls r3, r3, #17 8005f5a: 429a cmp r2, r3 8005f5c: d126 bne.n 8005fac { if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) 8005f5e: 2217 movs r2, #23 8005f60: 18bb adds r3, r7, r2 8005f62: 781b ldrb r3, [r3, #0] 8005f64: 2b21 cmp r3, #33 @ 0x21 8005f66: d003 beq.n 8005f70 8005f68: 18bb adds r3, r7, r2 8005f6a: 781b ldrb r3, [r3, #0] 8005f6c: 2b29 cmp r3, #41 @ 0x29 8005f6e: d103 bne.n 8005f78 { hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; 8005f70: 68fb ldr r3, [r7, #12] 8005f72: 2221 movs r2, #33 @ 0x21 8005f74: 631a str r2, [r3, #48] @ 0x30 8005f76: e00b b.n 8005f90 } else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) 8005f78: 2217 movs r2, #23 8005f7a: 18bb adds r3, r7, r2 8005f7c: 781b ldrb r3, [r3, #0] 8005f7e: 2b22 cmp r3, #34 @ 0x22 8005f80: d003 beq.n 8005f8a 8005f82: 18bb adds r3, r7, r2 8005f84: 781b ldrb r3, [r3, #0] 8005f86: 2b2a cmp r3, #42 @ 0x2a 8005f88: d102 bne.n 8005f90 { hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; 8005f8a: 68fb ldr r3, [r7, #12] 8005f8c: 2222 movs r2, #34 @ 0x22 8005f8e: 631a str r2, [r3, #48] @ 0x30 { /* Do nothing */ } /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, hi2c->ErrorCode); 8005f90: 68fb ldr r3, [r7, #12] 8005f92: 6c5a ldr r2, [r3, #68] @ 0x44 8005f94: 68fb ldr r3, [r7, #12] 8005f96: 0011 movs r1, r2 8005f98: 0018 movs r0, r3 8005f9a: f000 fc7f bl 800689c if (treatdmanack == 1U) 8005f9e: e005 b.n 8005fac 8005fa0: e004 b.n 8005fac } } else { /* Only Clear NACK Flag, no DMA treatment is pending */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 8005fa2: 68fb ldr r3, [r7, #12] 8005fa4: 681b ldr r3, [r3, #0] 8005fa6: 2210 movs r2, #16 8005fa8: 61da str r2, [r3, #28] if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) || 8005faa: e00f b.n 8005fcc if (treatdmanack == 1U) 8005fac: 46c0 nop @ (mov r8, r8) if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) || 8005fae: e00d b.n 8005fcc } } else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \ 8005fb0: 68bb ldr r3, [r7, #8] 8005fb2: 2208 movs r2, #8 8005fb4: 4013 ands r3, r2 8005fb6: d009 beq.n 8005fcc (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) 8005fb8: 687b ldr r3, [r7, #4] 8005fba: 2208 movs r2, #8 8005fbc: 4013 ands r3, r2 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \ 8005fbe: d005 beq.n 8005fcc { I2C_ITAddrCplt(hi2c, ITFlags); 8005fc0: 68ba ldr r2, [r7, #8] 8005fc2: 68fb ldr r3, [r7, #12] 8005fc4: 0011 movs r1, r2 8005fc6: 0018 movs r0, r3 8005fc8: f000 f870 bl 80060ac { /* Nothing to do */ } /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8005fcc: 68fb ldr r3, [r7, #12] 8005fce: 2240 movs r2, #64 @ 0x40 8005fd0: 2100 movs r1, #0 8005fd2: 5499 strb r1, [r3, r2] return HAL_OK; 8005fd4: 2300 movs r3, #0 } 8005fd6: 0018 movs r0, r3 8005fd8: 46bd mov sp, r7 8005fda: b008 add sp, #32 8005fdc: bd80 pop {r7, pc} 8005fde: 46c0 nop @ (mov r8, r8) 8005fe0: ffff0000 .word 0xffff0000 08005fe4 : * @retval HAL status */ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) { 8005fe4: b5b0 push {r4, r5, r7, lr} 8005fe6: b086 sub sp, #24 8005fe8: af02 add r7, sp, #8 8005fea: 60f8 str r0, [r7, #12] 8005fec: 000c movs r4, r1 8005fee: 0010 movs r0, r2 8005ff0: 0019 movs r1, r3 8005ff2: 250a movs r5, #10 8005ff4: 197b adds r3, r7, r5 8005ff6: 1c22 adds r2, r4, #0 8005ff8: 801a strh r2, [r3, #0] 8005ffa: 2308 movs r3, #8 8005ffc: 18fb adds r3, r7, r3 8005ffe: 1c02 adds r2, r0, #0 8006000: 801a strh r2, [r3, #0] 8006002: 1dbb adds r3, r7, #6 8006004: 1c0a adds r2, r1, #0 8006006: 801a strh r2, [r3, #0] I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); 8006008: 1dbb adds r3, r7, #6 800600a: 881b ldrh r3, [r3, #0] 800600c: b2da uxtb r2, r3 800600e: 2380 movs r3, #128 @ 0x80 8006010: 045c lsls r4, r3, #17 8006012: 197b adds r3, r7, r5 8006014: 8819 ldrh r1, [r3, #0] 8006016: 68f8 ldr r0, [r7, #12] 8006018: 4b23 ldr r3, [pc, #140] @ (80060a8 ) 800601a: 9300 str r3, [sp, #0] 800601c: 0023 movs r3, r4 800601e: f000 ff83 bl 8006f28 /* Wait until TXIS flag is set */ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) 8006022: 6a7a ldr r2, [r7, #36] @ 0x24 8006024: 6a39 ldr r1, [r7, #32] 8006026: 68fb ldr r3, [r7, #12] 8006028: 0018 movs r0, r3 800602a: f000 fdfb bl 8006c24 800602e: 1e03 subs r3, r0, #0 8006030: d001 beq.n 8006036 { return HAL_ERROR; 8006032: 2301 movs r3, #1 8006034: e033 b.n 800609e } /* If Memory address size is 8Bit */ if (MemAddSize == I2C_MEMADD_SIZE_8BIT) 8006036: 1dbb adds r3, r7, #6 8006038: 881b ldrh r3, [r3, #0] 800603a: 2b01 cmp r3, #1 800603c: d107 bne.n 800604e { /* Send Memory Address */ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); 800603e: 2308 movs r3, #8 8006040: 18fb adds r3, r7, r3 8006042: 881b ldrh r3, [r3, #0] 8006044: b2da uxtb r2, r3 8006046: 68fb ldr r3, [r7, #12] 8006048: 681b ldr r3, [r3, #0] 800604a: 629a str r2, [r3, #40] @ 0x28 800604c: e019 b.n 8006082 } /* If Memory address size is 16Bit */ else { /* Send MSB of Memory Address */ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); 800604e: 2308 movs r3, #8 8006050: 18fb adds r3, r7, r3 8006052: 881b ldrh r3, [r3, #0] 8006054: 0a1b lsrs r3, r3, #8 8006056: b29b uxth r3, r3 8006058: b2da uxtb r2, r3 800605a: 68fb ldr r3, [r7, #12] 800605c: 681b ldr r3, [r3, #0] 800605e: 629a str r2, [r3, #40] @ 0x28 /* Wait until TXIS flag is set */ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) 8006060: 6a7a ldr r2, [r7, #36] @ 0x24 8006062: 6a39 ldr r1, [r7, #32] 8006064: 68fb ldr r3, [r7, #12] 8006066: 0018 movs r0, r3 8006068: f000 fddc bl 8006c24 800606c: 1e03 subs r3, r0, #0 800606e: d001 beq.n 8006074 { return HAL_ERROR; 8006070: 2301 movs r3, #1 8006072: e014 b.n 800609e } /* Send LSB of Memory Address */ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); 8006074: 2308 movs r3, #8 8006076: 18fb adds r3, r7, r3 8006078: 881b ldrh r3, [r3, #0] 800607a: b2da uxtb r2, r3 800607c: 68fb ldr r3, [r7, #12] 800607e: 681b ldr r3, [r3, #0] 8006080: 629a str r2, [r3, #40] @ 0x28 } /* Wait until TCR flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) 8006082: 6a3a ldr r2, [r7, #32] 8006084: 68f8 ldr r0, [r7, #12] 8006086: 6a7b ldr r3, [r7, #36] @ 0x24 8006088: 9300 str r3, [sp, #0] 800608a: 0013 movs r3, r2 800608c: 2200 movs r2, #0 800608e: 2180 movs r1, #128 @ 0x80 8006090: f000 fd70 bl 8006b74 8006094: 1e03 subs r3, r0, #0 8006096: d001 beq.n 800609c { return HAL_ERROR; 8006098: 2301 movs r3, #1 800609a: e000 b.n 800609e } return HAL_OK; 800609c: 2300 movs r3, #0 } 800609e: 0018 movs r0, r3 80060a0: 46bd mov sp, r7 80060a2: b004 add sp, #16 80060a4: bdb0 pop {r4, r5, r7, pc} 80060a6: 46c0 nop @ (mov r8, r8) 80060a8: 80002000 .word 0x80002000 080060ac : * @param hi2c I2C handle. * @param ITFlags Interrupt flags to handle. * @retval None */ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { 80060ac: b5b0 push {r4, r5, r7, lr} 80060ae: b084 sub sp, #16 80060b0: af00 add r7, sp, #0 80060b2: 6078 str r0, [r7, #4] 80060b4: 6039 str r1, [r7, #0] /* Prevent unused argument(s) compilation warning */ UNUSED(ITFlags); /* In case of Listen state, need to inform upper layer of address match code event */ if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) 80060b6: 687b ldr r3, [r7, #4] 80060b8: 2241 movs r2, #65 @ 0x41 80060ba: 5c9b ldrb r3, [r3, r2] 80060bc: b2db uxtb r3, r3 80060be: 001a movs r2, r3 80060c0: 2328 movs r3, #40 @ 0x28 80060c2: 4013 ands r3, r2 80060c4: 2b28 cmp r3, #40 @ 0x28 80060c6: d000 beq.n 80060ca 80060c8: e088 b.n 80061dc { transferdirection = I2C_GET_DIR(hi2c); 80060ca: 687b ldr r3, [r7, #4] 80060cc: 681b ldr r3, [r3, #0] 80060ce: 699b ldr r3, [r3, #24] 80060d0: 0c1b lsrs r3, r3, #16 80060d2: b2da uxtb r2, r3 80060d4: 250f movs r5, #15 80060d6: 197b adds r3, r7, r5 80060d8: 2101 movs r1, #1 80060da: 400a ands r2, r1 80060dc: 701a strb r2, [r3, #0] slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); 80060de: 687b ldr r3, [r7, #4] 80060e0: 681b ldr r3, [r3, #0] 80060e2: 699b ldr r3, [r3, #24] 80060e4: 0c1b lsrs r3, r3, #16 80060e6: b29a uxth r2, r3 80060e8: 200c movs r0, #12 80060ea: 183b adds r3, r7, r0 80060ec: 21fe movs r1, #254 @ 0xfe 80060ee: 400a ands r2, r1 80060f0: 801a strh r2, [r3, #0] ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); 80060f2: 687b ldr r3, [r7, #4] 80060f4: 681b ldr r3, [r3, #0] 80060f6: 689b ldr r3, [r3, #8] 80060f8: b29a uxth r2, r3 80060fa: 240a movs r4, #10 80060fc: 193b adds r3, r7, r4 80060fe: 0592 lsls r2, r2, #22 8006100: 0d92 lsrs r2, r2, #22 8006102: 801a strh r2, [r3, #0] ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); 8006104: 687b ldr r3, [r7, #4] 8006106: 681b ldr r3, [r3, #0] 8006108: 68db ldr r3, [r3, #12] 800610a: b29a uxth r2, r3 800610c: 2308 movs r3, #8 800610e: 18fb adds r3, r7, r3 8006110: 21fe movs r1, #254 @ 0xfe 8006112: 400a ands r2, r1 8006114: 801a strh r2, [r3, #0] /* If 10bits addressing mode is selected */ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) 8006116: 687b ldr r3, [r7, #4] 8006118: 68db ldr r3, [r3, #12] 800611a: 2b02 cmp r3, #2 800611c: d148 bne.n 80061b0 { if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK)) 800611e: 0021 movs r1, r4 8006120: 187b adds r3, r7, r1 8006122: 881b ldrh r3, [r3, #0] 8006124: 09db lsrs r3, r3, #7 8006126: b29a uxth r2, r3 8006128: 183b adds r3, r7, r0 800612a: 881b ldrh r3, [r3, #0] 800612c: 4053 eors r3, r2 800612e: b29b uxth r3, r3 8006130: 001a movs r2, r3 8006132: 2306 movs r3, #6 8006134: 4013 ands r3, r2 8006136: d120 bne.n 800617a { slaveaddrcode = ownadd1code; 8006138: 183b adds r3, r7, r0 800613a: 187a adds r2, r7, r1 800613c: 8812 ldrh r2, [r2, #0] 800613e: 801a strh r2, [r3, #0] hi2c->AddrEventCount++; 8006140: 687b ldr r3, [r7, #4] 8006142: 6c9b ldr r3, [r3, #72] @ 0x48 8006144: 1c5a adds r2, r3, #1 8006146: 687b ldr r3, [r7, #4] 8006148: 649a str r2, [r3, #72] @ 0x48 if (hi2c->AddrEventCount == 2U) 800614a: 687b ldr r3, [r7, #4] 800614c: 6c9b ldr r3, [r3, #72] @ 0x48 800614e: 2b02 cmp r3, #2 8006150: d14c bne.n 80061ec { /* Reset Address Event counter */ hi2c->AddrEventCount = 0U; 8006152: 687b ldr r3, [r7, #4] 8006154: 2200 movs r2, #0 8006156: 649a str r2, [r3, #72] @ 0x48 /* Clear ADDR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); 8006158: 687b ldr r3, [r7, #4] 800615a: 681b ldr r3, [r3, #0] 800615c: 2208 movs r2, #8 800615e: 61da str r2, [r3, #28] /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8006160: 687b ldr r3, [r7, #4] 8006162: 2240 movs r2, #64 @ 0x40 8006164: 2100 movs r1, #0 8006166: 5499 strb r1, [r3, r2] /* Call Slave Addr callback */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); #else HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); 8006168: 183b adds r3, r7, r0 800616a: 881a ldrh r2, [r3, #0] 800616c: 197b adds r3, r7, r5 800616e: 7819 ldrb r1, [r3, #0] 8006170: 687b ldr r3, [r7, #4] 8006172: 0018 movs r0, r3 8006174: f7ff f9d3 bl 800551e __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); /* Process Unlocked */ __HAL_UNLOCK(hi2c); } } 8006178: e038 b.n 80061ec slaveaddrcode = ownadd2code; 800617a: 240c movs r4, #12 800617c: 193b adds r3, r7, r4 800617e: 2208 movs r2, #8 8006180: 18ba adds r2, r7, r2 8006182: 8812 ldrh r2, [r2, #0] 8006184: 801a strh r2, [r3, #0] I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); 8006186: 2380 movs r3, #128 @ 0x80 8006188: 021a lsls r2, r3, #8 800618a: 687b ldr r3, [r7, #4] 800618c: 0011 movs r1, r2 800618e: 0018 movs r0, r3 8006190: f000 ff8e bl 80070b0 __HAL_UNLOCK(hi2c); 8006194: 687b ldr r3, [r7, #4] 8006196: 2240 movs r2, #64 @ 0x40 8006198: 2100 movs r1, #0 800619a: 5499 strb r1, [r3, r2] HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); 800619c: 193b adds r3, r7, r4 800619e: 881a ldrh r2, [r3, #0] 80061a0: 230f movs r3, #15 80061a2: 18fb adds r3, r7, r3 80061a4: 7819 ldrb r1, [r3, #0] 80061a6: 687b ldr r3, [r7, #4] 80061a8: 0018 movs r0, r3 80061aa: f7ff f9b8 bl 800551e } 80061ae: e01d b.n 80061ec I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); 80061b0: 2380 movs r3, #128 @ 0x80 80061b2: 021a lsls r2, r3, #8 80061b4: 687b ldr r3, [r7, #4] 80061b6: 0011 movs r1, r2 80061b8: 0018 movs r0, r3 80061ba: f000 ff79 bl 80070b0 __HAL_UNLOCK(hi2c); 80061be: 687b ldr r3, [r7, #4] 80061c0: 2240 movs r2, #64 @ 0x40 80061c2: 2100 movs r1, #0 80061c4: 5499 strb r1, [r3, r2] HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); 80061c6: 230c movs r3, #12 80061c8: 18fb adds r3, r7, r3 80061ca: 881a ldrh r2, [r3, #0] 80061cc: 230f movs r3, #15 80061ce: 18fb adds r3, r7, r3 80061d0: 7819 ldrb r1, [r3, #0] 80061d2: 687b ldr r3, [r7, #4] 80061d4: 0018 movs r0, r3 80061d6: f7ff f9a2 bl 800551e } 80061da: e007 b.n 80061ec __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); 80061dc: 687b ldr r3, [r7, #4] 80061de: 681b ldr r3, [r3, #0] 80061e0: 2208 movs r2, #8 80061e2: 61da str r2, [r3, #28] __HAL_UNLOCK(hi2c); 80061e4: 687b ldr r3, [r7, #4] 80061e6: 2240 movs r2, #64 @ 0x40 80061e8: 2100 movs r1, #0 80061ea: 5499 strb r1, [r3, r2] } 80061ec: 46c0 nop @ (mov r8, r8) 80061ee: 46bd mov sp, r7 80061f0: b004 add sp, #16 80061f2: bdb0 pop {r4, r5, r7, pc} 080061f4 : * @brief I2C Master sequential complete process. * @param hi2c I2C handle. * @retval None */ static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c) { 80061f4: b580 push {r7, lr} 80061f6: b082 sub sp, #8 80061f8: af00 add r7, sp, #0 80061fa: 6078 str r0, [r7, #4] /* Reset I2C handle mode */ hi2c->Mode = HAL_I2C_MODE_NONE; 80061fc: 687b ldr r3, [r7, #4] 80061fe: 2242 movs r2, #66 @ 0x42 8006200: 2100 movs r1, #0 8006202: 5499 strb r1, [r3, r2] /* No Generate Stop, to permit restart mode */ /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */ if (hi2c->State == HAL_I2C_STATE_BUSY_TX) 8006204: 687b ldr r3, [r7, #4] 8006206: 2241 movs r2, #65 @ 0x41 8006208: 5c9b ldrb r3, [r3, r2] 800620a: b2db uxtb r3, r3 800620c: 2b21 cmp r3, #33 @ 0x21 800620e: d117 bne.n 8006240 { hi2c->State = HAL_I2C_STATE_READY; 8006210: 687b ldr r3, [r7, #4] 8006212: 2241 movs r2, #65 @ 0x41 8006214: 2120 movs r1, #32 8006216: 5499 strb r1, [r3, r2] hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; 8006218: 687b ldr r3, [r7, #4] 800621a: 2211 movs r2, #17 800621c: 631a str r2, [r3, #48] @ 0x30 hi2c->XferISR = NULL; 800621e: 687b ldr r3, [r7, #4] 8006220: 2200 movs r2, #0 8006222: 635a str r2, [r3, #52] @ 0x34 /* Disable Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); 8006224: 687b ldr r3, [r7, #4] 8006226: 2101 movs r1, #1 8006228: 0018 movs r0, r3 800622a: f000 ff41 bl 80070b0 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 800622e: 687b ldr r3, [r7, #4] 8006230: 2240 movs r2, #64 @ 0x40 8006232: 2100 movs r1, #0 8006234: 5499 strb r1, [r3, r2] /* Call the corresponding callback to inform upper layer of End of Transfer */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->MasterTxCpltCallback(hi2c); #else HAL_I2C_MasterTxCpltCallback(hi2c); 8006236: 687b ldr r3, [r7, #4] 8006238: 0018 movs r0, r3 800623a: f7ff f950 bl 80054de hi2c->MasterRxCpltCallback(hi2c); #else HAL_I2C_MasterRxCpltCallback(hi2c); #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } } 800623e: e016 b.n 800626e hi2c->State = HAL_I2C_STATE_READY; 8006240: 687b ldr r3, [r7, #4] 8006242: 2241 movs r2, #65 @ 0x41 8006244: 2120 movs r1, #32 8006246: 5499 strb r1, [r3, r2] hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; 8006248: 687b ldr r3, [r7, #4] 800624a: 2212 movs r2, #18 800624c: 631a str r2, [r3, #48] @ 0x30 hi2c->XferISR = NULL; 800624e: 687b ldr r3, [r7, #4] 8006250: 2200 movs r2, #0 8006252: 635a str r2, [r3, #52] @ 0x34 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); 8006254: 687b ldr r3, [r7, #4] 8006256: 2102 movs r1, #2 8006258: 0018 movs r0, r3 800625a: f000 ff29 bl 80070b0 __HAL_UNLOCK(hi2c); 800625e: 687b ldr r3, [r7, #4] 8006260: 2240 movs r2, #64 @ 0x40 8006262: 2100 movs r1, #0 8006264: 5499 strb r1, [r3, r2] HAL_I2C_MasterRxCpltCallback(hi2c); 8006266: 687b ldr r3, [r7, #4] 8006268: 0018 movs r0, r3 800626a: f7ff f940 bl 80054ee } 800626e: 46c0 nop @ (mov r8, r8) 8006270: 46bd mov sp, r7 8006272: b002 add sp, #8 8006274: bd80 pop {r7, pc} ... 08006278 : * @brief I2C Slave sequential complete process. * @param hi2c I2C handle. * @retval None */ static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c) { 8006278: b580 push {r7, lr} 800627a: b084 sub sp, #16 800627c: af00 add r7, sp, #0 800627e: 6078 str r0, [r7, #4] uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); 8006280: 687b ldr r3, [r7, #4] 8006282: 681b ldr r3, [r3, #0] 8006284: 681b ldr r3, [r3, #0] 8006286: 60fb str r3, [r7, #12] /* Reset I2C handle mode */ hi2c->Mode = HAL_I2C_MODE_NONE; 8006288: 687b ldr r3, [r7, #4] 800628a: 2242 movs r2, #66 @ 0x42 800628c: 2100 movs r1, #0 800628e: 5499 strb r1, [r3, r2] /* If a DMA is ongoing, Update handle size context */ if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) 8006290: 68fa ldr r2, [r7, #12] 8006292: 2380 movs r3, #128 @ 0x80 8006294: 01db lsls r3, r3, #7 8006296: 4013 ands r3, r2 8006298: d008 beq.n 80062ac { /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; 800629a: 687b ldr r3, [r7, #4] 800629c: 681b ldr r3, [r3, #0] 800629e: 681a ldr r2, [r3, #0] 80062a0: 687b ldr r3, [r7, #4] 80062a2: 681b ldr r3, [r3, #0] 80062a4: 4924 ldr r1, [pc, #144] @ (8006338 ) 80062a6: 400a ands r2, r1 80062a8: 601a str r2, [r3, #0] 80062aa: e00c b.n 80062c6 } else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) 80062ac: 68fa ldr r2, [r7, #12] 80062ae: 2380 movs r3, #128 @ 0x80 80062b0: 021b lsls r3, r3, #8 80062b2: 4013 ands r3, r2 80062b4: d007 beq.n 80062c6 { /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; 80062b6: 687b ldr r3, [r7, #4] 80062b8: 681b ldr r3, [r3, #0] 80062ba: 681a ldr r2, [r3, #0] 80062bc: 687b ldr r3, [r7, #4] 80062be: 681b ldr r3, [r3, #0] 80062c0: 491e ldr r1, [pc, #120] @ (800633c ) 80062c2: 400a ands r2, r1 80062c4: 601a str r2, [r3, #0] else { /* Do nothing */ } if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) 80062c6: 687b ldr r3, [r7, #4] 80062c8: 2241 movs r2, #65 @ 0x41 80062ca: 5c9b ldrb r3, [r3, r2] 80062cc: b2db uxtb r3, r3 80062ce: 2b29 cmp r3, #41 @ 0x29 80062d0: d114 bne.n 80062fc { /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ hi2c->State = HAL_I2C_STATE_LISTEN; 80062d2: 687b ldr r3, [r7, #4] 80062d4: 2241 movs r2, #65 @ 0x41 80062d6: 2128 movs r1, #40 @ 0x28 80062d8: 5499 strb r1, [r3, r2] hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; 80062da: 687b ldr r3, [r7, #4] 80062dc: 2221 movs r2, #33 @ 0x21 80062de: 631a str r2, [r3, #48] @ 0x30 /* Disable Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); 80062e0: 687b ldr r3, [r7, #4] 80062e2: 2101 movs r1, #1 80062e4: 0018 movs r0, r3 80062e6: f000 fee3 bl 80070b0 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 80062ea: 687b ldr r3, [r7, #4] 80062ec: 2240 movs r2, #64 @ 0x40 80062ee: 2100 movs r1, #0 80062f0: 5499 strb r1, [r3, r2] /* Call the corresponding callback to inform upper layer of End of Transfer */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->SlaveTxCpltCallback(hi2c); #else HAL_I2C_SlaveTxCpltCallback(hi2c); 80062f2: 687b ldr r3, [r7, #4] 80062f4: 0018 movs r0, r3 80062f6: f7ff f902 bl 80054fe } else { /* Nothing to do */ } } 80062fa: e019 b.n 8006330 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) 80062fc: 687b ldr r3, [r7, #4] 80062fe: 2241 movs r2, #65 @ 0x41 8006300: 5c9b ldrb r3, [r3, r2] 8006302: b2db uxtb r3, r3 8006304: 2b2a cmp r3, #42 @ 0x2a 8006306: d113 bne.n 8006330 hi2c->State = HAL_I2C_STATE_LISTEN; 8006308: 687b ldr r3, [r7, #4] 800630a: 2241 movs r2, #65 @ 0x41 800630c: 2128 movs r1, #40 @ 0x28 800630e: 5499 strb r1, [r3, r2] hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; 8006310: 687b ldr r3, [r7, #4] 8006312: 2222 movs r2, #34 @ 0x22 8006314: 631a str r2, [r3, #48] @ 0x30 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); 8006316: 687b ldr r3, [r7, #4] 8006318: 2102 movs r1, #2 800631a: 0018 movs r0, r3 800631c: f000 fec8 bl 80070b0 __HAL_UNLOCK(hi2c); 8006320: 687b ldr r3, [r7, #4] 8006322: 2240 movs r2, #64 @ 0x40 8006324: 2100 movs r1, #0 8006326: 5499 strb r1, [r3, r2] HAL_I2C_SlaveRxCpltCallback(hi2c); 8006328: 687b ldr r3, [r7, #4] 800632a: 0018 movs r0, r3 800632c: f7ff f8ef bl 800550e } 8006330: 46c0 nop @ (mov r8, r8) 8006332: 46bd mov sp, r7 8006334: b004 add sp, #16 8006336: bd80 pop {r7, pc} 8006338: ffffbfff .word 0xffffbfff 800633c: ffff7fff .word 0xffff7fff 08006340 : * @param hi2c I2C handle. * @param ITFlags Interrupt flags to handle. * @retval None */ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { 8006340: b580 push {r7, lr} 8006342: b086 sub sp, #24 8006344: af00 add r7, sp, #0 8006346: 6078 str r0, [r7, #4] 8006348: 6039 str r1, [r7, #0] uint32_t tmperror; uint32_t tmpITFlags = ITFlags; 800634a: 683b ldr r3, [r7, #0] 800634c: 617b str r3, [r7, #20] __IO uint32_t tmpreg; /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); 800634e: 687b ldr r3, [r7, #4] 8006350: 681b ldr r3, [r3, #0] 8006352: 2220 movs r2, #32 8006354: 61da str r2, [r3, #28] /* Disable Interrupts and Store Previous state */ if (hi2c->State == HAL_I2C_STATE_BUSY_TX) 8006356: 687b ldr r3, [r7, #4] 8006358: 2241 movs r2, #65 @ 0x41 800635a: 5c9b ldrb r3, [r3, r2] 800635c: b2db uxtb r3, r3 800635e: 2b21 cmp r3, #33 @ 0x21 8006360: d108 bne.n 8006374 { I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); 8006362: 687b ldr r3, [r7, #4] 8006364: 2101 movs r1, #1 8006366: 0018 movs r0, r3 8006368: f000 fea2 bl 80070b0 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; 800636c: 687b ldr r3, [r7, #4] 800636e: 2211 movs r2, #17 8006370: 631a str r2, [r3, #48] @ 0x30 8006372: e00d b.n 8006390 } else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) 8006374: 687b ldr r3, [r7, #4] 8006376: 2241 movs r2, #65 @ 0x41 8006378: 5c9b ldrb r3, [r3, r2] 800637a: b2db uxtb r3, r3 800637c: 2b22 cmp r3, #34 @ 0x22 800637e: d107 bne.n 8006390 { I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); 8006380: 687b ldr r3, [r7, #4] 8006382: 2102 movs r1, #2 8006384: 0018 movs r0, r3 8006386: f000 fe93 bl 80070b0 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; 800638a: 687b ldr r3, [r7, #4] 800638c: 2212 movs r2, #18 800638e: 631a str r2, [r3, #48] @ 0x30 { /* Do nothing */ } /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); 8006390: 687b ldr r3, [r7, #4] 8006392: 681b ldr r3, [r3, #0] 8006394: 685a ldr r2, [r3, #4] 8006396: 687b ldr r3, [r7, #4] 8006398: 681b ldr r3, [r3, #0] 800639a: 494e ldr r1, [pc, #312] @ (80064d4 ) 800639c: 400a ands r2, r1 800639e: 605a str r2, [r3, #4] /* Reset handle parameters */ hi2c->XferISR = NULL; 80063a0: 687b ldr r3, [r7, #4] 80063a2: 2200 movs r2, #0 80063a4: 635a str r2, [r3, #52] @ 0x34 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 80063a6: 687b ldr r3, [r7, #4] 80063a8: 4a4b ldr r2, [pc, #300] @ (80064d8 ) 80063aa: 62da str r2, [r3, #44] @ 0x2c if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) 80063ac: 697b ldr r3, [r7, #20] 80063ae: 2210 movs r2, #16 80063b0: 4013 ands r3, r2 80063b2: d009 beq.n 80063c8 { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 80063b4: 687b ldr r3, [r7, #4] 80063b6: 681b ldr r3, [r3, #0] 80063b8: 2210 movs r2, #16 80063ba: 61da str r2, [r3, #28] /* Set acknowledge error code */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 80063bc: 687b ldr r3, [r7, #4] 80063be: 6c5b ldr r3, [r3, #68] @ 0x44 80063c0: 2204 movs r2, #4 80063c2: 431a orrs r2, r3 80063c4: 687b ldr r3, [r7, #4] 80063c6: 645a str r2, [r3, #68] @ 0x44 } /* Fetch Last receive data if any */ if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)) 80063c8: 687b ldr r3, [r7, #4] 80063ca: 2241 movs r2, #65 @ 0x41 80063cc: 5c9b ldrb r3, [r3, r2] 80063ce: b2db uxtb r3, r3 80063d0: 2b60 cmp r3, #96 @ 0x60 80063d2: d109 bne.n 80063e8 80063d4: 697b ldr r3, [r7, #20] 80063d6: 2204 movs r2, #4 80063d8: 4013 ands r3, r2 80063da: d005 beq.n 80063e8 { /* Read data from RXDR */ tmpreg = (uint8_t)hi2c->Instance->RXDR; 80063dc: 687b ldr r3, [r7, #4] 80063de: 681b ldr r3, [r3, #0] 80063e0: 6a5b ldr r3, [r3, #36] @ 0x24 80063e2: b2db uxtb r3, r3 80063e4: 60fb str r3, [r7, #12] UNUSED(tmpreg); 80063e6: 68fb ldr r3, [r7, #12] } /* Flush TX register */ I2C_Flush_TXDR(hi2c); 80063e8: 687b ldr r3, [r7, #4] 80063ea: 0018 movs r0, r3 80063ec: f000 fb81 bl 8006af2 /* Store current volatile hi2c->ErrorCode, misra rule */ tmperror = hi2c->ErrorCode; 80063f0: 687b ldr r3, [r7, #4] 80063f2: 6c5b ldr r3, [r3, #68] @ 0x44 80063f4: 613b str r3, [r7, #16] /* Call the corresponding callback to inform upper layer of End of Transfer */ if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE)) 80063f6: 687b ldr r3, [r7, #4] 80063f8: 2241 movs r2, #65 @ 0x41 80063fa: 5c9b ldrb r3, [r3, r2] 80063fc: b2db uxtb r3, r3 80063fe: 2b60 cmp r3, #96 @ 0x60 8006400: d002 beq.n 8006408 8006402: 693b ldr r3, [r7, #16] 8006404: 2b00 cmp r3, #0 8006406: d007 beq.n 8006418 { /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, hi2c->ErrorCode); 8006408: 687b ldr r3, [r7, #4] 800640a: 6c5a ldr r2, [r3, #68] @ 0x44 800640c: 687b ldr r3, [r7, #4] 800640e: 0011 movs r1, r2 8006410: 0018 movs r0, r3 8006412: f000 fa43 bl 800689c } else { /* Nothing to do */ } } 8006416: e058 b.n 80064ca else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) 8006418: 687b ldr r3, [r7, #4] 800641a: 2241 movs r2, #65 @ 0x41 800641c: 5c9b ldrb r3, [r3, r2] 800641e: b2db uxtb r3, r3 8006420: 2b21 cmp r3, #33 @ 0x21 8006422: d126 bne.n 8006472 hi2c->State = HAL_I2C_STATE_READY; 8006424: 687b ldr r3, [r7, #4] 8006426: 2241 movs r2, #65 @ 0x41 8006428: 2120 movs r1, #32 800642a: 5499 strb r1, [r3, r2] hi2c->PreviousState = I2C_STATE_NONE; 800642c: 687b ldr r3, [r7, #4] 800642e: 2200 movs r2, #0 8006430: 631a str r2, [r3, #48] @ 0x30 if (hi2c->Mode == HAL_I2C_MODE_MEM) 8006432: 687b ldr r3, [r7, #4] 8006434: 2242 movs r2, #66 @ 0x42 8006436: 5c9b ldrb r3, [r3, r2] 8006438: b2db uxtb r3, r3 800643a: 2b40 cmp r3, #64 @ 0x40 800643c: d10c bne.n 8006458 hi2c->Mode = HAL_I2C_MODE_NONE; 800643e: 687b ldr r3, [r7, #4] 8006440: 2242 movs r2, #66 @ 0x42 8006442: 2100 movs r1, #0 8006444: 5499 strb r1, [r3, r2] __HAL_UNLOCK(hi2c); 8006446: 687b ldr r3, [r7, #4] 8006448: 2240 movs r2, #64 @ 0x40 800644a: 2100 movs r1, #0 800644c: 5499 strb r1, [r3, r2] HAL_I2C_MemTxCpltCallback(hi2c); 800644e: 687b ldr r3, [r7, #4] 8006450: 0018 movs r0, r3 8006452: f7ff f87c bl 800554e } 8006456: e038 b.n 80064ca hi2c->Mode = HAL_I2C_MODE_NONE; 8006458: 687b ldr r3, [r7, #4] 800645a: 2242 movs r2, #66 @ 0x42 800645c: 2100 movs r1, #0 800645e: 5499 strb r1, [r3, r2] __HAL_UNLOCK(hi2c); 8006460: 687b ldr r3, [r7, #4] 8006462: 2240 movs r2, #64 @ 0x40 8006464: 2100 movs r1, #0 8006466: 5499 strb r1, [r3, r2] HAL_I2C_MasterTxCpltCallback(hi2c); 8006468: 687b ldr r3, [r7, #4] 800646a: 0018 movs r0, r3 800646c: f7ff f837 bl 80054de } 8006470: e02b b.n 80064ca else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) 8006472: 687b ldr r3, [r7, #4] 8006474: 2241 movs r2, #65 @ 0x41 8006476: 5c9b ldrb r3, [r3, r2] 8006478: b2db uxtb r3, r3 800647a: 2b22 cmp r3, #34 @ 0x22 800647c: d125 bne.n 80064ca hi2c->State = HAL_I2C_STATE_READY; 800647e: 687b ldr r3, [r7, #4] 8006480: 2241 movs r2, #65 @ 0x41 8006482: 2120 movs r1, #32 8006484: 5499 strb r1, [r3, r2] hi2c->PreviousState = I2C_STATE_NONE; 8006486: 687b ldr r3, [r7, #4] 8006488: 2200 movs r2, #0 800648a: 631a str r2, [r3, #48] @ 0x30 if (hi2c->Mode == HAL_I2C_MODE_MEM) 800648c: 687b ldr r3, [r7, #4] 800648e: 2242 movs r2, #66 @ 0x42 8006490: 5c9b ldrb r3, [r3, r2] 8006492: b2db uxtb r3, r3 8006494: 2b40 cmp r3, #64 @ 0x40 8006496: d10c bne.n 80064b2 hi2c->Mode = HAL_I2C_MODE_NONE; 8006498: 687b ldr r3, [r7, #4] 800649a: 2242 movs r2, #66 @ 0x42 800649c: 2100 movs r1, #0 800649e: 5499 strb r1, [r3, r2] __HAL_UNLOCK(hi2c); 80064a0: 687b ldr r3, [r7, #4] 80064a2: 2240 movs r2, #64 @ 0x40 80064a4: 2100 movs r1, #0 80064a6: 5499 strb r1, [r3, r2] HAL_I2C_MemRxCpltCallback(hi2c); 80064a8: 687b ldr r3, [r7, #4] 80064aa: 0018 movs r0, r3 80064ac: f7fd feca bl 8004244 } 80064b0: e00b b.n 80064ca hi2c->Mode = HAL_I2C_MODE_NONE; 80064b2: 687b ldr r3, [r7, #4] 80064b4: 2242 movs r2, #66 @ 0x42 80064b6: 2100 movs r1, #0 80064b8: 5499 strb r1, [r3, r2] __HAL_UNLOCK(hi2c); 80064ba: 687b ldr r3, [r7, #4] 80064bc: 2240 movs r2, #64 @ 0x40 80064be: 2100 movs r1, #0 80064c0: 5499 strb r1, [r3, r2] HAL_I2C_MasterRxCpltCallback(hi2c); 80064c2: 687b ldr r3, [r7, #4] 80064c4: 0018 movs r0, r3 80064c6: f7ff f812 bl 80054ee } 80064ca: 46c0 nop @ (mov r8, r8) 80064cc: 46bd mov sp, r7 80064ce: b006 add sp, #24 80064d0: bd80 pop {r7, pc} 80064d2: 46c0 nop @ (mov r8, r8) 80064d4: fe00e800 .word 0xfe00e800 80064d8: ffff0000 .word 0xffff0000 080064dc : * @param hi2c I2C handle. * @param ITFlags Interrupt flags to handle. * @retval None */ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { 80064dc: b580 push {r7, lr} 80064de: b086 sub sp, #24 80064e0: af00 add r7, sp, #0 80064e2: 6078 str r0, [r7, #4] 80064e4: 6039 str r1, [r7, #0] uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); 80064e6: 687b ldr r3, [r7, #4] 80064e8: 681b ldr r3, [r3, #0] 80064ea: 681b ldr r3, [r3, #0] 80064ec: 613b str r3, [r7, #16] uint32_t tmpITFlags = ITFlags; 80064ee: 683b ldr r3, [r7, #0] 80064f0: 617b str r3, [r7, #20] uint32_t tmpoptions = hi2c->XferOptions; 80064f2: 687b ldr r3, [r7, #4] 80064f4: 6adb ldr r3, [r3, #44] @ 0x2c 80064f6: 60fb str r3, [r7, #12] HAL_I2C_StateTypeDef tmpstate = hi2c->State; 80064f8: 200b movs r0, #11 80064fa: 183b adds r3, r7, r0 80064fc: 687a ldr r2, [r7, #4] 80064fe: 2141 movs r1, #65 @ 0x41 8006500: 5c52 ldrb r2, [r2, r1] 8006502: 701a strb r2, [r3, #0] /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); 8006504: 687b ldr r3, [r7, #4] 8006506: 681b ldr r3, [r3, #0] 8006508: 2220 movs r2, #32 800650a: 61da str r2, [r3, #28] /* Disable Interrupts and Store Previous state */ if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) 800650c: 183b adds r3, r7, r0 800650e: 781b ldrb r3, [r3, #0] 8006510: 2b21 cmp r3, #33 @ 0x21 8006512: d003 beq.n 800651c 8006514: 183b adds r3, r7, r0 8006516: 781b ldrb r3, [r3, #0] 8006518: 2b29 cmp r3, #41 @ 0x29 800651a: d109 bne.n 8006530 { I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); 800651c: 4aac ldr r2, [pc, #688] @ (80067d0 ) 800651e: 687b ldr r3, [r7, #4] 8006520: 0011 movs r1, r2 8006522: 0018 movs r0, r3 8006524: f000 fdc4 bl 80070b0 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; 8006528: 687b ldr r3, [r7, #4] 800652a: 2221 movs r2, #33 @ 0x21 800652c: 631a str r2, [r3, #48] @ 0x30 800652e: e020 b.n 8006572 } else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) 8006530: 220b movs r2, #11 8006532: 18bb adds r3, r7, r2 8006534: 781b ldrb r3, [r3, #0] 8006536: 2b22 cmp r3, #34 @ 0x22 8006538: d003 beq.n 8006542 800653a: 18bb adds r3, r7, r2 800653c: 781b ldrb r3, [r3, #0] 800653e: 2b2a cmp r3, #42 @ 0x2a 8006540: d109 bne.n 8006556 { I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); 8006542: 4aa4 ldr r2, [pc, #656] @ (80067d4 ) 8006544: 687b ldr r3, [r7, #4] 8006546: 0011 movs r1, r2 8006548: 0018 movs r0, r3 800654a: f000 fdb1 bl 80070b0 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; 800654e: 687b ldr r3, [r7, #4] 8006550: 2222 movs r2, #34 @ 0x22 8006552: 631a str r2, [r3, #48] @ 0x30 8006554: e00d b.n 8006572 } else if (tmpstate == HAL_I2C_STATE_LISTEN) 8006556: 230b movs r3, #11 8006558: 18fb adds r3, r7, r3 800655a: 781b ldrb r3, [r3, #0] 800655c: 2b28 cmp r3, #40 @ 0x28 800655e: d108 bne.n 8006572 { I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); 8006560: 4a9d ldr r2, [pc, #628] @ (80067d8 ) 8006562: 687b ldr r3, [r7, #4] 8006564: 0011 movs r1, r2 8006566: 0018 movs r0, r3 8006568: f000 fda2 bl 80070b0 hi2c->PreviousState = I2C_STATE_NONE; 800656c: 687b ldr r3, [r7, #4] 800656e: 2200 movs r2, #0 8006570: 631a str r2, [r3, #48] @ 0x30 { /* Do nothing */ } /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; 8006572: 687b ldr r3, [r7, #4] 8006574: 681b ldr r3, [r3, #0] 8006576: 685a ldr r2, [r3, #4] 8006578: 687b ldr r3, [r7, #4] 800657a: 681b ldr r3, [r3, #0] 800657c: 2180 movs r1, #128 @ 0x80 800657e: 0209 lsls r1, r1, #8 8006580: 430a orrs r2, r1 8006582: 605a str r2, [r3, #4] /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); 8006584: 687b ldr r3, [r7, #4] 8006586: 681b ldr r3, [r3, #0] 8006588: 685a ldr r2, [r3, #4] 800658a: 687b ldr r3, [r7, #4] 800658c: 681b ldr r3, [r3, #0] 800658e: 4993 ldr r1, [pc, #588] @ (80067dc ) 8006590: 400a ands r2, r1 8006592: 605a str r2, [r3, #4] /* Flush TX register */ I2C_Flush_TXDR(hi2c); 8006594: 687b ldr r3, [r7, #4] 8006596: 0018 movs r0, r3 8006598: f000 faab bl 8006af2 /* If a DMA is ongoing, Update handle size context */ if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) 800659c: 693a ldr r2, [r7, #16] 800659e: 2380 movs r3, #128 @ 0x80 80065a0: 01db lsls r3, r3, #7 80065a2: 4013 ands r3, r2 80065a4: d013 beq.n 80065ce { /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; 80065a6: 687b ldr r3, [r7, #4] 80065a8: 681b ldr r3, [r3, #0] 80065aa: 681a ldr r2, [r3, #0] 80065ac: 687b ldr r3, [r7, #4] 80065ae: 681b ldr r3, [r3, #0] 80065b0: 498b ldr r1, [pc, #556] @ (80067e0 ) 80065b2: 400a ands r2, r1 80065b4: 601a str r2, [r3, #0] if (hi2c->hdmatx != NULL) 80065b6: 687b ldr r3, [r7, #4] 80065b8: 6b9b ldr r3, [r3, #56] @ 0x38 80065ba: 2b00 cmp r3, #0 80065bc: d01f beq.n 80065fe { hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx); 80065be: 687b ldr r3, [r7, #4] 80065c0: 6b9b ldr r3, [r3, #56] @ 0x38 80065c2: 681b ldr r3, [r3, #0] 80065c4: 685b ldr r3, [r3, #4] 80065c6: b29a uxth r2, r3 80065c8: 687b ldr r3, [r7, #4] 80065ca: 855a strh r2, [r3, #42] @ 0x2a 80065cc: e017 b.n 80065fe } } else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) 80065ce: 693a ldr r2, [r7, #16] 80065d0: 2380 movs r3, #128 @ 0x80 80065d2: 021b lsls r3, r3, #8 80065d4: 4013 ands r3, r2 80065d6: d012 beq.n 80065fe { /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; 80065d8: 687b ldr r3, [r7, #4] 80065da: 681b ldr r3, [r3, #0] 80065dc: 681a ldr r2, [r3, #0] 80065de: 687b ldr r3, [r7, #4] 80065e0: 681b ldr r3, [r3, #0] 80065e2: 4980 ldr r1, [pc, #512] @ (80067e4 ) 80065e4: 400a ands r2, r1 80065e6: 601a str r2, [r3, #0] if (hi2c->hdmarx != NULL) 80065e8: 687b ldr r3, [r7, #4] 80065ea: 6bdb ldr r3, [r3, #60] @ 0x3c 80065ec: 2b00 cmp r3, #0 80065ee: d006 beq.n 80065fe { hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx); 80065f0: 687b ldr r3, [r7, #4] 80065f2: 6bdb ldr r3, [r3, #60] @ 0x3c 80065f4: 681b ldr r3, [r3, #0] 80065f6: 685b ldr r3, [r3, #4] 80065f8: b29a uxth r2, r3 80065fa: 687b ldr r3, [r7, #4] 80065fc: 855a strh r2, [r3, #42] @ 0x2a { /* Do nothing */ } /* Store Last receive data if any */ if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) 80065fe: 697b ldr r3, [r7, #20] 8006600: 2204 movs r2, #4 8006602: 4013 ands r3, r2 8006604: d020 beq.n 8006648 { /* Remove RXNE flag on temporary variable as read done */ tmpITFlags &= ~I2C_FLAG_RXNE; 8006606: 697b ldr r3, [r7, #20] 8006608: 2204 movs r2, #4 800660a: 4393 bics r3, r2 800660c: 617b str r3, [r7, #20] /* Read data from RXDR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; 800660e: 687b ldr r3, [r7, #4] 8006610: 681b ldr r3, [r3, #0] 8006612: 6a5a ldr r2, [r3, #36] @ 0x24 8006614: 687b ldr r3, [r7, #4] 8006616: 6a5b ldr r3, [r3, #36] @ 0x24 8006618: b2d2 uxtb r2, r2 800661a: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 800661c: 687b ldr r3, [r7, #4] 800661e: 6a5b ldr r3, [r3, #36] @ 0x24 8006620: 1c5a adds r2, r3, #1 8006622: 687b ldr r3, [r7, #4] 8006624: 625a str r2, [r3, #36] @ 0x24 if ((hi2c->XferSize > 0U)) 8006626: 687b ldr r3, [r7, #4] 8006628: 8d1b ldrh r3, [r3, #40] @ 0x28 800662a: 2b00 cmp r3, #0 800662c: d00c beq.n 8006648 { hi2c->XferSize--; 800662e: 687b ldr r3, [r7, #4] 8006630: 8d1b ldrh r3, [r3, #40] @ 0x28 8006632: 3b01 subs r3, #1 8006634: b29a uxth r2, r3 8006636: 687b ldr r3, [r7, #4] 8006638: 851a strh r2, [r3, #40] @ 0x28 hi2c->XferCount--; 800663a: 687b ldr r3, [r7, #4] 800663c: 8d5b ldrh r3, [r3, #42] @ 0x2a 800663e: b29b uxth r3, r3 8006640: 3b01 subs r3, #1 8006642: b29a uxth r2, r3 8006644: 687b ldr r3, [r7, #4] 8006646: 855a strh r2, [r3, #42] @ 0x2a } } /* All data are not transferred, so set error code accordingly */ if (hi2c->XferCount != 0U) 8006648: 687b ldr r3, [r7, #4] 800664a: 8d5b ldrh r3, [r3, #42] @ 0x2a 800664c: b29b uxth r3, r3 800664e: 2b00 cmp r3, #0 8006650: d005 beq.n 800665e { /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 8006652: 687b ldr r3, [r7, #4] 8006654: 6c5b ldr r3, [r3, #68] @ 0x44 8006656: 2204 movs r2, #4 8006658: 431a orrs r2, r3 800665a: 687b ldr r3, [r7, #4] 800665c: 645a str r2, [r3, #68] @ 0x44 } if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ 800665e: 697b ldr r3, [r7, #20] 8006660: 2210 movs r2, #16 8006662: 4013 ands r3, r2 8006664: d04f beq.n 8006706 (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET)) 8006666: 693b ldr r3, [r7, #16] 8006668: 2210 movs r2, #16 800666a: 4013 ands r3, r2 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ 800666c: d04b beq.n 8006706 { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ /* Mean XferCount == 0*/ /* So clear Flag NACKF only */ if (hi2c->XferCount == 0U) 800666e: 687b ldr r3, [r7, #4] 8006670: 8d5b ldrh r3, [r3, #42] @ 0x2a 8006672: b29b uxth r3, r3 8006674: 2b00 cmp r3, #0 8006676: d12d bne.n 80066d4 { if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) 8006678: 687b ldr r3, [r7, #4] 800667a: 2241 movs r2, #65 @ 0x41 800667c: 5c9b ldrb r3, [r3, r2] 800667e: b2db uxtb r3, r3 8006680: 2b28 cmp r3, #40 @ 0x28 8006682: d10b bne.n 800669c 8006684: 68fa ldr r2, [r7, #12] 8006686: 2380 movs r3, #128 @ 0x80 8006688: 049b lsls r3, r3, #18 800668a: 429a cmp r2, r3 800668c: d106 bne.n 800669c /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ { /* Call I2C Listen complete process */ I2C_ITListenCplt(hi2c, tmpITFlags); 800668e: 697a ldr r2, [r7, #20] 8006690: 687b ldr r3, [r7, #4] 8006692: 0011 movs r1, r2 8006694: 0018 movs r0, r3 8006696: f000 f8a9 bl 80067ec 800669a: e034 b.n 8006706 } else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) 800669c: 687b ldr r3, [r7, #4] 800669e: 2241 movs r2, #65 @ 0x41 80066a0: 5c9b ldrb r3, [r3, r2] 80066a2: b2db uxtb r3, r3 80066a4: 2b29 cmp r3, #41 @ 0x29 80066a6: d110 bne.n 80066ca 80066a8: 68fb ldr r3, [r7, #12] 80066aa: 4a4f ldr r2, [pc, #316] @ (80067e8 ) 80066ac: 4293 cmp r3, r2 80066ae: d00c beq.n 80066ca { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 80066b0: 687b ldr r3, [r7, #4] 80066b2: 681b ldr r3, [r3, #0] 80066b4: 2210 movs r2, #16 80066b6: 61da str r2, [r3, #28] /* Flush TX register */ I2C_Flush_TXDR(hi2c); 80066b8: 687b ldr r3, [r7, #4] 80066ba: 0018 movs r0, r3 80066bc: f000 fa19 bl 8006af2 /* Last Byte is Transmitted */ /* Call I2C Slave Sequential complete process */ I2C_ITSlaveSeqCplt(hi2c); 80066c0: 687b ldr r3, [r7, #4] 80066c2: 0018 movs r0, r3 80066c4: f7ff fdd8 bl 8006278 80066c8: e01d b.n 8006706 } else { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 80066ca: 687b ldr r3, [r7, #4] 80066cc: 681b ldr r3, [r3, #0] 80066ce: 2210 movs r2, #16 80066d0: 61da str r2, [r3, #28] 80066d2: e018 b.n 8006706 } else { /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 80066d4: 687b ldr r3, [r7, #4] 80066d6: 681b ldr r3, [r3, #0] 80066d8: 2210 movs r2, #16 80066da: 61da str r2, [r3, #28] /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 80066dc: 687b ldr r3, [r7, #4] 80066de: 6c5b ldr r3, [r3, #68] @ 0x44 80066e0: 2204 movs r2, #4 80066e2: 431a orrs r2, r3 80066e4: 687b ldr r3, [r7, #4] 80066e6: 645a str r2, [r3, #68] @ 0x44 if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) 80066e8: 68fb ldr r3, [r7, #12] 80066ea: 2b00 cmp r3, #0 80066ec: d004 beq.n 80066f8 80066ee: 68fa ldr r2, [r7, #12] 80066f0: 2380 movs r3, #128 @ 0x80 80066f2: 045b lsls r3, r3, #17 80066f4: 429a cmp r2, r3 80066f6: d106 bne.n 8006706 { /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, hi2c->ErrorCode); 80066f8: 687b ldr r3, [r7, #4] 80066fa: 6c5a ldr r2, [r3, #68] @ 0x44 80066fc: 687b ldr r3, [r7, #4] 80066fe: 0011 movs r1, r2 8006700: 0018 movs r0, r3 8006702: f000 f8cb bl 800689c } } } hi2c->Mode = HAL_I2C_MODE_NONE; 8006706: 687b ldr r3, [r7, #4] 8006708: 2242 movs r2, #66 @ 0x42 800670a: 2100 movs r1, #0 800670c: 5499 strb r1, [r3, r2] hi2c->XferISR = NULL; 800670e: 687b ldr r3, [r7, #4] 8006710: 2200 movs r2, #0 8006712: 635a str r2, [r3, #52] @ 0x34 if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) 8006714: 687b ldr r3, [r7, #4] 8006716: 6c5b ldr r3, [r3, #68] @ 0x44 8006718: 2b00 cmp r3, #0 800671a: d013 beq.n 8006744 { /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, hi2c->ErrorCode); 800671c: 687b ldr r3, [r7, #4] 800671e: 6c5a ldr r2, [r3, #68] @ 0x44 8006720: 687b ldr r3, [r7, #4] 8006722: 0011 movs r1, r2 8006724: 0018 movs r0, r3 8006726: f000 f8b9 bl 800689c /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ if (hi2c->State == HAL_I2C_STATE_LISTEN) 800672a: 687b ldr r3, [r7, #4] 800672c: 2241 movs r2, #65 @ 0x41 800672e: 5c9b ldrb r3, [r3, r2] 8006730: b2db uxtb r3, r3 8006732: 2b28 cmp r3, #40 @ 0x28 8006734: d147 bne.n 80067c6 { /* Call I2C Listen complete process */ I2C_ITListenCplt(hi2c, tmpITFlags); 8006736: 697a ldr r2, [r7, #20] 8006738: 687b ldr r3, [r7, #4] 800673a: 0011 movs r1, r2 800673c: 0018 movs r0, r3 800673e: f000 f855 bl 80067ec hi2c->SlaveTxCpltCallback(hi2c); #else HAL_I2C_SlaveTxCpltCallback(hi2c); #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } } 8006742: e040 b.n 80067c6 else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) 8006744: 687b ldr r3, [r7, #4] 8006746: 6adb ldr r3, [r3, #44] @ 0x2c 8006748: 4a27 ldr r2, [pc, #156] @ (80067e8 ) 800674a: 4293 cmp r3, r2 800674c: d016 beq.n 800677c I2C_ITSlaveSeqCplt(hi2c); 800674e: 687b ldr r3, [r7, #4] 8006750: 0018 movs r0, r3 8006752: f7ff fd91 bl 8006278 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 8006756: 687b ldr r3, [r7, #4] 8006758: 4a23 ldr r2, [pc, #140] @ (80067e8 ) 800675a: 62da str r2, [r3, #44] @ 0x2c hi2c->State = HAL_I2C_STATE_READY; 800675c: 687b ldr r3, [r7, #4] 800675e: 2241 movs r2, #65 @ 0x41 8006760: 2120 movs r1, #32 8006762: 5499 strb r1, [r3, r2] hi2c->PreviousState = I2C_STATE_NONE; 8006764: 687b ldr r3, [r7, #4] 8006766: 2200 movs r2, #0 8006768: 631a str r2, [r3, #48] @ 0x30 __HAL_UNLOCK(hi2c); 800676a: 687b ldr r3, [r7, #4] 800676c: 2240 movs r2, #64 @ 0x40 800676e: 2100 movs r1, #0 8006770: 5499 strb r1, [r3, r2] HAL_I2C_ListenCpltCallback(hi2c); 8006772: 687b ldr r3, [r7, #4] 8006774: 0018 movs r0, r3 8006776: f7fe fee2 bl 800553e } 800677a: e024 b.n 80067c6 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) 800677c: 687b ldr r3, [r7, #4] 800677e: 2241 movs r2, #65 @ 0x41 8006780: 5c9b ldrb r3, [r3, r2] 8006782: b2db uxtb r3, r3 8006784: 2b22 cmp r3, #34 @ 0x22 8006786: d10f bne.n 80067a8 hi2c->State = HAL_I2C_STATE_READY; 8006788: 687b ldr r3, [r7, #4] 800678a: 2241 movs r2, #65 @ 0x41 800678c: 2120 movs r1, #32 800678e: 5499 strb r1, [r3, r2] hi2c->PreviousState = I2C_STATE_NONE; 8006790: 687b ldr r3, [r7, #4] 8006792: 2200 movs r2, #0 8006794: 631a str r2, [r3, #48] @ 0x30 __HAL_UNLOCK(hi2c); 8006796: 687b ldr r3, [r7, #4] 8006798: 2240 movs r2, #64 @ 0x40 800679a: 2100 movs r1, #0 800679c: 5499 strb r1, [r3, r2] HAL_I2C_SlaveRxCpltCallback(hi2c); 800679e: 687b ldr r3, [r7, #4] 80067a0: 0018 movs r0, r3 80067a2: f7fe feb4 bl 800550e } 80067a6: e00e b.n 80067c6 hi2c->State = HAL_I2C_STATE_READY; 80067a8: 687b ldr r3, [r7, #4] 80067aa: 2241 movs r2, #65 @ 0x41 80067ac: 2120 movs r1, #32 80067ae: 5499 strb r1, [r3, r2] hi2c->PreviousState = I2C_STATE_NONE; 80067b0: 687b ldr r3, [r7, #4] 80067b2: 2200 movs r2, #0 80067b4: 631a str r2, [r3, #48] @ 0x30 __HAL_UNLOCK(hi2c); 80067b6: 687b ldr r3, [r7, #4] 80067b8: 2240 movs r2, #64 @ 0x40 80067ba: 2100 movs r1, #0 80067bc: 5499 strb r1, [r3, r2] HAL_I2C_SlaveTxCpltCallback(hi2c); 80067be: 687b ldr r3, [r7, #4] 80067c0: 0018 movs r0, r3 80067c2: f7fe fe9c bl 80054fe } 80067c6: 46c0 nop @ (mov r8, r8) 80067c8: 46bd mov sp, r7 80067ca: b006 add sp, #24 80067cc: bd80 pop {r7, pc} 80067ce: 46c0 nop @ (mov r8, r8) 80067d0: 00008001 .word 0x00008001 80067d4: 00008002 .word 0x00008002 80067d8: 00008003 .word 0x00008003 80067dc: fe00e800 .word 0xfe00e800 80067e0: ffffbfff .word 0xffffbfff 80067e4: ffff7fff .word 0xffff7fff 80067e8: ffff0000 .word 0xffff0000 080067ec : * @param hi2c I2C handle. * @param ITFlags Interrupt flags to handle. * @retval None */ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { 80067ec: b580 push {r7, lr} 80067ee: b082 sub sp, #8 80067f0: af00 add r7, sp, #0 80067f2: 6078 str r0, [r7, #4] 80067f4: 6039 str r1, [r7, #0] /* Reset handle parameters */ hi2c->XferOptions = I2C_NO_OPTION_FRAME; 80067f6: 687b ldr r3, [r7, #4] 80067f8: 4a26 ldr r2, [pc, #152] @ (8006894 ) 80067fa: 62da str r2, [r3, #44] @ 0x2c hi2c->PreviousState = I2C_STATE_NONE; 80067fc: 687b ldr r3, [r7, #4] 80067fe: 2200 movs r2, #0 8006800: 631a str r2, [r3, #48] @ 0x30 hi2c->State = HAL_I2C_STATE_READY; 8006802: 687b ldr r3, [r7, #4] 8006804: 2241 movs r2, #65 @ 0x41 8006806: 2120 movs r1, #32 8006808: 5499 strb r1, [r3, r2] hi2c->Mode = HAL_I2C_MODE_NONE; 800680a: 687b ldr r3, [r7, #4] 800680c: 2242 movs r2, #66 @ 0x42 800680e: 2100 movs r1, #0 8006810: 5499 strb r1, [r3, r2] hi2c->XferISR = NULL; 8006812: 687b ldr r3, [r7, #4] 8006814: 2200 movs r2, #0 8006816: 635a str r2, [r3, #52] @ 0x34 /* Store Last receive data if any */ if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET) 8006818: 683b ldr r3, [r7, #0] 800681a: 2204 movs r2, #4 800681c: 4013 ands r3, r2 800681e: d022 beq.n 8006866 { /* Read data from RXDR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; 8006820: 687b ldr r3, [r7, #4] 8006822: 681b ldr r3, [r3, #0] 8006824: 6a5a ldr r2, [r3, #36] @ 0x24 8006826: 687b ldr r3, [r7, #4] 8006828: 6a5b ldr r3, [r3, #36] @ 0x24 800682a: b2d2 uxtb r2, r2 800682c: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 800682e: 687b ldr r3, [r7, #4] 8006830: 6a5b ldr r3, [r3, #36] @ 0x24 8006832: 1c5a adds r2, r3, #1 8006834: 687b ldr r3, [r7, #4] 8006836: 625a str r2, [r3, #36] @ 0x24 if ((hi2c->XferSize > 0U)) 8006838: 687b ldr r3, [r7, #4] 800683a: 8d1b ldrh r3, [r3, #40] @ 0x28 800683c: 2b00 cmp r3, #0 800683e: d012 beq.n 8006866 { hi2c->XferSize--; 8006840: 687b ldr r3, [r7, #4] 8006842: 8d1b ldrh r3, [r3, #40] @ 0x28 8006844: 3b01 subs r3, #1 8006846: b29a uxth r2, r3 8006848: 687b ldr r3, [r7, #4] 800684a: 851a strh r2, [r3, #40] @ 0x28 hi2c->XferCount--; 800684c: 687b ldr r3, [r7, #4] 800684e: 8d5b ldrh r3, [r3, #42] @ 0x2a 8006850: b29b uxth r3, r3 8006852: 3b01 subs r3, #1 8006854: b29a uxth r2, r3 8006856: 687b ldr r3, [r7, #4] 8006858: 855a strh r2, [r3, #42] @ 0x2a /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 800685a: 687b ldr r3, [r7, #4] 800685c: 6c5b ldr r3, [r3, #68] @ 0x44 800685e: 2204 movs r2, #4 8006860: 431a orrs r2, r3 8006862: 687b ldr r3, [r7, #4] 8006864: 645a str r2, [r3, #68] @ 0x44 } } /* Disable all Interrupts*/ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); 8006866: 4a0c ldr r2, [pc, #48] @ (8006898 ) 8006868: 687b ldr r3, [r7, #4] 800686a: 0011 movs r1, r2 800686c: 0018 movs r0, r3 800686e: f000 fc1f bl 80070b0 /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 8006872: 687b ldr r3, [r7, #4] 8006874: 681b ldr r3, [r3, #0] 8006876: 2210 movs r2, #16 8006878: 61da str r2, [r3, #28] /* Process Unlocked */ __HAL_UNLOCK(hi2c); 800687a: 687b ldr r3, [r7, #4] 800687c: 2240 movs r2, #64 @ 0x40 800687e: 2100 movs r1, #0 8006880: 5499 strb r1, [r3, r2] /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->ListenCpltCallback(hi2c); #else HAL_I2C_ListenCpltCallback(hi2c); 8006882: 687b ldr r3, [r7, #4] 8006884: 0018 movs r0, r3 8006886: f7fe fe5a bl 800553e #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } 800688a: 46c0 nop @ (mov r8, r8) 800688c: 46bd mov sp, r7 800688e: b002 add sp, #8 8006890: bd80 pop {r7, pc} 8006892: 46c0 nop @ (mov r8, r8) 8006894: ffff0000 .word 0xffff0000 8006898: 00008003 .word 0x00008003 0800689c : * @param hi2c I2C handle. * @param ErrorCode Error code to handle. * @retval None */ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) { 800689c: b580 push {r7, lr} 800689e: b084 sub sp, #16 80068a0: af00 add r7, sp, #0 80068a2: 6078 str r0, [r7, #4] 80068a4: 6039 str r1, [r7, #0] HAL_I2C_StateTypeDef tmpstate = hi2c->State; 80068a6: 200f movs r0, #15 80068a8: 183b adds r3, r7, r0 80068aa: 687a ldr r2, [r7, #4] 80068ac: 2141 movs r1, #65 @ 0x41 80068ae: 5c52 ldrb r2, [r2, r1] 80068b0: 701a strb r2, [r3, #0] uint32_t tmppreviousstate; /* Reset handle parameters */ hi2c->Mode = HAL_I2C_MODE_NONE; 80068b2: 687b ldr r3, [r7, #4] 80068b4: 2242 movs r2, #66 @ 0x42 80068b6: 2100 movs r1, #0 80068b8: 5499 strb r1, [r3, r2] hi2c->XferOptions = I2C_NO_OPTION_FRAME; 80068ba: 687b ldr r3, [r7, #4] 80068bc: 4a72 ldr r2, [pc, #456] @ (8006a88 ) 80068be: 62da str r2, [r3, #44] @ 0x2c hi2c->XferCount = 0U; 80068c0: 687b ldr r3, [r7, #4] 80068c2: 2200 movs r2, #0 80068c4: 855a strh r2, [r3, #42] @ 0x2a /* Set new error code */ hi2c->ErrorCode |= ErrorCode; 80068c6: 687b ldr r3, [r7, #4] 80068c8: 6c5a ldr r2, [r3, #68] @ 0x44 80068ca: 683b ldr r3, [r7, #0] 80068cc: 431a orrs r2, r3 80068ce: 687b ldr r3, [r7, #4] 80068d0: 645a str r2, [r3, #68] @ 0x44 /* Disable Interrupts */ if ((tmpstate == HAL_I2C_STATE_LISTEN) || 80068d2: 183b adds r3, r7, r0 80068d4: 781b ldrb r3, [r3, #0] 80068d6: 2b28 cmp r3, #40 @ 0x28 80068d8: d007 beq.n 80068ea 80068da: 183b adds r3, r7, r0 80068dc: 781b ldrb r3, [r3, #0] 80068de: 2b29 cmp r3, #41 @ 0x29 80068e0: d003 beq.n 80068ea (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) || 80068e2: 183b adds r3, r7, r0 80068e4: 781b ldrb r3, [r3, #0] 80068e6: 2b2a cmp r3, #42 @ 0x2a 80068e8: d10c bne.n 8006904 (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) { /* Disable all interrupts, except interrupts related to LISTEN state */ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT); 80068ea: 687b ldr r3, [r7, #4] 80068ec: 2103 movs r1, #3 80068ee: 0018 movs r0, r3 80068f0: f000 fbde bl 80070b0 /* keep HAL_I2C_STATE_LISTEN if set */ hi2c->State = HAL_I2C_STATE_LISTEN; 80068f4: 687b ldr r3, [r7, #4] 80068f6: 2241 movs r2, #65 @ 0x41 80068f8: 2128 movs r1, #40 @ 0x28 80068fa: 5499 strb r1, [r3, r2] hi2c->XferISR = I2C_Slave_ISR_IT; 80068fc: 687b ldr r3, [r7, #4] 80068fe: 4a63 ldr r2, [pc, #396] @ (8006a8c ) 8006900: 635a str r2, [r3, #52] @ 0x34 8006902: e032 b.n 800696a } else { /* Disable all interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); 8006904: 4a62 ldr r2, [pc, #392] @ (8006a90 ) 8006906: 687b ldr r3, [r7, #4] 8006908: 0011 movs r1, r2 800690a: 0018 movs r0, r3 800690c: f000 fbd0 bl 80070b0 /* Flush TX register */ I2C_Flush_TXDR(hi2c); 8006910: 687b ldr r3, [r7, #4] 8006912: 0018 movs r0, r3 8006914: f000 f8ed bl 8006af2 /* If state is an abort treatment on going, don't change state */ /* This change will be do later */ if (hi2c->State != HAL_I2C_STATE_ABORT) 8006918: 687b ldr r3, [r7, #4] 800691a: 2241 movs r2, #65 @ 0x41 800691c: 5c9b ldrb r3, [r3, r2] 800691e: b2db uxtb r3, r3 8006920: 2b60 cmp r3, #96 @ 0x60 8006922: d01f beq.n 8006964 { /* Set HAL_I2C_STATE_READY */ hi2c->State = HAL_I2C_STATE_READY; 8006924: 687b ldr r3, [r7, #4] 8006926: 2241 movs r2, #65 @ 0x41 8006928: 2120 movs r1, #32 800692a: 5499 strb r1, [r3, r2] /* Check if a STOPF is detected */ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) 800692c: 687b ldr r3, [r7, #4] 800692e: 681b ldr r3, [r3, #0] 8006930: 699b ldr r3, [r3, #24] 8006932: 2220 movs r2, #32 8006934: 4013 ands r3, r2 8006936: 2b20 cmp r3, #32 8006938: d114 bne.n 8006964 { if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) 800693a: 687b ldr r3, [r7, #4] 800693c: 681b ldr r3, [r3, #0] 800693e: 699b ldr r3, [r3, #24] 8006940: 2210 movs r2, #16 8006942: 4013 ands r3, r2 8006944: 2b10 cmp r3, #16 8006946: d109 bne.n 800695c { __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 8006948: 687b ldr r3, [r7, #4] 800694a: 681b ldr r3, [r3, #0] 800694c: 2210 movs r2, #16 800694e: 61da str r2, [r3, #28] hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 8006950: 687b ldr r3, [r7, #4] 8006952: 6c5b ldr r3, [r3, #68] @ 0x44 8006954: 2204 movs r2, #4 8006956: 431a orrs r2, r3 8006958: 687b ldr r3, [r7, #4] 800695a: 645a str r2, [r3, #68] @ 0x44 } /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); 800695c: 687b ldr r3, [r7, #4] 800695e: 681b ldr r3, [r3, #0] 8006960: 2220 movs r2, #32 8006962: 61da str r2, [r3, #28] } } hi2c->XferISR = NULL; 8006964: 687b ldr r3, [r7, #4] 8006966: 2200 movs r2, #0 8006968: 635a str r2, [r3, #52] @ 0x34 } /* Abort DMA TX transfer if any */ tmppreviousstate = hi2c->PreviousState; 800696a: 687b ldr r3, [r7, #4] 800696c: 6b1b ldr r3, [r3, #48] @ 0x30 800696e: 60bb str r3, [r7, #8] if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \ 8006970: 687b ldr r3, [r7, #4] 8006972: 6b9b ldr r3, [r3, #56] @ 0x38 8006974: 2b00 cmp r3, #0 8006976: d03b beq.n 80069f0 8006978: 68bb ldr r3, [r7, #8] 800697a: 2b11 cmp r3, #17 800697c: d002 beq.n 8006984 800697e: 68bb ldr r3, [r7, #8] 8006980: 2b21 cmp r3, #33 @ 0x21 8006982: d135 bne.n 80069f0 (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) { if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) 8006984: 687b ldr r3, [r7, #4] 8006986: 681b ldr r3, [r3, #0] 8006988: 681a ldr r2, [r3, #0] 800698a: 2380 movs r3, #128 @ 0x80 800698c: 01db lsls r3, r3, #7 800698e: 401a ands r2, r3 8006990: 2380 movs r3, #128 @ 0x80 8006992: 01db lsls r3, r3, #7 8006994: 429a cmp r2, r3 8006996: d107 bne.n 80069a8 { hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; 8006998: 687b ldr r3, [r7, #4] 800699a: 681b ldr r3, [r3, #0] 800699c: 681a ldr r2, [r3, #0] 800699e: 687b ldr r3, [r7, #4] 80069a0: 681b ldr r3, [r3, #0] 80069a2: 493c ldr r1, [pc, #240] @ (8006a94 ) 80069a4: 400a ands r2, r1 80069a6: 601a str r2, [r3, #0] } if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) 80069a8: 687b ldr r3, [r7, #4] 80069aa: 6b9b ldr r3, [r3, #56] @ 0x38 80069ac: 0018 movs r0, r3 80069ae: f7fe f827 bl 8004a00 80069b2: 0003 movs r3, r0 80069b4: 2b01 cmp r3, #1 80069b6: d016 beq.n 80069e6 { /* Set the I2C DMA Abort callback : will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; 80069b8: 687b ldr r3, [r7, #4] 80069ba: 6b9b ldr r3, [r3, #56] @ 0x38 80069bc: 4a36 ldr r2, [pc, #216] @ (8006a98 ) 80069be: 639a str r2, [r3, #56] @ 0x38 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 80069c0: 687b ldr r3, [r7, #4] 80069c2: 2240 movs r2, #64 @ 0x40 80069c4: 2100 movs r1, #0 80069c6: 5499 strb r1, [r3, r2] /* Abort DMA TX */ if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) 80069c8: 687b ldr r3, [r7, #4] 80069ca: 6b9b ldr r3, [r3, #56] @ 0x38 80069cc: 0018 movs r0, r3 80069ce: f7fd ffad bl 800492c 80069d2: 1e03 subs r3, r0, #0 80069d4: d051 beq.n 8006a7a { /* Call Directly XferAbortCallback function in case of error */ hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); 80069d6: 687b ldr r3, [r7, #4] 80069d8: 6b9b ldr r3, [r3, #56] @ 0x38 80069da: 6b9a ldr r2, [r3, #56] @ 0x38 80069dc: 687b ldr r3, [r7, #4] 80069de: 6b9b ldr r3, [r3, #56] @ 0x38 80069e0: 0018 movs r0, r3 80069e2: 4790 blx r2 if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) 80069e4: e049 b.n 8006a7a } } else { I2C_TreatErrorCallback(hi2c); 80069e6: 687b ldr r3, [r7, #4] 80069e8: 0018 movs r0, r3 80069ea: f000 f859 bl 8006aa0 if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) 80069ee: e044 b.n 8006a7a } } /* Abort DMA RX transfer if any */ else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \ 80069f0: 687b ldr r3, [r7, #4] 80069f2: 6bdb ldr r3, [r3, #60] @ 0x3c 80069f4: 2b00 cmp r3, #0 80069f6: d03b beq.n 8006a70 80069f8: 68bb ldr r3, [r7, #8] 80069fa: 2b12 cmp r3, #18 80069fc: d002 beq.n 8006a04 80069fe: 68bb ldr r3, [r7, #8] 8006a00: 2b22 cmp r3, #34 @ 0x22 8006a02: d135 bne.n 8006a70 (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX))) { if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) 8006a04: 687b ldr r3, [r7, #4] 8006a06: 681b ldr r3, [r3, #0] 8006a08: 681a ldr r2, [r3, #0] 8006a0a: 2380 movs r3, #128 @ 0x80 8006a0c: 021b lsls r3, r3, #8 8006a0e: 401a ands r2, r3 8006a10: 2380 movs r3, #128 @ 0x80 8006a12: 021b lsls r3, r3, #8 8006a14: 429a cmp r2, r3 8006a16: d107 bne.n 8006a28 { hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; 8006a18: 687b ldr r3, [r7, #4] 8006a1a: 681b ldr r3, [r3, #0] 8006a1c: 681a ldr r2, [r3, #0] 8006a1e: 687b ldr r3, [r7, #4] 8006a20: 681b ldr r3, [r3, #0] 8006a22: 491e ldr r1, [pc, #120] @ (8006a9c ) 8006a24: 400a ands r2, r1 8006a26: 601a str r2, [r3, #0] } if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) 8006a28: 687b ldr r3, [r7, #4] 8006a2a: 6bdb ldr r3, [r3, #60] @ 0x3c 8006a2c: 0018 movs r0, r3 8006a2e: f7fd ffe7 bl 8004a00 8006a32: 0003 movs r3, r0 8006a34: 2b01 cmp r3, #1 8006a36: d016 beq.n 8006a66 { /* Set the I2C DMA Abort callback : will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; 8006a38: 687b ldr r3, [r7, #4] 8006a3a: 6bdb ldr r3, [r3, #60] @ 0x3c 8006a3c: 4a16 ldr r2, [pc, #88] @ (8006a98 ) 8006a3e: 639a str r2, [r3, #56] @ 0x38 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8006a40: 687b ldr r3, [r7, #4] 8006a42: 2240 movs r2, #64 @ 0x40 8006a44: 2100 movs r1, #0 8006a46: 5499 strb r1, [r3, r2] /* Abort DMA RX */ if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) 8006a48: 687b ldr r3, [r7, #4] 8006a4a: 6bdb ldr r3, [r3, #60] @ 0x3c 8006a4c: 0018 movs r0, r3 8006a4e: f7fd ff6d bl 800492c 8006a52: 1e03 subs r3, r0, #0 8006a54: d013 beq.n 8006a7e { /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); 8006a56: 687b ldr r3, [r7, #4] 8006a58: 6bdb ldr r3, [r3, #60] @ 0x3c 8006a5a: 6b9a ldr r2, [r3, #56] @ 0x38 8006a5c: 687b ldr r3, [r7, #4] 8006a5e: 6bdb ldr r3, [r3, #60] @ 0x3c 8006a60: 0018 movs r0, r3 8006a62: 4790 blx r2 if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) 8006a64: e00b b.n 8006a7e } } else { I2C_TreatErrorCallback(hi2c); 8006a66: 687b ldr r3, [r7, #4] 8006a68: 0018 movs r0, r3 8006a6a: f000 f819 bl 8006aa0 if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) 8006a6e: e006 b.n 8006a7e } } else { I2C_TreatErrorCallback(hi2c); 8006a70: 687b ldr r3, [r7, #4] 8006a72: 0018 movs r0, r3 8006a74: f000 f814 bl 8006aa0 } } 8006a78: e002 b.n 8006a80 if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) 8006a7a: 46c0 nop @ (mov r8, r8) 8006a7c: e000 b.n 8006a80 if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) 8006a7e: 46c0 nop @ (mov r8, r8) } 8006a80: 46c0 nop @ (mov r8, r8) 8006a82: 46bd mov sp, r7 8006a84: b004 add sp, #16 8006a86: bd80 pop {r7, pc} 8006a88: ffff0000 .word 0xffff0000 8006a8c: 080057c5 .word 0x080057c5 8006a90: 00008003 .word 0x00008003 8006a94: ffffbfff .word 0xffffbfff 8006a98: 08006b37 .word 0x08006b37 8006a9c: ffff7fff .word 0xffff7fff 08006aa0 : * @brief I2C Error callback treatment. * @param hi2c I2C handle. * @retval None */ static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c) { 8006aa0: b580 push {r7, lr} 8006aa2: b082 sub sp, #8 8006aa4: af00 add r7, sp, #0 8006aa6: 6078 str r0, [r7, #4] if (hi2c->State == HAL_I2C_STATE_ABORT) 8006aa8: 687b ldr r3, [r7, #4] 8006aaa: 2241 movs r2, #65 @ 0x41 8006aac: 5c9b ldrb r3, [r3, r2] 8006aae: b2db uxtb r3, r3 8006ab0: 2b60 cmp r3, #96 @ 0x60 8006ab2: d10f bne.n 8006ad4 { hi2c->State = HAL_I2C_STATE_READY; 8006ab4: 687b ldr r3, [r7, #4] 8006ab6: 2241 movs r2, #65 @ 0x41 8006ab8: 2120 movs r1, #32 8006aba: 5499 strb r1, [r3, r2] hi2c->PreviousState = I2C_STATE_NONE; 8006abc: 687b ldr r3, [r7, #4] 8006abe: 2200 movs r2, #0 8006ac0: 631a str r2, [r3, #48] @ 0x30 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8006ac2: 687b ldr r3, [r7, #4] 8006ac4: 2240 movs r2, #64 @ 0x40 8006ac6: 2100 movs r1, #0 8006ac8: 5499 strb r1, [r3, r2] /* Call the corresponding callback to inform upper layer of End of Transfer */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->AbortCpltCallback(hi2c); #else HAL_I2C_AbortCpltCallback(hi2c); 8006aca: 687b ldr r3, [r7, #4] 8006acc: 0018 movs r0, r3 8006ace: f7fe fd4e bl 800556e hi2c->ErrorCallback(hi2c); #else HAL_I2C_ErrorCallback(hi2c); #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } } 8006ad2: e00a b.n 8006aea hi2c->PreviousState = I2C_STATE_NONE; 8006ad4: 687b ldr r3, [r7, #4] 8006ad6: 2200 movs r2, #0 8006ad8: 631a str r2, [r3, #48] @ 0x30 __HAL_UNLOCK(hi2c); 8006ada: 687b ldr r3, [r7, #4] 8006adc: 2240 movs r2, #64 @ 0x40 8006ade: 2100 movs r1, #0 8006ae0: 5499 strb r1, [r3, r2] HAL_I2C_ErrorCallback(hi2c); 8006ae2: 687b ldr r3, [r7, #4] 8006ae4: 0018 movs r0, r3 8006ae6: f7fe fd3a bl 800555e } 8006aea: 46c0 nop @ (mov r8, r8) 8006aec: 46bd mov sp, r7 8006aee: b002 add sp, #8 8006af0: bd80 pop {r7, pc} 08006af2 : * @brief I2C Tx data register flush process. * @param hi2c I2C handle. * @retval None */ static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) { 8006af2: b580 push {r7, lr} 8006af4: b082 sub sp, #8 8006af6: af00 add r7, sp, #0 8006af8: 6078 str r0, [r7, #4] /* If a pending TXIS flag is set */ /* Write a dummy data in TXDR to clear it */ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) 8006afa: 687b ldr r3, [r7, #4] 8006afc: 681b ldr r3, [r3, #0] 8006afe: 699b ldr r3, [r3, #24] 8006b00: 2202 movs r2, #2 8006b02: 4013 ands r3, r2 8006b04: 2b02 cmp r3, #2 8006b06: d103 bne.n 8006b10 { hi2c->Instance->TXDR = 0x00U; 8006b08: 687b ldr r3, [r7, #4] 8006b0a: 681b ldr r3, [r3, #0] 8006b0c: 2200 movs r2, #0 8006b0e: 629a str r2, [r3, #40] @ 0x28 } /* Flush TX register if not empty */ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) 8006b10: 687b ldr r3, [r7, #4] 8006b12: 681b ldr r3, [r3, #0] 8006b14: 699b ldr r3, [r3, #24] 8006b16: 2201 movs r2, #1 8006b18: 4013 ands r3, r2 8006b1a: 2b01 cmp r3, #1 8006b1c: d007 beq.n 8006b2e { __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); 8006b1e: 687b ldr r3, [r7, #4] 8006b20: 681b ldr r3, [r3, #0] 8006b22: 699a ldr r2, [r3, #24] 8006b24: 687b ldr r3, [r7, #4] 8006b26: 681b ldr r3, [r3, #0] 8006b28: 2101 movs r1, #1 8006b2a: 430a orrs r2, r1 8006b2c: 619a str r2, [r3, #24] } } 8006b2e: 46c0 nop @ (mov r8, r8) 8006b30: 46bd mov sp, r7 8006b32: b002 add sp, #8 8006b34: bd80 pop {r7, pc} 08006b36 : * (To be called at end of DMA Abort procedure). * @param hdma DMA handle. * @retval None */ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) { 8006b36: b580 push {r7, lr} 8006b38: b084 sub sp, #16 8006b3a: af00 add r7, sp, #0 8006b3c: 6078 str r0, [r7, #4] /* Derogation MISRAC2012-Rule-11.5 */ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); 8006b3e: 687b ldr r3, [r7, #4] 8006b40: 6a9b ldr r3, [r3, #40] @ 0x28 8006b42: 60fb str r3, [r7, #12] /* Reset AbortCpltCallback */ if (hi2c->hdmatx != NULL) 8006b44: 68fb ldr r3, [r7, #12] 8006b46: 6b9b ldr r3, [r3, #56] @ 0x38 8006b48: 2b00 cmp r3, #0 8006b4a: d003 beq.n 8006b54 { hi2c->hdmatx->XferAbortCallback = NULL; 8006b4c: 68fb ldr r3, [r7, #12] 8006b4e: 6b9b ldr r3, [r3, #56] @ 0x38 8006b50: 2200 movs r2, #0 8006b52: 639a str r2, [r3, #56] @ 0x38 } if (hi2c->hdmarx != NULL) 8006b54: 68fb ldr r3, [r7, #12] 8006b56: 6bdb ldr r3, [r3, #60] @ 0x3c 8006b58: 2b00 cmp r3, #0 8006b5a: d003 beq.n 8006b64 { hi2c->hdmarx->XferAbortCallback = NULL; 8006b5c: 68fb ldr r3, [r7, #12] 8006b5e: 6bdb ldr r3, [r3, #60] @ 0x3c 8006b60: 2200 movs r2, #0 8006b62: 639a str r2, [r3, #56] @ 0x38 } I2C_TreatErrorCallback(hi2c); 8006b64: 68fb ldr r3, [r7, #12] 8006b66: 0018 movs r0, r3 8006b68: f7ff ff9a bl 8006aa0 } 8006b6c: 46c0 nop @ (mov r8, r8) 8006b6e: 46bd mov sp, r7 8006b70: b004 add sp, #16 8006b72: bd80 pop {r7, pc} 08006b74 : * @param Tickstart Tick start value * @retval HAL status */ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) { 8006b74: b580 push {r7, lr} 8006b76: b084 sub sp, #16 8006b78: af00 add r7, sp, #0 8006b7a: 60f8 str r0, [r7, #12] 8006b7c: 60b9 str r1, [r7, #8] 8006b7e: 603b str r3, [r7, #0] 8006b80: 1dfb adds r3, r7, #7 8006b82: 701a strb r2, [r3, #0] while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) 8006b84: e03a b.n 8006bfc { /* Check if an error is detected */ if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) 8006b86: 69ba ldr r2, [r7, #24] 8006b88: 6839 ldr r1, [r7, #0] 8006b8a: 68fb ldr r3, [r7, #12] 8006b8c: 0018 movs r0, r3 8006b8e: f000 f8d3 bl 8006d38 8006b92: 1e03 subs r3, r0, #0 8006b94: d001 beq.n 8006b9a { return HAL_ERROR; 8006b96: 2301 movs r3, #1 8006b98: e040 b.n 8006c1c } /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 8006b9a: 683b ldr r3, [r7, #0] 8006b9c: 3301 adds r3, #1 8006b9e: d02d beq.n 8006bfc { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 8006ba0: f7fd fdb8 bl 8004714 8006ba4: 0002 movs r2, r0 8006ba6: 69bb ldr r3, [r7, #24] 8006ba8: 1ad3 subs r3, r2, r3 8006baa: 683a ldr r2, [r7, #0] 8006bac: 429a cmp r2, r3 8006bae: d302 bcc.n 8006bb6 8006bb0: 683b ldr r3, [r7, #0] 8006bb2: 2b00 cmp r3, #0 8006bb4: d122 bne.n 8006bfc { if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)) 8006bb6: 68fb ldr r3, [r7, #12] 8006bb8: 681b ldr r3, [r3, #0] 8006bba: 699b ldr r3, [r3, #24] 8006bbc: 68ba ldr r2, [r7, #8] 8006bbe: 4013 ands r3, r2 8006bc0: 68ba ldr r2, [r7, #8] 8006bc2: 1ad3 subs r3, r2, r3 8006bc4: 425a negs r2, r3 8006bc6: 4153 adcs r3, r2 8006bc8: b2db uxtb r3, r3 8006bca: 001a movs r2, r3 8006bcc: 1dfb adds r3, r7, #7 8006bce: 781b ldrb r3, [r3, #0] 8006bd0: 429a cmp r2, r3 8006bd2: d113 bne.n 8006bfc { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 8006bd4: 68fb ldr r3, [r7, #12] 8006bd6: 6c5b ldr r3, [r3, #68] @ 0x44 8006bd8: 2220 movs r2, #32 8006bda: 431a orrs r2, r3 8006bdc: 68fb ldr r3, [r7, #12] 8006bde: 645a str r2, [r3, #68] @ 0x44 hi2c->State = HAL_I2C_STATE_READY; 8006be0: 68fb ldr r3, [r7, #12] 8006be2: 2241 movs r2, #65 @ 0x41 8006be4: 2120 movs r1, #32 8006be6: 5499 strb r1, [r3, r2] hi2c->Mode = HAL_I2C_MODE_NONE; 8006be8: 68fb ldr r3, [r7, #12] 8006bea: 2242 movs r2, #66 @ 0x42 8006bec: 2100 movs r1, #0 8006bee: 5499 strb r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8006bf0: 68fb ldr r3, [r7, #12] 8006bf2: 2240 movs r2, #64 @ 0x40 8006bf4: 2100 movs r1, #0 8006bf6: 5499 strb r1, [r3, r2] return HAL_ERROR; 8006bf8: 2301 movs r3, #1 8006bfa: e00f b.n 8006c1c while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) 8006bfc: 68fb ldr r3, [r7, #12] 8006bfe: 681b ldr r3, [r3, #0] 8006c00: 699b ldr r3, [r3, #24] 8006c02: 68ba ldr r2, [r7, #8] 8006c04: 4013 ands r3, r2 8006c06: 68ba ldr r2, [r7, #8] 8006c08: 1ad3 subs r3, r2, r3 8006c0a: 425a negs r2, r3 8006c0c: 4153 adcs r3, r2 8006c0e: b2db uxtb r3, r3 8006c10: 001a movs r2, r3 8006c12: 1dfb adds r3, r7, #7 8006c14: 781b ldrb r3, [r3, #0] 8006c16: 429a cmp r2, r3 8006c18: d0b5 beq.n 8006b86 } } } } return HAL_OK; 8006c1a: 2300 movs r3, #0 } 8006c1c: 0018 movs r0, r3 8006c1e: 46bd mov sp, r7 8006c20: b004 add sp, #16 8006c22: bd80 pop {r7, pc} 08006c24 : * @param Tickstart Tick start value * @retval HAL status */ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { 8006c24: b580 push {r7, lr} 8006c26: b084 sub sp, #16 8006c28: af00 add r7, sp, #0 8006c2a: 60f8 str r0, [r7, #12] 8006c2c: 60b9 str r1, [r7, #8] 8006c2e: 607a str r2, [r7, #4] while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) 8006c30: e032 b.n 8006c98 { /* Check if an error is detected */ if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) 8006c32: 687a ldr r2, [r7, #4] 8006c34: 68b9 ldr r1, [r7, #8] 8006c36: 68fb ldr r3, [r7, #12] 8006c38: 0018 movs r0, r3 8006c3a: f000 f87d bl 8006d38 8006c3e: 1e03 subs r3, r0, #0 8006c40: d001 beq.n 8006c46 { return HAL_ERROR; 8006c42: 2301 movs r3, #1 8006c44: e030 b.n 8006ca8 } /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 8006c46: 68bb ldr r3, [r7, #8] 8006c48: 3301 adds r3, #1 8006c4a: d025 beq.n 8006c98 { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 8006c4c: f7fd fd62 bl 8004714 8006c50: 0002 movs r2, r0 8006c52: 687b ldr r3, [r7, #4] 8006c54: 1ad3 subs r3, r2, r3 8006c56: 68ba ldr r2, [r7, #8] 8006c58: 429a cmp r2, r3 8006c5a: d302 bcc.n 8006c62 8006c5c: 68bb ldr r3, [r7, #8] 8006c5e: 2b00 cmp r3, #0 8006c60: d11a bne.n 8006c98 { if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)) 8006c62: 68fb ldr r3, [r7, #12] 8006c64: 681b ldr r3, [r3, #0] 8006c66: 699b ldr r3, [r3, #24] 8006c68: 2202 movs r2, #2 8006c6a: 4013 ands r3, r2 8006c6c: 2b02 cmp r3, #2 8006c6e: d013 beq.n 8006c98 { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 8006c70: 68fb ldr r3, [r7, #12] 8006c72: 6c5b ldr r3, [r3, #68] @ 0x44 8006c74: 2220 movs r2, #32 8006c76: 431a orrs r2, r3 8006c78: 68fb ldr r3, [r7, #12] 8006c7a: 645a str r2, [r3, #68] @ 0x44 hi2c->State = HAL_I2C_STATE_READY; 8006c7c: 68fb ldr r3, [r7, #12] 8006c7e: 2241 movs r2, #65 @ 0x41 8006c80: 2120 movs r1, #32 8006c82: 5499 strb r1, [r3, r2] hi2c->Mode = HAL_I2C_MODE_NONE; 8006c84: 68fb ldr r3, [r7, #12] 8006c86: 2242 movs r2, #66 @ 0x42 8006c88: 2100 movs r1, #0 8006c8a: 5499 strb r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8006c8c: 68fb ldr r3, [r7, #12] 8006c8e: 2240 movs r2, #64 @ 0x40 8006c90: 2100 movs r1, #0 8006c92: 5499 strb r1, [r3, r2] return HAL_ERROR; 8006c94: 2301 movs r3, #1 8006c96: e007 b.n 8006ca8 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) 8006c98: 68fb ldr r3, [r7, #12] 8006c9a: 681b ldr r3, [r3, #0] 8006c9c: 699b ldr r3, [r3, #24] 8006c9e: 2202 movs r2, #2 8006ca0: 4013 ands r3, r2 8006ca2: 2b02 cmp r3, #2 8006ca4: d1c5 bne.n 8006c32 } } } } return HAL_OK; 8006ca6: 2300 movs r3, #0 } 8006ca8: 0018 movs r0, r3 8006caa: 46bd mov sp, r7 8006cac: b004 add sp, #16 8006cae: bd80 pop {r7, pc} 08006cb0 : * @param Tickstart Tick start value * @retval HAL status */ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { 8006cb0: b580 push {r7, lr} 8006cb2: b084 sub sp, #16 8006cb4: af00 add r7, sp, #0 8006cb6: 60f8 str r0, [r7, #12] 8006cb8: 60b9 str r1, [r7, #8] 8006cba: 607a str r2, [r7, #4] while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) 8006cbc: e02f b.n 8006d1e { /* Check if an error is detected */ if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) 8006cbe: 687a ldr r2, [r7, #4] 8006cc0: 68b9 ldr r1, [r7, #8] 8006cc2: 68fb ldr r3, [r7, #12] 8006cc4: 0018 movs r0, r3 8006cc6: f000 f837 bl 8006d38 8006cca: 1e03 subs r3, r0, #0 8006ccc: d001 beq.n 8006cd2 { return HAL_ERROR; 8006cce: 2301 movs r3, #1 8006cd0: e02d b.n 8006d2e } /* Check for the Timeout */ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 8006cd2: f7fd fd1f bl 8004714 8006cd6: 0002 movs r2, r0 8006cd8: 687b ldr r3, [r7, #4] 8006cda: 1ad3 subs r3, r2, r3 8006cdc: 68ba ldr r2, [r7, #8] 8006cde: 429a cmp r2, r3 8006ce0: d302 bcc.n 8006ce8 8006ce2: 68bb ldr r3, [r7, #8] 8006ce4: 2b00 cmp r3, #0 8006ce6: d11a bne.n 8006d1e { if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)) 8006ce8: 68fb ldr r3, [r7, #12] 8006cea: 681b ldr r3, [r3, #0] 8006cec: 699b ldr r3, [r3, #24] 8006cee: 2220 movs r2, #32 8006cf0: 4013 ands r3, r2 8006cf2: 2b20 cmp r3, #32 8006cf4: d013 beq.n 8006d1e { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 8006cf6: 68fb ldr r3, [r7, #12] 8006cf8: 6c5b ldr r3, [r3, #68] @ 0x44 8006cfa: 2220 movs r2, #32 8006cfc: 431a orrs r2, r3 8006cfe: 68fb ldr r3, [r7, #12] 8006d00: 645a str r2, [r3, #68] @ 0x44 hi2c->State = HAL_I2C_STATE_READY; 8006d02: 68fb ldr r3, [r7, #12] 8006d04: 2241 movs r2, #65 @ 0x41 8006d06: 2120 movs r1, #32 8006d08: 5499 strb r1, [r3, r2] hi2c->Mode = HAL_I2C_MODE_NONE; 8006d0a: 68fb ldr r3, [r7, #12] 8006d0c: 2242 movs r2, #66 @ 0x42 8006d0e: 2100 movs r1, #0 8006d10: 5499 strb r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8006d12: 68fb ldr r3, [r7, #12] 8006d14: 2240 movs r2, #64 @ 0x40 8006d16: 2100 movs r1, #0 8006d18: 5499 strb r1, [r3, r2] return HAL_ERROR; 8006d1a: 2301 movs r3, #1 8006d1c: e007 b.n 8006d2e while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) 8006d1e: 68fb ldr r3, [r7, #12] 8006d20: 681b ldr r3, [r3, #0] 8006d22: 699b ldr r3, [r3, #24] 8006d24: 2220 movs r2, #32 8006d26: 4013 ands r3, r2 8006d28: 2b20 cmp r3, #32 8006d2a: d1c8 bne.n 8006cbe } } } return HAL_OK; 8006d2c: 2300 movs r3, #0 } 8006d2e: 0018 movs r0, r3 8006d30: 46bd mov sp, r7 8006d32: b004 add sp, #16 8006d34: bd80 pop {r7, pc} ... 08006d38 : * @param Timeout Timeout duration * @param Tickstart Tick start value * @retval HAL status */ static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { 8006d38: b580 push {r7, lr} 8006d3a: b08a sub sp, #40 @ 0x28 8006d3c: af00 add r7, sp, #0 8006d3e: 60f8 str r0, [r7, #12] 8006d40: 60b9 str r1, [r7, #8] 8006d42: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8006d44: 2327 movs r3, #39 @ 0x27 8006d46: 18fb adds r3, r7, r3 8006d48: 2200 movs r2, #0 8006d4a: 701a strb r2, [r3, #0] uint32_t itflag = hi2c->Instance->ISR; 8006d4c: 68fb ldr r3, [r7, #12] 8006d4e: 681b ldr r3, [r3, #0] 8006d50: 699b ldr r3, [r3, #24] 8006d52: 61bb str r3, [r7, #24] uint32_t error_code = 0; 8006d54: 2300 movs r3, #0 8006d56: 623b str r3, [r7, #32] uint32_t tickstart = Tickstart; 8006d58: 687b ldr r3, [r7, #4] 8006d5a: 61fb str r3, [r7, #28] uint32_t tmp1; HAL_I2C_ModeTypeDef tmp2; if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF)) 8006d5c: 69bb ldr r3, [r7, #24] 8006d5e: 2210 movs r2, #16 8006d60: 4013 ands r3, r2 8006d62: d100 bne.n 8006d66 8006d64: e079 b.n 8006e5a { /* Clear NACKF Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 8006d66: 68fb ldr r3, [r7, #12] 8006d68: 681b ldr r3, [r3, #0] 8006d6a: 2210 movs r2, #16 8006d6c: 61da str r2, [r3, #28] /* Wait until STOP Flag is set or timeout occurred */ /* AutoEnd should be initiate after AF */ while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK)) 8006d6e: e057 b.n 8006e20 8006d70: 2227 movs r2, #39 @ 0x27 8006d72: 18bb adds r3, r7, r2 8006d74: 18ba adds r2, r7, r2 8006d76: 7812 ldrb r2, [r2, #0] 8006d78: 701a strb r2, [r3, #0] { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 8006d7a: 68bb ldr r3, [r7, #8] 8006d7c: 3301 adds r3, #1 8006d7e: d04f beq.n 8006e20 { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) 8006d80: f7fd fcc8 bl 8004714 8006d84: 0002 movs r2, r0 8006d86: 69fb ldr r3, [r7, #28] 8006d88: 1ad3 subs r3, r2, r3 8006d8a: 68ba ldr r2, [r7, #8] 8006d8c: 429a cmp r2, r3 8006d8e: d302 bcc.n 8006d96 8006d90: 68bb ldr r3, [r7, #8] 8006d92: 2b00 cmp r3, #0 8006d94: d144 bne.n 8006e20 { tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP); 8006d96: 68fb ldr r3, [r7, #12] 8006d98: 681b ldr r3, [r3, #0] 8006d9a: 685a ldr r2, [r3, #4] 8006d9c: 2380 movs r3, #128 @ 0x80 8006d9e: 01db lsls r3, r3, #7 8006da0: 4013 ands r3, r2 8006da2: 617b str r3, [r7, #20] tmp2 = hi2c->Mode; 8006da4: 2013 movs r0, #19 8006da6: 183b adds r3, r7, r0 8006da8: 68fa ldr r2, [r7, #12] 8006daa: 2142 movs r1, #66 @ 0x42 8006dac: 5c52 ldrb r2, [r2, r1] 8006dae: 701a strb r2, [r3, #0] /* In case of I2C still busy, try to regenerate a STOP manually */ if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \ 8006db0: 68fb ldr r3, [r7, #12] 8006db2: 681b ldr r3, [r3, #0] 8006db4: 699a ldr r2, [r3, #24] 8006db6: 2380 movs r3, #128 @ 0x80 8006db8: 021b lsls r3, r3, #8 8006dba: 401a ands r2, r3 8006dbc: 2380 movs r3, #128 @ 0x80 8006dbe: 021b lsls r3, r3, #8 8006dc0: 429a cmp r2, r3 8006dc2: d126 bne.n 8006e12 8006dc4: 697a ldr r2, [r7, #20] 8006dc6: 2380 movs r3, #128 @ 0x80 8006dc8: 01db lsls r3, r3, #7 8006dca: 429a cmp r2, r3 8006dcc: d021 beq.n 8006e12 (tmp1 != I2C_CR2_STOP) && \ 8006dce: 183b adds r3, r7, r0 8006dd0: 781b ldrb r3, [r3, #0] 8006dd2: 2b20 cmp r3, #32 8006dd4: d01d beq.n 8006e12 (tmp2 != HAL_I2C_MODE_SLAVE)) { /* Generate Stop */ hi2c->Instance->CR2 |= I2C_CR2_STOP; 8006dd6: 68fb ldr r3, [r7, #12] 8006dd8: 681b ldr r3, [r3, #0] 8006dda: 685a ldr r2, [r3, #4] 8006ddc: 68fb ldr r3, [r7, #12] 8006dde: 681b ldr r3, [r3, #0] 8006de0: 2180 movs r1, #128 @ 0x80 8006de2: 01c9 lsls r1, r1, #7 8006de4: 430a orrs r2, r1 8006de6: 605a str r2, [r3, #4] /* Update Tick with new reference */ tickstart = HAL_GetTick(); 8006de8: f7fd fc94 bl 8004714 8006dec: 0003 movs r3, r0 8006dee: 61fb str r3, [r7, #28] } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) 8006df0: e00f b.n 8006e12 { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF) 8006df2: f7fd fc8f bl 8004714 8006df6: 0002 movs r2, r0 8006df8: 69fb ldr r3, [r7, #28] 8006dfa: 1ad3 subs r3, r2, r3 8006dfc: 2b19 cmp r3, #25 8006dfe: d908 bls.n 8006e12 { error_code |= HAL_I2C_ERROR_TIMEOUT; 8006e00: 6a3b ldr r3, [r7, #32] 8006e02: 2220 movs r2, #32 8006e04: 4313 orrs r3, r2 8006e06: 623b str r3, [r7, #32] status = HAL_ERROR; 8006e08: 2327 movs r3, #39 @ 0x27 8006e0a: 18fb adds r3, r7, r3 8006e0c: 2201 movs r2, #1 8006e0e: 701a strb r2, [r3, #0] break; 8006e10: e006 b.n 8006e20 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) 8006e12: 68fb ldr r3, [r7, #12] 8006e14: 681b ldr r3, [r3, #0] 8006e16: 699b ldr r3, [r3, #24] 8006e18: 2220 movs r2, #32 8006e1a: 4013 ands r3, r2 8006e1c: 2b20 cmp r3, #32 8006e1e: d1e8 bne.n 8006df2 while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK)) 8006e20: 68fb ldr r3, [r7, #12] 8006e22: 681b ldr r3, [r3, #0] 8006e24: 699b ldr r3, [r3, #24] 8006e26: 2220 movs r2, #32 8006e28: 4013 ands r3, r2 8006e2a: 2b20 cmp r3, #32 8006e2c: d004 beq.n 8006e38 8006e2e: 2327 movs r3, #39 @ 0x27 8006e30: 18fb adds r3, r7, r3 8006e32: 781b ldrb r3, [r3, #0] 8006e34: 2b00 cmp r3, #0 8006e36: d09b beq.n 8006d70 } } } /* In case STOP Flag is detected, clear it */ if (status == HAL_OK) 8006e38: 2327 movs r3, #39 @ 0x27 8006e3a: 18fb adds r3, r7, r3 8006e3c: 781b ldrb r3, [r3, #0] 8006e3e: 2b00 cmp r3, #0 8006e40: d103 bne.n 8006e4a { /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); 8006e42: 68fb ldr r3, [r7, #12] 8006e44: 681b ldr r3, [r3, #0] 8006e46: 2220 movs r2, #32 8006e48: 61da str r2, [r3, #28] } error_code |= HAL_I2C_ERROR_AF; 8006e4a: 6a3b ldr r3, [r7, #32] 8006e4c: 2204 movs r2, #4 8006e4e: 4313 orrs r3, r2 8006e50: 623b str r3, [r7, #32] status = HAL_ERROR; 8006e52: 2327 movs r3, #39 @ 0x27 8006e54: 18fb adds r3, r7, r3 8006e56: 2201 movs r2, #1 8006e58: 701a strb r2, [r3, #0] } /* Refresh Content of Status register */ itflag = hi2c->Instance->ISR; 8006e5a: 68fb ldr r3, [r7, #12] 8006e5c: 681b ldr r3, [r3, #0] 8006e5e: 699b ldr r3, [r3, #24] 8006e60: 61bb str r3, [r7, #24] /* Then verify if an additional errors occurs */ /* Check if a Bus error occurred */ if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR)) 8006e62: 69ba ldr r2, [r7, #24] 8006e64: 2380 movs r3, #128 @ 0x80 8006e66: 005b lsls r3, r3, #1 8006e68: 4013 ands r3, r2 8006e6a: d00c beq.n 8006e86 { error_code |= HAL_I2C_ERROR_BERR; 8006e6c: 6a3b ldr r3, [r7, #32] 8006e6e: 2201 movs r2, #1 8006e70: 4313 orrs r3, r2 8006e72: 623b str r3, [r7, #32] /* Clear BERR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); 8006e74: 68fb ldr r3, [r7, #12] 8006e76: 681b ldr r3, [r3, #0] 8006e78: 2280 movs r2, #128 @ 0x80 8006e7a: 0052 lsls r2, r2, #1 8006e7c: 61da str r2, [r3, #28] status = HAL_ERROR; 8006e7e: 2327 movs r3, #39 @ 0x27 8006e80: 18fb adds r3, r7, r3 8006e82: 2201 movs r2, #1 8006e84: 701a strb r2, [r3, #0] } /* Check if an Over-Run/Under-Run error occurred */ if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR)) 8006e86: 69ba ldr r2, [r7, #24] 8006e88: 2380 movs r3, #128 @ 0x80 8006e8a: 00db lsls r3, r3, #3 8006e8c: 4013 ands r3, r2 8006e8e: d00c beq.n 8006eaa { error_code |= HAL_I2C_ERROR_OVR; 8006e90: 6a3b ldr r3, [r7, #32] 8006e92: 2208 movs r2, #8 8006e94: 4313 orrs r3, r2 8006e96: 623b str r3, [r7, #32] /* Clear OVR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); 8006e98: 68fb ldr r3, [r7, #12] 8006e9a: 681b ldr r3, [r3, #0] 8006e9c: 2280 movs r2, #128 @ 0x80 8006e9e: 00d2 lsls r2, r2, #3 8006ea0: 61da str r2, [r3, #28] status = HAL_ERROR; 8006ea2: 2327 movs r3, #39 @ 0x27 8006ea4: 18fb adds r3, r7, r3 8006ea6: 2201 movs r2, #1 8006ea8: 701a strb r2, [r3, #0] } /* Check if an Arbitration Loss error occurred */ if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO)) 8006eaa: 69ba ldr r2, [r7, #24] 8006eac: 2380 movs r3, #128 @ 0x80 8006eae: 009b lsls r3, r3, #2 8006eb0: 4013 ands r3, r2 8006eb2: d00c beq.n 8006ece { error_code |= HAL_I2C_ERROR_ARLO; 8006eb4: 6a3b ldr r3, [r7, #32] 8006eb6: 2202 movs r2, #2 8006eb8: 4313 orrs r3, r2 8006eba: 623b str r3, [r7, #32] /* Clear ARLO flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); 8006ebc: 68fb ldr r3, [r7, #12] 8006ebe: 681b ldr r3, [r3, #0] 8006ec0: 2280 movs r2, #128 @ 0x80 8006ec2: 0092 lsls r2, r2, #2 8006ec4: 61da str r2, [r3, #28] status = HAL_ERROR; 8006ec6: 2327 movs r3, #39 @ 0x27 8006ec8: 18fb adds r3, r7, r3 8006eca: 2201 movs r2, #1 8006ecc: 701a strb r2, [r3, #0] } if (status != HAL_OK) 8006ece: 2327 movs r3, #39 @ 0x27 8006ed0: 18fb adds r3, r7, r3 8006ed2: 781b ldrb r3, [r3, #0] 8006ed4: 2b00 cmp r3, #0 8006ed6: d01d beq.n 8006f14 { /* Flush TX register */ I2C_Flush_TXDR(hi2c); 8006ed8: 68fb ldr r3, [r7, #12] 8006eda: 0018 movs r0, r3 8006edc: f7ff fe09 bl 8006af2 /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); 8006ee0: 68fb ldr r3, [r7, #12] 8006ee2: 681b ldr r3, [r3, #0] 8006ee4: 685a ldr r2, [r3, #4] 8006ee6: 68fb ldr r3, [r7, #12] 8006ee8: 681b ldr r3, [r3, #0] 8006eea: 490e ldr r1, [pc, #56] @ (8006f24 ) 8006eec: 400a ands r2, r1 8006eee: 605a str r2, [r3, #4] hi2c->ErrorCode |= error_code; 8006ef0: 68fb ldr r3, [r7, #12] 8006ef2: 6c5a ldr r2, [r3, #68] @ 0x44 8006ef4: 6a3b ldr r3, [r7, #32] 8006ef6: 431a orrs r2, r3 8006ef8: 68fb ldr r3, [r7, #12] 8006efa: 645a str r2, [r3, #68] @ 0x44 hi2c->State = HAL_I2C_STATE_READY; 8006efc: 68fb ldr r3, [r7, #12] 8006efe: 2241 movs r2, #65 @ 0x41 8006f00: 2120 movs r1, #32 8006f02: 5499 strb r1, [r3, r2] hi2c->Mode = HAL_I2C_MODE_NONE; 8006f04: 68fb ldr r3, [r7, #12] 8006f06: 2242 movs r2, #66 @ 0x42 8006f08: 2100 movs r1, #0 8006f0a: 5499 strb r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8006f0c: 68fb ldr r3, [r7, #12] 8006f0e: 2240 movs r2, #64 @ 0x40 8006f10: 2100 movs r1, #0 8006f12: 5499 strb r1, [r3, r2] } return status; 8006f14: 2327 movs r3, #39 @ 0x27 8006f16: 18fb adds r3, r7, r3 8006f18: 781b ldrb r3, [r3, #0] } 8006f1a: 0018 movs r0, r3 8006f1c: 46bd mov sp, r7 8006f1e: b00a add sp, #40 @ 0x28 8006f20: bd80 pop {r7, pc} 8006f22: 46c0 nop @ (mov r8, r8) 8006f24: fe00e800 .word 0xfe00e800 08006f28 : * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request. * @retval None */ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) { 8006f28: b590 push {r4, r7, lr} 8006f2a: b087 sub sp, #28 8006f2c: af00 add r7, sp, #0 8006f2e: 60f8 str r0, [r7, #12] 8006f30: 0008 movs r0, r1 8006f32: 0011 movs r1, r2 8006f34: 607b str r3, [r7, #4] 8006f36: 240a movs r4, #10 8006f38: 193b adds r3, r7, r4 8006f3a: 1c02 adds r2, r0, #0 8006f3c: 801a strh r2, [r3, #0] 8006f3e: 2009 movs r0, #9 8006f40: 183b adds r3, r7, r0 8006f42: 1c0a adds r2, r1, #0 8006f44: 701a strb r2, [r3, #0] assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_TRANSFER_MODE(Mode)); assert_param(IS_TRANSFER_REQUEST(Request)); /* Declaration of tmp to prevent undefined behavior of volatile usage */ uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ 8006f46: 193b adds r3, r7, r4 8006f48: 881b ldrh r3, [r3, #0] 8006f4a: 059b lsls r3, r3, #22 8006f4c: 0d9a lsrs r2, r3, #22 (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ 8006f4e: 183b adds r3, r7, r0 8006f50: 781b ldrb r3, [r3, #0] 8006f52: 0419 lsls r1, r3, #16 8006f54: 23ff movs r3, #255 @ 0xff 8006f56: 041b lsls r3, r3, #16 8006f58: 400b ands r3, r1 uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ 8006f5a: 431a orrs r2, r3 (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ 8006f5c: 687b ldr r3, [r7, #4] 8006f5e: 431a orrs r2, r3 uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ 8006f60: 6abb ldr r3, [r7, #40] @ 0x28 8006f62: 4313 orrs r3, r2 8006f64: 005b lsls r3, r3, #1 8006f66: 085b lsrs r3, r3, #1 8006f68: 617b str r3, [r7, #20] (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); /* update CR2 register */ MODIFY_REG(hi2c->Instance->CR2, \ 8006f6a: 68fb ldr r3, [r7, #12] 8006f6c: 681b ldr r3, [r3, #0] 8006f6e: 685b ldr r3, [r3, #4] 8006f70: 6aba ldr r2, [r7, #40] @ 0x28 8006f72: 0d51 lsrs r1, r2, #21 8006f74: 2280 movs r2, #128 @ 0x80 8006f76: 00d2 lsls r2, r2, #3 8006f78: 400a ands r2, r1 8006f7a: 4907 ldr r1, [pc, #28] @ (8006f98 ) 8006f7c: 430a orrs r2, r1 8006f7e: 43d2 mvns r2, r2 8006f80: 401a ands r2, r3 8006f82: 0011 movs r1, r2 8006f84: 68fb ldr r3, [r7, #12] 8006f86: 681b ldr r3, [r3, #0] 8006f88: 697a ldr r2, [r7, #20] 8006f8a: 430a orrs r2, r1 8006f8c: 605a str r2, [r3, #4] ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \ (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \ I2C_CR2_START | I2C_CR2_STOP)), tmp); } 8006f8e: 46c0 nop @ (mov r8, r8) 8006f90: 46bd mov sp, r7 8006f92: b007 add sp, #28 8006f94: bd90 pop {r4, r7, pc} 8006f96: 46c0 nop @ (mov r8, r8) 8006f98: 03ff63ff .word 0x03ff63ff 08006f9c : * the configuration information for the specified I2C. * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. * @retval None */ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) { 8006f9c: b580 push {r7, lr} 8006f9e: b084 sub sp, #16 8006fa0: af00 add r7, sp, #0 8006fa2: 6078 str r0, [r7, #4] 8006fa4: 000a movs r2, r1 8006fa6: 1cbb adds r3, r7, #2 8006fa8: 801a strh r2, [r3, #0] uint32_t tmpisr = 0U; 8006faa: 2300 movs r3, #0 8006fac: 60fb str r3, [r7, #12] if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \ 8006fae: 687b ldr r3, [r7, #4] 8006fb0: 6b5a ldr r2, [r3, #52] @ 0x34 8006fb2: 4b3c ldr r3, [pc, #240] @ (80070a4 ) 8006fb4: 429a cmp r2, r3 8006fb6: d035 beq.n 8007024 (hi2c->XferISR != I2C_Slave_ISR_DMA) && \ 8006fb8: 687b ldr r3, [r7, #4] 8006fba: 6b5a ldr r2, [r3, #52] @ 0x34 if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \ 8006fbc: 4b3a ldr r3, [pc, #232] @ (80070a8 ) 8006fbe: 429a cmp r2, r3 8006fc0: d030 beq.n 8007024 (hi2c->XferISR != I2C_Mem_ISR_DMA)) 8006fc2: 687b ldr r3, [r7, #4] 8006fc4: 6b5a ldr r2, [r3, #52] @ 0x34 (hi2c->XferISR != I2C_Slave_ISR_DMA) && \ 8006fc6: 4b39 ldr r3, [pc, #228] @ (80070ac ) 8006fc8: 429a cmp r2, r3 8006fca: d02b beq.n 8007024 { if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) 8006fcc: 1cbb adds r3, r7, #2 8006fce: 2200 movs r2, #0 8006fd0: 5e9b ldrsh r3, [r3, r2] 8006fd2: 2b00 cmp r3, #0 8006fd4: da03 bge.n 8006fde { /* Enable ERR, STOP, NACK and ADDR interrupts */ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; 8006fd6: 68fb ldr r3, [r7, #12] 8006fd8: 22b8 movs r2, #184 @ 0xb8 8006fda: 4313 orrs r3, r2 8006fdc: 60fb str r3, [r7, #12] } if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) 8006fde: 1cbb adds r3, r7, #2 8006fe0: 881b ldrh r3, [r3, #0] 8006fe2: 2201 movs r2, #1 8006fe4: 4013 ands r3, r2 8006fe6: d003 beq.n 8006ff0 { /* Enable ERR, TC, STOP, NACK and TXI interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; 8006fe8: 68fb ldr r3, [r7, #12] 8006fea: 22f2 movs r2, #242 @ 0xf2 8006fec: 4313 orrs r3, r2 8006fee: 60fb str r3, [r7, #12] } if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) 8006ff0: 1cbb adds r3, r7, #2 8006ff2: 881b ldrh r3, [r3, #0] 8006ff4: 2202 movs r2, #2 8006ff6: 4013 ands r3, r2 8006ff8: d003 beq.n 8007002 { /* Enable ERR, TC, STOP, NACK and RXI interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; 8006ffa: 68fb ldr r3, [r7, #12] 8006ffc: 22f4 movs r2, #244 @ 0xf4 8006ffe: 4313 orrs r3, r2 8007000: 60fb str r3, [r7, #12] } if (InterruptRequest == I2C_XFER_ERROR_IT) 8007002: 1cbb adds r3, r7, #2 8007004: 881b ldrh r3, [r3, #0] 8007006: 2b10 cmp r3, #16 8007008: d103 bne.n 8007012 { /* Enable ERR and NACK interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; 800700a: 68fb ldr r3, [r7, #12] 800700c: 2290 movs r2, #144 @ 0x90 800700e: 4313 orrs r3, r2 8007010: 60fb str r3, [r7, #12] } if (InterruptRequest == I2C_XFER_CPLT_IT) 8007012: 1cbb adds r3, r7, #2 8007014: 881b ldrh r3, [r3, #0] 8007016: 2b20 cmp r3, #32 8007018: d137 bne.n 800708a { /* Enable STOP interrupts */ tmpisr |= I2C_IT_STOPI; 800701a: 68fb ldr r3, [r7, #12] 800701c: 2220 movs r2, #32 800701e: 4313 orrs r3, r2 8007020: 60fb str r3, [r7, #12] if (InterruptRequest == I2C_XFER_CPLT_IT) 8007022: e032 b.n 800708a } } else { if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) 8007024: 1cbb adds r3, r7, #2 8007026: 2200 movs r2, #0 8007028: 5e9b ldrsh r3, [r3, r2] 800702a: 2b00 cmp r3, #0 800702c: da03 bge.n 8007036 { /* Enable ERR, STOP, NACK and ADDR interrupts */ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; 800702e: 68fb ldr r3, [r7, #12] 8007030: 22b8 movs r2, #184 @ 0xb8 8007032: 4313 orrs r3, r2 8007034: 60fb str r3, [r7, #12] } if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) 8007036: 1cbb adds r3, r7, #2 8007038: 881b ldrh r3, [r3, #0] 800703a: 2201 movs r2, #1 800703c: 4013 ands r3, r2 800703e: d003 beq.n 8007048 { /* Enable ERR, TC, STOP, NACK and TXI interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; 8007040: 68fb ldr r3, [r7, #12] 8007042: 22f2 movs r2, #242 @ 0xf2 8007044: 4313 orrs r3, r2 8007046: 60fb str r3, [r7, #12] } if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) 8007048: 1cbb adds r3, r7, #2 800704a: 881b ldrh r3, [r3, #0] 800704c: 2202 movs r2, #2 800704e: 4013 ands r3, r2 8007050: d003 beq.n 800705a { /* Enable ERR, TC, STOP, NACK and RXI interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; 8007052: 68fb ldr r3, [r7, #12] 8007054: 22f4 movs r2, #244 @ 0xf4 8007056: 4313 orrs r3, r2 8007058: 60fb str r3, [r7, #12] } if (InterruptRequest == I2C_XFER_ERROR_IT) 800705a: 1cbb adds r3, r7, #2 800705c: 881b ldrh r3, [r3, #0] 800705e: 2b10 cmp r3, #16 8007060: d103 bne.n 800706a { /* Enable ERR and NACK interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; 8007062: 68fb ldr r3, [r7, #12] 8007064: 2290 movs r2, #144 @ 0x90 8007066: 4313 orrs r3, r2 8007068: 60fb str r3, [r7, #12] } if (InterruptRequest == I2C_XFER_CPLT_IT) 800706a: 1cbb adds r3, r7, #2 800706c: 881b ldrh r3, [r3, #0] 800706e: 2b20 cmp r3, #32 8007070: d103 bne.n 800707a { /* Enable STOP interrupts */ tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI); 8007072: 68fb ldr r3, [r7, #12] 8007074: 2260 movs r2, #96 @ 0x60 8007076: 4313 orrs r3, r2 8007078: 60fb str r3, [r7, #12] } if (InterruptRequest == I2C_XFER_RELOAD_IT) 800707a: 1cbb adds r3, r7, #2 800707c: 881b ldrh r3, [r3, #0] 800707e: 2b40 cmp r3, #64 @ 0x40 8007080: d103 bne.n 800708a { /* Enable TC interrupts */ tmpisr |= I2C_IT_TCI; 8007082: 68fb ldr r3, [r7, #12] 8007084: 2240 movs r2, #64 @ 0x40 8007086: 4313 orrs r3, r2 8007088: 60fb str r3, [r7, #12] } /* Enable interrupts only at the end */ /* to avoid the risk of I2C interrupt handle execution before */ /* all interrupts requested done */ __HAL_I2C_ENABLE_IT(hi2c, tmpisr); 800708a: 687b ldr r3, [r7, #4] 800708c: 681b ldr r3, [r3, #0] 800708e: 6819 ldr r1, [r3, #0] 8007090: 687b ldr r3, [r7, #4] 8007092: 681b ldr r3, [r3, #0] 8007094: 68fa ldr r2, [r7, #12] 8007096: 430a orrs r2, r1 8007098: 601a str r2, [r3, #0] } 800709a: 46c0 nop @ (mov r8, r8) 800709c: 46bd mov sp, r7 800709e: b004 add sp, #16 80070a0: bd80 pop {r7, pc} 80070a2: 46c0 nop @ (mov r8, r8) 80070a4: 080059c5 .word 0x080059c5 80070a8: 08005e15 .word 0x08005e15 80070ac: 08005bbd .word 0x08005bbd 080070b0 : * the configuration information for the specified I2C. * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. * @retval None */ static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) { 80070b0: b580 push {r7, lr} 80070b2: b084 sub sp, #16 80070b4: af00 add r7, sp, #0 80070b6: 6078 str r0, [r7, #4] 80070b8: 000a movs r2, r1 80070ba: 1cbb adds r3, r7, #2 80070bc: 801a strh r2, [r3, #0] uint32_t tmpisr = 0U; 80070be: 2300 movs r3, #0 80070c0: 60fb str r3, [r7, #12] if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) 80070c2: 1cbb adds r3, r7, #2 80070c4: 881b ldrh r3, [r3, #0] 80070c6: 2201 movs r2, #1 80070c8: 4013 ands r3, r2 80070ca: d010 beq.n 80070ee { /* Disable TC and TXI interrupts */ tmpisr |= I2C_IT_TCI | I2C_IT_TXI; 80070cc: 68fb ldr r3, [r7, #12] 80070ce: 2242 movs r2, #66 @ 0x42 80070d0: 4313 orrs r3, r2 80070d2: 60fb str r3, [r7, #12] if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) 80070d4: 687b ldr r3, [r7, #4] 80070d6: 2241 movs r2, #65 @ 0x41 80070d8: 5c9b ldrb r3, [r3, r2] 80070da: b2db uxtb r3, r3 80070dc: 001a movs r2, r3 80070de: 2328 movs r3, #40 @ 0x28 80070e0: 4013 ands r3, r2 80070e2: 2b28 cmp r3, #40 @ 0x28 80070e4: d003 beq.n 80070ee { /* Disable NACK and STOP interrupts */ tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; 80070e6: 68fb ldr r3, [r7, #12] 80070e8: 22b0 movs r2, #176 @ 0xb0 80070ea: 4313 orrs r3, r2 80070ec: 60fb str r3, [r7, #12] } } if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) 80070ee: 1cbb adds r3, r7, #2 80070f0: 881b ldrh r3, [r3, #0] 80070f2: 2202 movs r2, #2 80070f4: 4013 ands r3, r2 80070f6: d010 beq.n 800711a { /* Disable TC and RXI interrupts */ tmpisr |= I2C_IT_TCI | I2C_IT_RXI; 80070f8: 68fb ldr r3, [r7, #12] 80070fa: 2244 movs r2, #68 @ 0x44 80070fc: 4313 orrs r3, r2 80070fe: 60fb str r3, [r7, #12] if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) 8007100: 687b ldr r3, [r7, #4] 8007102: 2241 movs r2, #65 @ 0x41 8007104: 5c9b ldrb r3, [r3, r2] 8007106: b2db uxtb r3, r3 8007108: 001a movs r2, r3 800710a: 2328 movs r3, #40 @ 0x28 800710c: 4013 ands r3, r2 800710e: 2b28 cmp r3, #40 @ 0x28 8007110: d003 beq.n 800711a { /* Disable NACK and STOP interrupts */ tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; 8007112: 68fb ldr r3, [r7, #12] 8007114: 22b0 movs r2, #176 @ 0xb0 8007116: 4313 orrs r3, r2 8007118: 60fb str r3, [r7, #12] } } if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) 800711a: 1cbb adds r3, r7, #2 800711c: 2200 movs r2, #0 800711e: 5e9b ldrsh r3, [r3, r2] 8007120: 2b00 cmp r3, #0 8007122: da03 bge.n 800712c { /* Disable ADDR, NACK and STOP interrupts */ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; 8007124: 68fb ldr r3, [r7, #12] 8007126: 22b8 movs r2, #184 @ 0xb8 8007128: 4313 orrs r3, r2 800712a: 60fb str r3, [r7, #12] } if (InterruptRequest == I2C_XFER_ERROR_IT) 800712c: 1cbb adds r3, r7, #2 800712e: 881b ldrh r3, [r3, #0] 8007130: 2b10 cmp r3, #16 8007132: d103 bne.n 800713c { /* Enable ERR and NACK interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; 8007134: 68fb ldr r3, [r7, #12] 8007136: 2290 movs r2, #144 @ 0x90 8007138: 4313 orrs r3, r2 800713a: 60fb str r3, [r7, #12] } if (InterruptRequest == I2C_XFER_CPLT_IT) 800713c: 1cbb adds r3, r7, #2 800713e: 881b ldrh r3, [r3, #0] 8007140: 2b20 cmp r3, #32 8007142: d103 bne.n 800714c { /* Enable STOP interrupts */ tmpisr |= I2C_IT_STOPI; 8007144: 68fb ldr r3, [r7, #12] 8007146: 2220 movs r2, #32 8007148: 4313 orrs r3, r2 800714a: 60fb str r3, [r7, #12] } if (InterruptRequest == I2C_XFER_RELOAD_IT) 800714c: 1cbb adds r3, r7, #2 800714e: 881b ldrh r3, [r3, #0] 8007150: 2b40 cmp r3, #64 @ 0x40 8007152: d103 bne.n 800715c { /* Enable TC interrupts */ tmpisr |= I2C_IT_TCI; 8007154: 68fb ldr r3, [r7, #12] 8007156: 2240 movs r2, #64 @ 0x40 8007158: 4313 orrs r3, r2 800715a: 60fb str r3, [r7, #12] } /* Disable interrupts only at the end */ /* to avoid a breaking situation like at "t" time */ /* all disable interrupts request are not done */ __HAL_I2C_DISABLE_IT(hi2c, tmpisr); 800715c: 687b ldr r3, [r7, #4] 800715e: 681b ldr r3, [r3, #0] 8007160: 681a ldr r2, [r3, #0] 8007162: 68fb ldr r3, [r7, #12] 8007164: 43d9 mvns r1, r3 8007166: 687b ldr r3, [r7, #4] 8007168: 681b ldr r3, [r3, #0] 800716a: 400a ands r2, r1 800716c: 601a str r2, [r3, #0] } 800716e: 46c0 nop @ (mov r8, r8) 8007170: 46bd mov sp, r7 8007172: b004 add sp, #16 8007174: bd80 pop {r7, pc} ... 08007178 : * the configuration information for the specified I2Cx peripheral. * @param AnalogFilter New state of the Analog filter. * @retval HAL status */ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) { 8007178: b580 push {r7, lr} 800717a: b082 sub sp, #8 800717c: af00 add r7, sp, #0 800717e: 6078 str r0, [r7, #4] 8007180: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); if (hi2c->State == HAL_I2C_STATE_READY) 8007182: 687b ldr r3, [r7, #4] 8007184: 2241 movs r2, #65 @ 0x41 8007186: 5c9b ldrb r3, [r3, r2] 8007188: b2db uxtb r3, r3 800718a: 2b20 cmp r3, #32 800718c: d138 bne.n 8007200 { /* Process Locked */ __HAL_LOCK(hi2c); 800718e: 687b ldr r3, [r7, #4] 8007190: 2240 movs r2, #64 @ 0x40 8007192: 5c9b ldrb r3, [r3, r2] 8007194: 2b01 cmp r3, #1 8007196: d101 bne.n 800719c 8007198: 2302 movs r3, #2 800719a: e032 b.n 8007202 800719c: 687b ldr r3, [r7, #4] 800719e: 2240 movs r2, #64 @ 0x40 80071a0: 2101 movs r1, #1 80071a2: 5499 strb r1, [r3, r2] hi2c->State = HAL_I2C_STATE_BUSY; 80071a4: 687b ldr r3, [r7, #4] 80071a6: 2241 movs r2, #65 @ 0x41 80071a8: 2124 movs r1, #36 @ 0x24 80071aa: 5499 strb r1, [r3, r2] /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); 80071ac: 687b ldr r3, [r7, #4] 80071ae: 681b ldr r3, [r3, #0] 80071b0: 681a ldr r2, [r3, #0] 80071b2: 687b ldr r3, [r7, #4] 80071b4: 681b ldr r3, [r3, #0] 80071b6: 2101 movs r1, #1 80071b8: 438a bics r2, r1 80071ba: 601a str r2, [r3, #0] /* Reset I2Cx ANOFF bit */ hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); 80071bc: 687b ldr r3, [r7, #4] 80071be: 681b ldr r3, [r3, #0] 80071c0: 681a ldr r2, [r3, #0] 80071c2: 687b ldr r3, [r7, #4] 80071c4: 681b ldr r3, [r3, #0] 80071c6: 4911 ldr r1, [pc, #68] @ (800720c ) 80071c8: 400a ands r2, r1 80071ca: 601a str r2, [r3, #0] /* Set analog filter bit*/ hi2c->Instance->CR1 |= AnalogFilter; 80071cc: 687b ldr r3, [r7, #4] 80071ce: 681b ldr r3, [r3, #0] 80071d0: 6819 ldr r1, [r3, #0] 80071d2: 687b ldr r3, [r7, #4] 80071d4: 681b ldr r3, [r3, #0] 80071d6: 683a ldr r2, [r7, #0] 80071d8: 430a orrs r2, r1 80071da: 601a str r2, [r3, #0] __HAL_I2C_ENABLE(hi2c); 80071dc: 687b ldr r3, [r7, #4] 80071de: 681b ldr r3, [r3, #0] 80071e0: 681a ldr r2, [r3, #0] 80071e2: 687b ldr r3, [r7, #4] 80071e4: 681b ldr r3, [r3, #0] 80071e6: 2101 movs r1, #1 80071e8: 430a orrs r2, r1 80071ea: 601a str r2, [r3, #0] hi2c->State = HAL_I2C_STATE_READY; 80071ec: 687b ldr r3, [r7, #4] 80071ee: 2241 movs r2, #65 @ 0x41 80071f0: 2120 movs r1, #32 80071f2: 5499 strb r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(hi2c); 80071f4: 687b ldr r3, [r7, #4] 80071f6: 2240 movs r2, #64 @ 0x40 80071f8: 2100 movs r1, #0 80071fa: 5499 strb r1, [r3, r2] return HAL_OK; 80071fc: 2300 movs r3, #0 80071fe: e000 b.n 8007202 } else { return HAL_BUSY; 8007200: 2302 movs r3, #2 } } 8007202: 0018 movs r0, r3 8007204: 46bd mov sp, r7 8007206: b002 add sp, #8 8007208: bd80 pop {r7, pc} 800720a: 46c0 nop @ (mov r8, r8) 800720c: ffffefff .word 0xffffefff 08007210 : * the configuration information for the specified I2Cx peripheral. * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. * @retval HAL status */ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) { 8007210: b580 push {r7, lr} 8007212: b084 sub sp, #16 8007214: af00 add r7, sp, #0 8007216: 6078 str r0, [r7, #4] 8007218: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); if (hi2c->State == HAL_I2C_STATE_READY) 800721a: 687b ldr r3, [r7, #4] 800721c: 2241 movs r2, #65 @ 0x41 800721e: 5c9b ldrb r3, [r3, r2] 8007220: b2db uxtb r3, r3 8007222: 2b20 cmp r3, #32 8007224: d139 bne.n 800729a { /* Process Locked */ __HAL_LOCK(hi2c); 8007226: 687b ldr r3, [r7, #4] 8007228: 2240 movs r2, #64 @ 0x40 800722a: 5c9b ldrb r3, [r3, r2] 800722c: 2b01 cmp r3, #1 800722e: d101 bne.n 8007234 8007230: 2302 movs r3, #2 8007232: e033 b.n 800729c 8007234: 687b ldr r3, [r7, #4] 8007236: 2240 movs r2, #64 @ 0x40 8007238: 2101 movs r1, #1 800723a: 5499 strb r1, [r3, r2] hi2c->State = HAL_I2C_STATE_BUSY; 800723c: 687b ldr r3, [r7, #4] 800723e: 2241 movs r2, #65 @ 0x41 8007240: 2124 movs r1, #36 @ 0x24 8007242: 5499 strb r1, [r3, r2] /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); 8007244: 687b ldr r3, [r7, #4] 8007246: 681b ldr r3, [r3, #0] 8007248: 681a ldr r2, [r3, #0] 800724a: 687b ldr r3, [r7, #4] 800724c: 681b ldr r3, [r3, #0] 800724e: 2101 movs r1, #1 8007250: 438a bics r2, r1 8007252: 601a str r2, [r3, #0] /* Get the old register value */ tmpreg = hi2c->Instance->CR1; 8007254: 687b ldr r3, [r7, #4] 8007256: 681b ldr r3, [r3, #0] 8007258: 681b ldr r3, [r3, #0] 800725a: 60fb str r3, [r7, #12] /* Reset I2Cx DNF bits [11:8] */ tmpreg &= ~(I2C_CR1_DNF); 800725c: 68fb ldr r3, [r7, #12] 800725e: 4a11 ldr r2, [pc, #68] @ (80072a4 ) 8007260: 4013 ands r3, r2 8007262: 60fb str r3, [r7, #12] /* Set I2Cx DNF coefficient */ tmpreg |= DigitalFilter << 8U; 8007264: 683b ldr r3, [r7, #0] 8007266: 021b lsls r3, r3, #8 8007268: 68fa ldr r2, [r7, #12] 800726a: 4313 orrs r3, r2 800726c: 60fb str r3, [r7, #12] /* Store the new register value */ hi2c->Instance->CR1 = tmpreg; 800726e: 687b ldr r3, [r7, #4] 8007270: 681b ldr r3, [r3, #0] 8007272: 68fa ldr r2, [r7, #12] 8007274: 601a str r2, [r3, #0] __HAL_I2C_ENABLE(hi2c); 8007276: 687b ldr r3, [r7, #4] 8007278: 681b ldr r3, [r3, #0] 800727a: 681a ldr r2, [r3, #0] 800727c: 687b ldr r3, [r7, #4] 800727e: 681b ldr r3, [r3, #0] 8007280: 2101 movs r1, #1 8007282: 430a orrs r2, r1 8007284: 601a str r2, [r3, #0] hi2c->State = HAL_I2C_STATE_READY; 8007286: 687b ldr r3, [r7, #4] 8007288: 2241 movs r2, #65 @ 0x41 800728a: 2120 movs r1, #32 800728c: 5499 strb r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(hi2c); 800728e: 687b ldr r3, [r7, #4] 8007290: 2240 movs r2, #64 @ 0x40 8007292: 2100 movs r1, #0 8007294: 5499 strb r1, [r3, r2] return HAL_OK; 8007296: 2300 movs r3, #0 8007298: e000 b.n 800729c } else { return HAL_BUSY; 800729a: 2302 movs r3, #2 } } 800729c: 0018 movs r0, r3 800729e: 46bd mov sp, r7 80072a0: b004 add sp, #16 80072a2: bd80 pop {r7, pc} 80072a4: fffff0ff .word 0xfffff0ff 080072a8 : * cleared before returning the status. If the flag is not cleared within * 6 microseconds, HAL_TIMEOUT status is reported. * @retval HAL Status */ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) { 80072a8: b580 push {r7, lr} 80072aa: b084 sub sp, #16 80072ac: af00 add r7, sp, #0 80072ae: 6078 str r0, [r7, #4] uint32_t wait_loop_index; assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); /* Modify voltage scaling range */ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling); 80072b0: 4b19 ldr r3, [pc, #100] @ (8007318 ) 80072b2: 681b ldr r3, [r3, #0] 80072b4: 4a19 ldr r2, [pc, #100] @ (800731c ) 80072b6: 4013 ands r3, r2 80072b8: 0019 movs r1, r3 80072ba: 4b17 ldr r3, [pc, #92] @ (8007318 ) 80072bc: 687a ldr r2, [r7, #4] 80072be: 430a orrs r2, r1 80072c0: 601a str r2, [r3, #0] /* In case of Range 1 selected, we need to ensure that main regulator reaches new value */ if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1) 80072c2: 687a ldr r2, [r7, #4] 80072c4: 2380 movs r3, #128 @ 0x80 80072c6: 009b lsls r3, r3, #2 80072c8: 429a cmp r2, r3 80072ca: d11f bne.n 800730c { /* Set timeout value */ wait_loop_index = ((PWR_VOSF_SETTING_DELAY_6_US * SystemCoreClock) / 1000000U) + 1U; 80072cc: 4b14 ldr r3, [pc, #80] @ (8007320 ) 80072ce: 681a ldr r2, [r3, #0] 80072d0: 0013 movs r3, r2 80072d2: 005b lsls r3, r3, #1 80072d4: 189b adds r3, r3, r2 80072d6: 005b lsls r3, r3, #1 80072d8: 4912 ldr r1, [pc, #72] @ (8007324 ) 80072da: 0018 movs r0, r3 80072dc: f7f8 ff12 bl 8000104 <__udivsi3> 80072e0: 0003 movs r3, r0 80072e2: 3301 adds r3, #1 80072e4: 60fb str r3, [r7, #12] /* Wait until VOSF is reset */ while (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) 80072e6: e008 b.n 80072fa { if (wait_loop_index != 0U) 80072e8: 68fb ldr r3, [r7, #12] 80072ea: 2b00 cmp r3, #0 80072ec: d003 beq.n 80072f6 { wait_loop_index--; 80072ee: 68fb ldr r3, [r7, #12] 80072f0: 3b01 subs r3, #1 80072f2: 60fb str r3, [r7, #12] 80072f4: e001 b.n 80072fa } else { return HAL_TIMEOUT; 80072f6: 2303 movs r3, #3 80072f8: e009 b.n 800730e while (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) 80072fa: 4b07 ldr r3, [pc, #28] @ (8007318 ) 80072fc: 695a ldr r2, [r3, #20] 80072fe: 2380 movs r3, #128 @ 0x80 8007300: 00db lsls r3, r3, #3 8007302: 401a ands r2, r3 8007304: 2380 movs r3, #128 @ 0x80 8007306: 00db lsls r3, r3, #3 8007308: 429a cmp r2, r3 800730a: d0ed beq.n 80072e8 } } } return HAL_OK; 800730c: 2300 movs r3, #0 } 800730e: 0018 movs r0, r3 8007310: 46bd mov sp, r7 8007312: b004 add sp, #16 8007314: bd80 pop {r7, pc} 8007316: 46c0 nop @ (mov r8, r8) 8007318: 40007000 .word 0x40007000 800731c: fffff9ff .word 0xfffff9ff 8007320: 20000000 .word 0x20000000 8007324: 000f4240 .word 0x000f4240 08007328 : * supported by this function. User should request a transition to LSE Off * first and then to LSE On or LSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 8007328: b580 push {r7, lr} 800732a: b088 sub sp, #32 800732c: af00 add r7, sp, #0 800732e: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t temp_sysclksrc; uint32_t temp_pllckcfg; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 8007330: 687b ldr r3, [r7, #4] 8007332: 2b00 cmp r3, #0 8007334: d101 bne.n 800733a { return HAL_ERROR; 8007336: 2301 movs r3, #1 8007338: e2fe b.n 8007938 /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 800733a: 687b ldr r3, [r7, #4] 800733c: 681b ldr r3, [r3, #0] 800733e: 2201 movs r2, #1 8007340: 4013 ands r3, r2 8007342: d100 bne.n 8007346 8007344: e07c b.n 8007440 { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 8007346: 4bc3 ldr r3, [pc, #780] @ (8007654 ) 8007348: 689b ldr r3, [r3, #8] 800734a: 2238 movs r2, #56 @ 0x38 800734c: 4013 ands r3, r2 800734e: 61bb str r3, [r7, #24] temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE(); 8007350: 4bc0 ldr r3, [pc, #768] @ (8007654 ) 8007352: 68db ldr r3, [r3, #12] 8007354: 2203 movs r2, #3 8007356: 4013 ands r3, r2 8007358: 617b str r3, [r7, #20] /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if (((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_pllckcfg == RCC_PLLSOURCE_HSE)) 800735a: 69bb ldr r3, [r7, #24] 800735c: 2b10 cmp r3, #16 800735e: d102 bne.n 8007366 8007360: 697b ldr r3, [r7, #20] 8007362: 2b03 cmp r3, #3 8007364: d002 beq.n 800736c || (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSE)) 8007366: 69bb ldr r3, [r7, #24] 8007368: 2b08 cmp r3, #8 800736a: d10b bne.n 8007384 { if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 800736c: 4bb9 ldr r3, [pc, #740] @ (8007654 ) 800736e: 681a ldr r2, [r3, #0] 8007370: 2380 movs r3, #128 @ 0x80 8007372: 029b lsls r3, r3, #10 8007374: 4013 ands r3, r2 8007376: d062 beq.n 800743e 8007378: 687b ldr r3, [r7, #4] 800737a: 685b ldr r3, [r3, #4] 800737c: 2b00 cmp r3, #0 800737e: d15e bne.n 800743e { return HAL_ERROR; 8007380: 2301 movs r3, #1 8007382: e2d9 b.n 8007938 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8007384: 687b ldr r3, [r7, #4] 8007386: 685a ldr r2, [r3, #4] 8007388: 2380 movs r3, #128 @ 0x80 800738a: 025b lsls r3, r3, #9 800738c: 429a cmp r2, r3 800738e: d107 bne.n 80073a0 8007390: 4bb0 ldr r3, [pc, #704] @ (8007654 ) 8007392: 681a ldr r2, [r3, #0] 8007394: 4baf ldr r3, [pc, #700] @ (8007654 ) 8007396: 2180 movs r1, #128 @ 0x80 8007398: 0249 lsls r1, r1, #9 800739a: 430a orrs r2, r1 800739c: 601a str r2, [r3, #0] 800739e: e020 b.n 80073e2 80073a0: 687b ldr r3, [r7, #4] 80073a2: 685a ldr r2, [r3, #4] 80073a4: 23a0 movs r3, #160 @ 0xa0 80073a6: 02db lsls r3, r3, #11 80073a8: 429a cmp r2, r3 80073aa: d10e bne.n 80073ca 80073ac: 4ba9 ldr r3, [pc, #676] @ (8007654 ) 80073ae: 681a ldr r2, [r3, #0] 80073b0: 4ba8 ldr r3, [pc, #672] @ (8007654 ) 80073b2: 2180 movs r1, #128 @ 0x80 80073b4: 02c9 lsls r1, r1, #11 80073b6: 430a orrs r2, r1 80073b8: 601a str r2, [r3, #0] 80073ba: 4ba6 ldr r3, [pc, #664] @ (8007654 ) 80073bc: 681a ldr r2, [r3, #0] 80073be: 4ba5 ldr r3, [pc, #660] @ (8007654 ) 80073c0: 2180 movs r1, #128 @ 0x80 80073c2: 0249 lsls r1, r1, #9 80073c4: 430a orrs r2, r1 80073c6: 601a str r2, [r3, #0] 80073c8: e00b b.n 80073e2 80073ca: 4ba2 ldr r3, [pc, #648] @ (8007654 ) 80073cc: 681a ldr r2, [r3, #0] 80073ce: 4ba1 ldr r3, [pc, #644] @ (8007654 ) 80073d0: 49a1 ldr r1, [pc, #644] @ (8007658 ) 80073d2: 400a ands r2, r1 80073d4: 601a str r2, [r3, #0] 80073d6: 4b9f ldr r3, [pc, #636] @ (8007654 ) 80073d8: 681a ldr r2, [r3, #0] 80073da: 4b9e ldr r3, [pc, #632] @ (8007654 ) 80073dc: 499f ldr r1, [pc, #636] @ (800765c ) 80073de: 400a ands r2, r1 80073e0: 601a str r2, [r3, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 80073e2: 687b ldr r3, [r7, #4] 80073e4: 685b ldr r3, [r3, #4] 80073e6: 2b00 cmp r3, #0 80073e8: d014 beq.n 8007414 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 80073ea: f7fd f993 bl 8004714 80073ee: 0003 movs r3, r0 80073f0: 613b str r3, [r7, #16] /* Wait till HSE is ready */ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) 80073f2: e008 b.n 8007406 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 80073f4: f7fd f98e bl 8004714 80073f8: 0002 movs r2, r0 80073fa: 693b ldr r3, [r7, #16] 80073fc: 1ad3 subs r3, r2, r3 80073fe: 2b64 cmp r3, #100 @ 0x64 8007400: d901 bls.n 8007406 { return HAL_TIMEOUT; 8007402: 2303 movs r3, #3 8007404: e298 b.n 8007938 while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) 8007406: 4b93 ldr r3, [pc, #588] @ (8007654 ) 8007408: 681a ldr r2, [r3, #0] 800740a: 2380 movs r3, #128 @ 0x80 800740c: 029b lsls r3, r3, #10 800740e: 4013 ands r3, r2 8007410: d0f0 beq.n 80073f4 8007412: e015 b.n 8007440 } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8007414: f7fd f97e bl 8004714 8007418: 0003 movs r3, r0 800741a: 613b str r3, [r7, #16] /* Wait till HSE is disabled */ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) 800741c: e008 b.n 8007430 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 800741e: f7fd f979 bl 8004714 8007422: 0002 movs r2, r0 8007424: 693b ldr r3, [r7, #16] 8007426: 1ad3 subs r3, r2, r3 8007428: 2b64 cmp r3, #100 @ 0x64 800742a: d901 bls.n 8007430 { return HAL_TIMEOUT; 800742c: 2303 movs r3, #3 800742e: e283 b.n 8007938 while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) 8007430: 4b88 ldr r3, [pc, #544] @ (8007654 ) 8007432: 681a ldr r2, [r3, #0] 8007434: 2380 movs r3, #128 @ 0x80 8007436: 029b lsls r3, r3, #10 8007438: 4013 ands r3, r2 800743a: d1f0 bne.n 800741e 800743c: e000 b.n 8007440 if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 800743e: 46c0 nop @ (mov r8, r8) } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8007440: 687b ldr r3, [r7, #4] 8007442: 681b ldr r3, [r3, #0] 8007444: 2202 movs r2, #2 8007446: 4013 ands r3, r2 8007448: d100 bne.n 800744c 800744a: e099 b.n 8007580 assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); assert_param(IS_RCC_HSIDIV(RCC_OscInitStruct->HSIDiv)); /* Check if HSI16 is used as system clock or as PLL source when PLL is selected as system clock */ temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 800744c: 4b81 ldr r3, [pc, #516] @ (8007654 ) 800744e: 689b ldr r3, [r3, #8] 8007450: 2238 movs r2, #56 @ 0x38 8007452: 4013 ands r3, r2 8007454: 61bb str r3, [r7, #24] temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE(); 8007456: 4b7f ldr r3, [pc, #508] @ (8007654 ) 8007458: 68db ldr r3, [r3, #12] 800745a: 2203 movs r2, #3 800745c: 4013 ands r3, r2 800745e: 617b str r3, [r7, #20] if (((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_pllckcfg == RCC_PLLSOURCE_HSI)) 8007460: 69bb ldr r3, [r7, #24] 8007462: 2b10 cmp r3, #16 8007464: d102 bne.n 800746c 8007466: 697b ldr r3, [r7, #20] 8007468: 2b02 cmp r3, #2 800746a: d002 beq.n 8007472 || (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI)) 800746c: 69bb ldr r3, [r7, #24] 800746e: 2b00 cmp r3, #0 8007470: d135 bne.n 80074de { /* When HSI is used as system clock or as PLL input clock it can not be disabled */ if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 8007472: 4b78 ldr r3, [pc, #480] @ (8007654 ) 8007474: 681a ldr r2, [r3, #0] 8007476: 2380 movs r3, #128 @ 0x80 8007478: 00db lsls r3, r3, #3 800747a: 4013 ands r3, r2 800747c: d005 beq.n 800748a 800747e: 687b ldr r3, [r7, #4] 8007480: 68db ldr r3, [r3, #12] 8007482: 2b00 cmp r3, #0 8007484: d101 bne.n 800748a { return HAL_ERROR; 8007486: 2301 movs r3, #1 8007488: e256 b.n 8007938 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800748a: 4b72 ldr r3, [pc, #456] @ (8007654 ) 800748c: 685b ldr r3, [r3, #4] 800748e: 4a74 ldr r2, [pc, #464] @ (8007660 ) 8007490: 4013 ands r3, r2 8007492: 0019 movs r1, r3 8007494: 687b ldr r3, [r7, #4] 8007496: 695b ldr r3, [r3, #20] 8007498: 021a lsls r2, r3, #8 800749a: 4b6e ldr r3, [pc, #440] @ (8007654 ) 800749c: 430a orrs r2, r1 800749e: 605a str r2, [r3, #4] if (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI) 80074a0: 69bb ldr r3, [r7, #24] 80074a2: 2b00 cmp r3, #0 80074a4: d112 bne.n 80074cc { /* Adjust the HSI16 division factor */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv); 80074a6: 4b6b ldr r3, [pc, #428] @ (8007654 ) 80074a8: 681b ldr r3, [r3, #0] 80074aa: 4a6e ldr r2, [pc, #440] @ (8007664 ) 80074ac: 4013 ands r3, r2 80074ae: 0019 movs r1, r3 80074b0: 687b ldr r3, [r7, #4] 80074b2: 691a ldr r2, [r3, #16] 80074b4: 4b67 ldr r3, [pc, #412] @ (8007654 ) 80074b6: 430a orrs r2, r1 80074b8: 601a str r2, [r3, #0] /* Update the SystemCoreClock global variable with HSISYS value */ SystemCoreClock = (HSI_VALUE / (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos))); 80074ba: 4b66 ldr r3, [pc, #408] @ (8007654 ) 80074bc: 681b ldr r3, [r3, #0] 80074be: 0adb lsrs r3, r3, #11 80074c0: 2207 movs r2, #7 80074c2: 4013 ands r3, r2 80074c4: 4a68 ldr r2, [pc, #416] @ (8007668 ) 80074c6: 40da lsrs r2, r3 80074c8: 4b68 ldr r3, [pc, #416] @ (800766c ) 80074ca: 601a str r2, [r3, #0] } /* Adapt Systick interrupt period */ if (HAL_InitTick(uwTickPrio) != HAL_OK) 80074cc: 4b68 ldr r3, [pc, #416] @ (8007670 ) 80074ce: 681b ldr r3, [r3, #0] 80074d0: 0018 movs r0, r3 80074d2: f7fd f8c3 bl 800465c 80074d6: 1e03 subs r3, r0, #0 80074d8: d051 beq.n 800757e { return HAL_ERROR; 80074da: 2301 movs r3, #1 80074dc: e22c b.n 8007938 } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 80074de: 687b ldr r3, [r7, #4] 80074e0: 68db ldr r3, [r3, #12] 80074e2: 2b00 cmp r3, #0 80074e4: d030 beq.n 8007548 { /* Configure the HSI16 division factor */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv); 80074e6: 4b5b ldr r3, [pc, #364] @ (8007654 ) 80074e8: 681b ldr r3, [r3, #0] 80074ea: 4a5e ldr r2, [pc, #376] @ (8007664 ) 80074ec: 4013 ands r3, r2 80074ee: 0019 movs r1, r3 80074f0: 687b ldr r3, [r7, #4] 80074f2: 691a ldr r2, [r3, #16] 80074f4: 4b57 ldr r3, [pc, #348] @ (8007654 ) 80074f6: 430a orrs r2, r1 80074f8: 601a str r2, [r3, #0] /* Enable the Internal High Speed oscillator (HSI16). */ __HAL_RCC_HSI_ENABLE(); 80074fa: 4b56 ldr r3, [pc, #344] @ (8007654 ) 80074fc: 681a ldr r2, [r3, #0] 80074fe: 4b55 ldr r3, [pc, #340] @ (8007654 ) 8007500: 2180 movs r1, #128 @ 0x80 8007502: 0049 lsls r1, r1, #1 8007504: 430a orrs r2, r1 8007506: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8007508: f7fd f904 bl 8004714 800750c: 0003 movs r3, r0 800750e: 613b str r3, [r7, #16] /* Wait till HSI is ready */ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) 8007510: e008 b.n 8007524 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8007512: f7fd f8ff bl 8004714 8007516: 0002 movs r2, r0 8007518: 693b ldr r3, [r7, #16] 800751a: 1ad3 subs r3, r2, r3 800751c: 2b02 cmp r3, #2 800751e: d901 bls.n 8007524 { return HAL_TIMEOUT; 8007520: 2303 movs r3, #3 8007522: e209 b.n 8007938 while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) 8007524: 4b4b ldr r3, [pc, #300] @ (8007654 ) 8007526: 681a ldr r2, [r3, #0] 8007528: 2380 movs r3, #128 @ 0x80 800752a: 00db lsls r3, r3, #3 800752c: 4013 ands r3, r2 800752e: d0f0 beq.n 8007512 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8007530: 4b48 ldr r3, [pc, #288] @ (8007654 ) 8007532: 685b ldr r3, [r3, #4] 8007534: 4a4a ldr r2, [pc, #296] @ (8007660 ) 8007536: 4013 ands r3, r2 8007538: 0019 movs r1, r3 800753a: 687b ldr r3, [r7, #4] 800753c: 695b ldr r3, [r3, #20] 800753e: 021a lsls r2, r3, #8 8007540: 4b44 ldr r3, [pc, #272] @ (8007654 ) 8007542: 430a orrs r2, r1 8007544: 605a str r2, [r3, #4] 8007546: e01b b.n 8007580 } else { /* Disable the Internal High Speed oscillator (HSI16). */ __HAL_RCC_HSI_DISABLE(); 8007548: 4b42 ldr r3, [pc, #264] @ (8007654 ) 800754a: 681a ldr r2, [r3, #0] 800754c: 4b41 ldr r3, [pc, #260] @ (8007654 ) 800754e: 4949 ldr r1, [pc, #292] @ (8007674 ) 8007550: 400a ands r2, r1 8007552: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8007554: f7fd f8de bl 8004714 8007558: 0003 movs r3, r0 800755a: 613b str r3, [r7, #16] /* Wait till HSI is disabled */ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) 800755c: e008 b.n 8007570 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 800755e: f7fd f8d9 bl 8004714 8007562: 0002 movs r2, r0 8007564: 693b ldr r3, [r7, #16] 8007566: 1ad3 subs r3, r2, r3 8007568: 2b02 cmp r3, #2 800756a: d901 bls.n 8007570 { return HAL_TIMEOUT; 800756c: 2303 movs r3, #3 800756e: e1e3 b.n 8007938 while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) 8007570: 4b38 ldr r3, [pc, #224] @ (8007654 ) 8007572: 681a ldr r2, [r3, #0] 8007574: 2380 movs r3, #128 @ 0x80 8007576: 00db lsls r3, r3, #3 8007578: 4013 ands r3, r2 800757a: d1f0 bne.n 800755e 800757c: e000 b.n 8007580 if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 800757e: 46c0 nop @ (mov r8, r8) } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8007580: 687b ldr r3, [r7, #4] 8007582: 681b ldr r3, [r3, #0] 8007584: 2208 movs r2, #8 8007586: 4013 ands r3, r2 8007588: d047 beq.n 800761a { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check if LSI is used as system clock */ if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSI) 800758a: 4b32 ldr r3, [pc, #200] @ (8007654 ) 800758c: 689b ldr r3, [r3, #8] 800758e: 2238 movs r2, #56 @ 0x38 8007590: 4013 ands r3, r2 8007592: 2b18 cmp r3, #24 8007594: d10a bne.n 80075ac { /* When LSI is used as system clock it will not be disabled */ if ((((RCC->CSR) & RCC_CSR_LSIRDY) != 0U) && (RCC_OscInitStruct->LSIState == RCC_LSI_OFF)) 8007596: 4b2f ldr r3, [pc, #188] @ (8007654 ) 8007598: 6e1b ldr r3, [r3, #96] @ 0x60 800759a: 2202 movs r2, #2 800759c: 4013 ands r3, r2 800759e: d03c beq.n 800761a 80075a0: 687b ldr r3, [r7, #4] 80075a2: 699b ldr r3, [r3, #24] 80075a4: 2b00 cmp r3, #0 80075a6: d138 bne.n 800761a { return HAL_ERROR; 80075a8: 2301 movs r3, #1 80075aa: e1c5 b.n 8007938 } } else { /* Check the LSI State */ if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 80075ac: 687b ldr r3, [r7, #4] 80075ae: 699b ldr r3, [r3, #24] 80075b0: 2b00 cmp r3, #0 80075b2: d019 beq.n 80075e8 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 80075b4: 4b27 ldr r3, [pc, #156] @ (8007654 ) 80075b6: 6e1a ldr r2, [r3, #96] @ 0x60 80075b8: 4b26 ldr r3, [pc, #152] @ (8007654 ) 80075ba: 2101 movs r1, #1 80075bc: 430a orrs r2, r1 80075be: 661a str r2, [r3, #96] @ 0x60 /* Get Start Tick*/ tickstart = HAL_GetTick(); 80075c0: f7fd f8a8 bl 8004714 80075c4: 0003 movs r3, r0 80075c6: 613b str r3, [r7, #16] /* Wait till LSI is ready */ while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) 80075c8: e008 b.n 80075dc { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 80075ca: f7fd f8a3 bl 8004714 80075ce: 0002 movs r2, r0 80075d0: 693b ldr r3, [r7, #16] 80075d2: 1ad3 subs r3, r2, r3 80075d4: 2b02 cmp r3, #2 80075d6: d901 bls.n 80075dc { return HAL_TIMEOUT; 80075d8: 2303 movs r3, #3 80075da: e1ad b.n 8007938 while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) 80075dc: 4b1d ldr r3, [pc, #116] @ (8007654 ) 80075de: 6e1b ldr r3, [r3, #96] @ 0x60 80075e0: 2202 movs r2, #2 80075e2: 4013 ands r3, r2 80075e4: d0f1 beq.n 80075ca 80075e6: e018 b.n 800761a } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 80075e8: 4b1a ldr r3, [pc, #104] @ (8007654 ) 80075ea: 6e1a ldr r2, [r3, #96] @ 0x60 80075ec: 4b19 ldr r3, [pc, #100] @ (8007654 ) 80075ee: 2101 movs r1, #1 80075f0: 438a bics r2, r1 80075f2: 661a str r2, [r3, #96] @ 0x60 /* Get Start Tick*/ tickstart = HAL_GetTick(); 80075f4: f7fd f88e bl 8004714 80075f8: 0003 movs r3, r0 80075fa: 613b str r3, [r7, #16] /* Wait till LSI is disabled */ while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) 80075fc: e008 b.n 8007610 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 80075fe: f7fd f889 bl 8004714 8007602: 0002 movs r2, r0 8007604: 693b ldr r3, [r7, #16] 8007606: 1ad3 subs r3, r2, r3 8007608: 2b02 cmp r3, #2 800760a: d901 bls.n 8007610 { return HAL_TIMEOUT; 800760c: 2303 movs r3, #3 800760e: e193 b.n 8007938 while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) 8007610: 4b10 ldr r3, [pc, #64] @ (8007654 ) 8007612: 6e1b ldr r3, [r3, #96] @ 0x60 8007614: 2202 movs r2, #2 8007616: 4013 ands r3, r2 8007618: d1f1 bne.n 80075fe } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 800761a: 687b ldr r3, [r7, #4] 800761c: 681b ldr r3, [r3, #0] 800761e: 2204 movs r2, #4 8007620: 4013 ands r3, r2 8007622: d100 bne.n 8007626 8007624: e0c6 b.n 80077b4 { FlagStatus pwrclkchanged = RESET; 8007626: 231f movs r3, #31 8007628: 18fb adds r3, r7, r3 800762a: 2200 movs r2, #0 800762c: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* When the LSE is used as system clock, it is not allowed disable it */ if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSE) 800762e: 4b09 ldr r3, [pc, #36] @ (8007654 ) 8007630: 689b ldr r3, [r3, #8] 8007632: 2238 movs r2, #56 @ 0x38 8007634: 4013 ands r3, r2 8007636: 2b20 cmp r3, #32 8007638: d11e bne.n 8007678 { if ((((RCC->BDCR) & RCC_BDCR_LSERDY) != 0U) && (RCC_OscInitStruct->LSEState == RCC_LSE_OFF)) 800763a: 4b06 ldr r3, [pc, #24] @ (8007654 ) 800763c: 6ddb ldr r3, [r3, #92] @ 0x5c 800763e: 2202 movs r2, #2 8007640: 4013 ands r3, r2 8007642: d100 bne.n 8007646 8007644: e0b6 b.n 80077b4 8007646: 687b ldr r3, [r7, #4] 8007648: 689b ldr r3, [r3, #8] 800764a: 2b00 cmp r3, #0 800764c: d000 beq.n 8007650 800764e: e0b1 b.n 80077b4 { return HAL_ERROR; 8007650: 2301 movs r3, #1 8007652: e171 b.n 8007938 8007654: 40021000 .word 0x40021000 8007658: fffeffff .word 0xfffeffff 800765c: fffbffff .word 0xfffbffff 8007660: ffff80ff .word 0xffff80ff 8007664: ffffc7ff .word 0xffffc7ff 8007668: 00f42400 .word 0x00f42400 800766c: 20000000 .word 0x20000000 8007670: 20000004 .word 0x20000004 8007674: fffffeff .word 0xfffffeff } else { /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U) 8007678: 4bb1 ldr r3, [pc, #708] @ (8007940 ) 800767a: 6bda ldr r2, [r3, #60] @ 0x3c 800767c: 2380 movs r3, #128 @ 0x80 800767e: 055b lsls r3, r3, #21 8007680: 4013 ands r3, r2 8007682: d101 bne.n 8007688 8007684: 2301 movs r3, #1 8007686: e000 b.n 800768a 8007688: 2300 movs r3, #0 800768a: 2b00 cmp r3, #0 800768c: d011 beq.n 80076b2 { __HAL_RCC_PWR_CLK_ENABLE(); 800768e: 4bac ldr r3, [pc, #688] @ (8007940 ) 8007690: 6bda ldr r2, [r3, #60] @ 0x3c 8007692: 4bab ldr r3, [pc, #684] @ (8007940 ) 8007694: 2180 movs r1, #128 @ 0x80 8007696: 0549 lsls r1, r1, #21 8007698: 430a orrs r2, r1 800769a: 63da str r2, [r3, #60] @ 0x3c 800769c: 4ba8 ldr r3, [pc, #672] @ (8007940 ) 800769e: 6bda ldr r2, [r3, #60] @ 0x3c 80076a0: 2380 movs r3, #128 @ 0x80 80076a2: 055b lsls r3, r3, #21 80076a4: 4013 ands r3, r2 80076a6: 60fb str r3, [r7, #12] 80076a8: 68fb ldr r3, [r7, #12] pwrclkchanged = SET; 80076aa: 231f movs r3, #31 80076ac: 18fb adds r3, r7, r3 80076ae: 2201 movs r2, #1 80076b0: 701a strb r2, [r3, #0] } if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) 80076b2: 4ba4 ldr r3, [pc, #656] @ (8007944 ) 80076b4: 681a ldr r2, [r3, #0] 80076b6: 2380 movs r3, #128 @ 0x80 80076b8: 005b lsls r3, r3, #1 80076ba: 4013 ands r3, r2 80076bc: d11a bne.n 80076f4 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); 80076be: 4ba1 ldr r3, [pc, #644] @ (8007944 ) 80076c0: 681a ldr r2, [r3, #0] 80076c2: 4ba0 ldr r3, [pc, #640] @ (8007944 ) 80076c4: 2180 movs r1, #128 @ 0x80 80076c6: 0049 lsls r1, r1, #1 80076c8: 430a orrs r2, r1 80076ca: 601a str r2, [r3, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 80076cc: f7fd f822 bl 8004714 80076d0: 0003 movs r3, r0 80076d2: 613b str r3, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) 80076d4: e008 b.n 80076e8 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 80076d6: f7fd f81d bl 8004714 80076da: 0002 movs r2, r0 80076dc: 693b ldr r3, [r7, #16] 80076de: 1ad3 subs r3, r2, r3 80076e0: 2b02 cmp r3, #2 80076e2: d901 bls.n 80076e8 { return HAL_TIMEOUT; 80076e4: 2303 movs r3, #3 80076e6: e127 b.n 8007938 while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) 80076e8: 4b96 ldr r3, [pc, #600] @ (8007944 ) 80076ea: 681a ldr r2, [r3, #0] 80076ec: 2380 movs r3, #128 @ 0x80 80076ee: 005b lsls r3, r3, #1 80076f0: 4013 ands r3, r2 80076f2: d0f0 beq.n 80076d6 } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 80076f4: 687b ldr r3, [r7, #4] 80076f6: 689b ldr r3, [r3, #8] 80076f8: 2b01 cmp r3, #1 80076fa: d106 bne.n 800770a 80076fc: 4b90 ldr r3, [pc, #576] @ (8007940 ) 80076fe: 6dda ldr r2, [r3, #92] @ 0x5c 8007700: 4b8f ldr r3, [pc, #572] @ (8007940 ) 8007702: 2101 movs r1, #1 8007704: 430a orrs r2, r1 8007706: 65da str r2, [r3, #92] @ 0x5c 8007708: e01c b.n 8007744 800770a: 687b ldr r3, [r7, #4] 800770c: 689b ldr r3, [r3, #8] 800770e: 2b05 cmp r3, #5 8007710: d10c bne.n 800772c 8007712: 4b8b ldr r3, [pc, #556] @ (8007940 ) 8007714: 6dda ldr r2, [r3, #92] @ 0x5c 8007716: 4b8a ldr r3, [pc, #552] @ (8007940 ) 8007718: 2104 movs r1, #4 800771a: 430a orrs r2, r1 800771c: 65da str r2, [r3, #92] @ 0x5c 800771e: 4b88 ldr r3, [pc, #544] @ (8007940 ) 8007720: 6dda ldr r2, [r3, #92] @ 0x5c 8007722: 4b87 ldr r3, [pc, #540] @ (8007940 ) 8007724: 2101 movs r1, #1 8007726: 430a orrs r2, r1 8007728: 65da str r2, [r3, #92] @ 0x5c 800772a: e00b b.n 8007744 800772c: 4b84 ldr r3, [pc, #528] @ (8007940 ) 800772e: 6dda ldr r2, [r3, #92] @ 0x5c 8007730: 4b83 ldr r3, [pc, #524] @ (8007940 ) 8007732: 2101 movs r1, #1 8007734: 438a bics r2, r1 8007736: 65da str r2, [r3, #92] @ 0x5c 8007738: 4b81 ldr r3, [pc, #516] @ (8007940 ) 800773a: 6dda ldr r2, [r3, #92] @ 0x5c 800773c: 4b80 ldr r3, [pc, #512] @ (8007940 ) 800773e: 2104 movs r1, #4 8007740: 438a bics r2, r1 8007742: 65da str r2, [r3, #92] @ 0x5c /* Check the LSE State */ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 8007744: 687b ldr r3, [r7, #4] 8007746: 689b ldr r3, [r3, #8] 8007748: 2b00 cmp r3, #0 800774a: d014 beq.n 8007776 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800774c: f7fc ffe2 bl 8004714 8007750: 0003 movs r3, r0 8007752: 613b str r3, [r7, #16] /* Wait till LSE is ready */ while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 8007754: e009 b.n 800776a { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8007756: f7fc ffdd bl 8004714 800775a: 0002 movs r2, r0 800775c: 693b ldr r3, [r7, #16] 800775e: 1ad3 subs r3, r2, r3 8007760: 4a79 ldr r2, [pc, #484] @ (8007948 ) 8007762: 4293 cmp r3, r2 8007764: d901 bls.n 800776a { return HAL_TIMEOUT; 8007766: 2303 movs r3, #3 8007768: e0e6 b.n 8007938 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 800776a: 4b75 ldr r3, [pc, #468] @ (8007940 ) 800776c: 6ddb ldr r3, [r3, #92] @ 0x5c 800776e: 2202 movs r2, #2 8007770: 4013 ands r3, r2 8007772: d0f0 beq.n 8007756 8007774: e013 b.n 800779e } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8007776: f7fc ffcd bl 8004714 800777a: 0003 movs r3, r0 800777c: 613b str r3, [r7, #16] /* Wait till LSE is disabled */ while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) 800777e: e009 b.n 8007794 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8007780: f7fc ffc8 bl 8004714 8007784: 0002 movs r2, r0 8007786: 693b ldr r3, [r7, #16] 8007788: 1ad3 subs r3, r2, r3 800778a: 4a6f ldr r2, [pc, #444] @ (8007948 ) 800778c: 4293 cmp r3, r2 800778e: d901 bls.n 8007794 { return HAL_TIMEOUT; 8007790: 2303 movs r3, #3 8007792: e0d1 b.n 8007938 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) 8007794: 4b6a ldr r3, [pc, #424] @ (8007940 ) 8007796: 6ddb ldr r3, [r3, #92] @ 0x5c 8007798: 2202 movs r2, #2 800779a: 4013 ands r3, r2 800779c: d1f0 bne.n 8007780 } } } /* Restore clock configuration if changed */ if (pwrclkchanged == SET) 800779e: 231f movs r3, #31 80077a0: 18fb adds r3, r7, r3 80077a2: 781b ldrb r3, [r3, #0] 80077a4: 2b01 cmp r3, #1 80077a6: d105 bne.n 80077b4 { __HAL_RCC_PWR_CLK_DISABLE(); 80077a8: 4b65 ldr r3, [pc, #404] @ (8007940 ) 80077aa: 6bda ldr r2, [r3, #60] @ 0x3c 80077ac: 4b64 ldr r3, [pc, #400] @ (8007940 ) 80077ae: 4967 ldr r1, [pc, #412] @ (800794c ) 80077b0: 400a ands r2, r1 80077b2: 63da str r2, [r3, #60] @ 0x3c #endif /* RCC_HSI48_SUPPORT */ /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE) 80077b4: 687b ldr r3, [r7, #4] 80077b6: 69db ldr r3, [r3, #28] 80077b8: 2b00 cmp r3, #0 80077ba: d100 bne.n 80077be 80077bc: e0bb b.n 8007936 { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 80077be: 4b60 ldr r3, [pc, #384] @ (8007940 ) 80077c0: 689b ldr r3, [r3, #8] 80077c2: 2238 movs r2, #56 @ 0x38 80077c4: 4013 ands r3, r2 80077c6: 2b10 cmp r3, #16 80077c8: d100 bne.n 80077cc 80077ca: e07b b.n 80078c4 { if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON) 80077cc: 687b ldr r3, [r7, #4] 80077ce: 69db ldr r3, [r3, #28] 80077d0: 2b02 cmp r3, #2 80077d2: d156 bne.n 8007882 assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); #endif /* RCC_PLLQ_SUPPORT */ assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 80077d4: 4b5a ldr r3, [pc, #360] @ (8007940 ) 80077d6: 681a ldr r2, [r3, #0] 80077d8: 4b59 ldr r3, [pc, #356] @ (8007940 ) 80077da: 495d ldr r1, [pc, #372] @ (8007950 ) 80077dc: 400a ands r2, r1 80077de: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80077e0: f7fc ff98 bl 8004714 80077e4: 0003 movs r3, r0 80077e6: 613b str r3, [r7, #16] /* Wait till PLL is ready */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 80077e8: e008 b.n 80077fc { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80077ea: f7fc ff93 bl 8004714 80077ee: 0002 movs r2, r0 80077f0: 693b ldr r3, [r7, #16] 80077f2: 1ad3 subs r3, r2, r3 80077f4: 2b02 cmp r3, #2 80077f6: d901 bls.n 80077fc { return HAL_TIMEOUT; 80077f8: 2303 movs r3, #3 80077fa: e09d b.n 8007938 while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 80077fc: 4b50 ldr r3, [pc, #320] @ (8007940 ) 80077fe: 681a ldr r2, [r3, #0] 8007800: 2380 movs r3, #128 @ 0x80 8007802: 049b lsls r3, r3, #18 8007804: 4013 ands r3, r2 8007806: d1f0 bne.n 80077ea } } /* Configure the main PLL clock source, multiplication and division factors. */ #if defined(RCC_PLLQ_SUPPORT) __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 8007808: 4b4d ldr r3, [pc, #308] @ (8007940 ) 800780a: 68db ldr r3, [r3, #12] 800780c: 4a51 ldr r2, [pc, #324] @ (8007954 ) 800780e: 4013 ands r3, r2 8007810: 0019 movs r1, r3 8007812: 687b ldr r3, [r7, #4] 8007814: 6a1a ldr r2, [r3, #32] 8007816: 687b ldr r3, [r7, #4] 8007818: 6a5b ldr r3, [r3, #36] @ 0x24 800781a: 431a orrs r2, r3 800781c: 687b ldr r3, [r7, #4] 800781e: 6a9b ldr r3, [r3, #40] @ 0x28 8007820: 021b lsls r3, r3, #8 8007822: 431a orrs r2, r3 8007824: 687b ldr r3, [r7, #4] 8007826: 6adb ldr r3, [r3, #44] @ 0x2c 8007828: 431a orrs r2, r3 800782a: 687b ldr r3, [r7, #4] 800782c: 6b1b ldr r3, [r3, #48] @ 0x30 800782e: 431a orrs r2, r3 8007830: 687b ldr r3, [r7, #4] 8007832: 6b5b ldr r3, [r3, #52] @ 0x34 8007834: 431a orrs r2, r3 8007836: 4b42 ldr r3, [pc, #264] @ (8007940 ) 8007838: 430a orrs r2, r1 800783a: 60da str r2, [r3, #12] RCC_OscInitStruct->PLL.PLLP, RCC_OscInitStruct->PLL.PLLR); #endif /* RCC_PLLQ_SUPPORT */ /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 800783c: 4b40 ldr r3, [pc, #256] @ (8007940 ) 800783e: 681a ldr r2, [r3, #0] 8007840: 4b3f ldr r3, [pc, #252] @ (8007940 ) 8007842: 2180 movs r1, #128 @ 0x80 8007844: 0449 lsls r1, r1, #17 8007846: 430a orrs r2, r1 8007848: 601a str r2, [r3, #0] /* Enable PLLR Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLRCLK); 800784a: 4b3d ldr r3, [pc, #244] @ (8007940 ) 800784c: 68da ldr r2, [r3, #12] 800784e: 4b3c ldr r3, [pc, #240] @ (8007940 ) 8007850: 2180 movs r1, #128 @ 0x80 8007852: 0549 lsls r1, r1, #21 8007854: 430a orrs r2, r1 8007856: 60da str r2, [r3, #12] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8007858: f7fc ff5c bl 8004714 800785c: 0003 movs r3, r0 800785e: 613b str r3, [r7, #16] /* Wait till PLL is ready */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) 8007860: e008 b.n 8007874 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8007862: f7fc ff57 bl 8004714 8007866: 0002 movs r2, r0 8007868: 693b ldr r3, [r7, #16] 800786a: 1ad3 subs r3, r2, r3 800786c: 2b02 cmp r3, #2 800786e: d901 bls.n 8007874 { return HAL_TIMEOUT; 8007870: 2303 movs r3, #3 8007872: e061 b.n 8007938 while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) 8007874: 4b32 ldr r3, [pc, #200] @ (8007940 ) 8007876: 681a ldr r2, [r3, #0] 8007878: 2380 movs r3, #128 @ 0x80 800787a: 049b lsls r3, r3, #18 800787c: 4013 ands r3, r2 800787e: d0f0 beq.n 8007862 8007880: e059 b.n 8007936 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8007882: 4b2f ldr r3, [pc, #188] @ (8007940 ) 8007884: 681a ldr r2, [r3, #0] 8007886: 4b2e ldr r3, [pc, #184] @ (8007940 ) 8007888: 4931 ldr r1, [pc, #196] @ (8007950 ) 800788a: 400a ands r2, r1 800788c: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800788e: f7fc ff41 bl 8004714 8007892: 0003 movs r3, r0 8007894: 613b str r3, [r7, #16] /* Wait till PLL is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 8007896: e008 b.n 80078aa { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8007898: f7fc ff3c bl 8004714 800789c: 0002 movs r2, r0 800789e: 693b ldr r3, [r7, #16] 80078a0: 1ad3 subs r3, r2, r3 80078a2: 2b02 cmp r3, #2 80078a4: d901 bls.n 80078aa { return HAL_TIMEOUT; 80078a6: 2303 movs r3, #3 80078a8: e046 b.n 8007938 while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 80078aa: 4b25 ldr r3, [pc, #148] @ (8007940 ) 80078ac: 681a ldr r2, [r3, #0] 80078ae: 2380 movs r3, #128 @ 0x80 80078b0: 049b lsls r3, r3, #18 80078b2: 4013 ands r3, r2 80078b4: d1f0 bne.n 8007898 } } /* Unselect main PLL clock source and disable main PLL outputs to save power */ #if defined(RCC_PLLQ_SUPPORT) RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLPEN | RCC_PLLCFGR_PLLQEN | RCC_PLLCFGR_PLLREN); 80078b6: 4b22 ldr r3, [pc, #136] @ (8007940 ) 80078b8: 68da ldr r2, [r3, #12] 80078ba: 4b21 ldr r3, [pc, #132] @ (8007940 ) 80078bc: 4926 ldr r1, [pc, #152] @ (8007958 ) 80078be: 400a ands r2, r1 80078c0: 60da str r2, [r3, #12] 80078c2: e038 b.n 8007936 } } else { /* Check if there is a request to disable the PLL used as System clock source */ if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 80078c4: 687b ldr r3, [r7, #4] 80078c6: 69db ldr r3, [r3, #28] 80078c8: 2b01 cmp r3, #1 80078ca: d101 bne.n 80078d0 { return HAL_ERROR; 80078cc: 2301 movs r3, #1 80078ce: e033 b.n 8007938 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ temp_pllckcfg = RCC->PLLCFGR; 80078d0: 4b1b ldr r3, [pc, #108] @ (8007940 ) 80078d2: 68db ldr r3, [r3, #12] 80078d4: 617b str r3, [r7, #20] if ((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 80078d6: 697b ldr r3, [r7, #20] 80078d8: 2203 movs r2, #3 80078da: 401a ands r2, r3 80078dc: 687b ldr r3, [r7, #4] 80078de: 6a1b ldr r3, [r3, #32] 80078e0: 429a cmp r2, r3 80078e2: d126 bne.n 8007932 (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || 80078e4: 697b ldr r3, [r7, #20] 80078e6: 2270 movs r2, #112 @ 0x70 80078e8: 401a ands r2, r3 80078ea: 687b ldr r3, [r7, #4] 80078ec: 6a5b ldr r3, [r3, #36] @ 0x24 if ((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 80078ee: 429a cmp r2, r3 80078f0: d11f bne.n 8007932 (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) || 80078f2: 697a ldr r2, [r7, #20] 80078f4: 23fe movs r3, #254 @ 0xfe 80078f6: 01db lsls r3, r3, #7 80078f8: 401a ands r2, r3 80078fa: 687b ldr r3, [r7, #4] 80078fc: 6a9b ldr r3, [r3, #40] @ 0x28 80078fe: 021b lsls r3, r3, #8 (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || 8007900: 429a cmp r2, r3 8007902: d116 bne.n 8007932 (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) || 8007904: 697a ldr r2, [r7, #20] 8007906: 23f8 movs r3, #248 @ 0xf8 8007908: 039b lsls r3, r3, #14 800790a: 401a ands r2, r3 800790c: 687b ldr r3, [r7, #4] 800790e: 6adb ldr r3, [r3, #44] @ 0x2c (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) || 8007910: 429a cmp r2, r3 8007912: d10e bne.n 8007932 #if defined (RCC_PLLQ_SUPPORT) (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) || 8007914: 697a ldr r2, [r7, #20] 8007916: 23e0 movs r3, #224 @ 0xe0 8007918: 051b lsls r3, r3, #20 800791a: 401a ands r2, r3 800791c: 687b ldr r3, [r7, #4] 800791e: 6b1b ldr r3, [r3, #48] @ 0x30 (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) || 8007920: 429a cmp r2, r3 8007922: d106 bne.n 8007932 #endif /* RCC_PLLQ_SUPPORT */ (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLR) != RCC_OscInitStruct->PLL.PLLR)) 8007924: 697b ldr r3, [r7, #20] 8007926: 0f5b lsrs r3, r3, #29 8007928: 075a lsls r2, r3, #29 800792a: 687b ldr r3, [r7, #4] 800792c: 6b5b ldr r3, [r3, #52] @ 0x34 (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) || 800792e: 429a cmp r2, r3 8007930: d001 beq.n 8007936 { return HAL_ERROR; 8007932: 2301 movs r3, #1 8007934: e000 b.n 8007938 } } } } return HAL_OK; 8007936: 2300 movs r3, #0 } 8007938: 0018 movs r0, r3 800793a: 46bd mov sp, r7 800793c: b008 add sp, #32 800793e: bd80 pop {r7, pc} 8007940: 40021000 .word 0x40021000 8007944: 40007000 .word 0x40007000 8007948: 00001388 .word 0x00001388 800794c: efffffff .word 0xefffffff 8007950: feffffff .word 0xfeffffff 8007954: 11c1808c .word 0x11c1808c 8007958: eefefffc .word 0xeefefffc 0800795c : * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 800795c: b580 push {r7, lr} 800795e: b084 sub sp, #16 8007960: af00 add r7, sp, #0 8007962: 6078 str r0, [r7, #4] 8007964: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 8007966: 687b ldr r3, [r7, #4] 8007968: 2b00 cmp r3, #0 800796a: d101 bne.n 8007970 { return HAL_ERROR; 800796c: 2301 movs r3, #1 800796e: e0e9 b.n 8007b44 /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the FLASH clock (HCLK) and the supply voltage of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 8007970: 4b76 ldr r3, [pc, #472] @ (8007b4c ) 8007972: 681b ldr r3, [r3, #0] 8007974: 2207 movs r2, #7 8007976: 4013 ands r3, r2 8007978: 683a ldr r2, [r7, #0] 800797a: 429a cmp r2, r3 800797c: d91e bls.n 80079bc { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 800797e: 4b73 ldr r3, [pc, #460] @ (8007b4c ) 8007980: 681b ldr r3, [r3, #0] 8007982: 2207 movs r2, #7 8007984: 4393 bics r3, r2 8007986: 0019 movs r1, r3 8007988: 4b70 ldr r3, [pc, #448] @ (8007b4c ) 800798a: 683a ldr r2, [r7, #0] 800798c: 430a orrs r2, r1 800798e: 601a str r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by polling the FLASH_ACR register */ tickstart = HAL_GetTick(); 8007990: f7fc fec0 bl 8004714 8007994: 0003 movs r3, r0 8007996: 60fb str r3, [r7, #12] while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) 8007998: e009 b.n 80079ae { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 800799a: f7fc febb bl 8004714 800799e: 0002 movs r2, r0 80079a0: 68fb ldr r3, [r7, #12] 80079a2: 1ad3 subs r3, r2, r3 80079a4: 4a6a ldr r2, [pc, #424] @ (8007b50 ) 80079a6: 4293 cmp r3, r2 80079a8: d901 bls.n 80079ae { return HAL_TIMEOUT; 80079aa: 2303 movs r3, #3 80079ac: e0ca b.n 8007b44 while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) 80079ae: 4b67 ldr r3, [pc, #412] @ (8007b4c ) 80079b0: 681b ldr r3, [r3, #0] 80079b2: 2207 movs r2, #7 80079b4: 4013 ands r3, r2 80079b6: 683a ldr r2, [r7, #0] 80079b8: 429a cmp r2, r3 80079ba: d1ee bne.n 800799a } } } /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 80079bc: 687b ldr r3, [r7, #4] 80079be: 681b ldr r3, [r3, #0] 80079c0: 2202 movs r2, #2 80079c2: 4013 ands r3, r2 80079c4: d015 beq.n 80079f2 { /* Set the highest APB divider in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 80079c6: 687b ldr r3, [r7, #4] 80079c8: 681b ldr r3, [r3, #0] 80079ca: 2204 movs r2, #4 80079cc: 4013 ands r3, r2 80079ce: d006 beq.n 80079de { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16); 80079d0: 4b60 ldr r3, [pc, #384] @ (8007b54 ) 80079d2: 689a ldr r2, [r3, #8] 80079d4: 4b5f ldr r3, [pc, #380] @ (8007b54 ) 80079d6: 21e0 movs r1, #224 @ 0xe0 80079d8: 01c9 lsls r1, r1, #7 80079da: 430a orrs r2, r1 80079dc: 609a str r2, [r3, #8] } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 80079de: 4b5d ldr r3, [pc, #372] @ (8007b54 ) 80079e0: 689b ldr r3, [r3, #8] 80079e2: 4a5d ldr r2, [pc, #372] @ (8007b58 ) 80079e4: 4013 ands r3, r2 80079e6: 0019 movs r1, r3 80079e8: 687b ldr r3, [r7, #4] 80079ea: 689a ldr r2, [r3, #8] 80079ec: 4b59 ldr r3, [pc, #356] @ (8007b54 ) 80079ee: 430a orrs r2, r1 80079f0: 609a str r2, [r3, #8] } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 80079f2: 687b ldr r3, [r7, #4] 80079f4: 681b ldr r3, [r3, #0] 80079f6: 2201 movs r2, #1 80079f8: 4013 ands r3, r2 80079fa: d057 beq.n 8007aac { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 80079fc: 687b ldr r3, [r7, #4] 80079fe: 685b ldr r3, [r3, #4] 8007a00: 2b01 cmp r3, #1 8007a02: d107 bne.n 8007a14 { /* Check the HSE ready flag */ if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) 8007a04: 4b53 ldr r3, [pc, #332] @ (8007b54 ) 8007a06: 681a ldr r2, [r3, #0] 8007a08: 2380 movs r3, #128 @ 0x80 8007a0a: 029b lsls r3, r3, #10 8007a0c: 4013 ands r3, r2 8007a0e: d12b bne.n 8007a68 { return HAL_ERROR; 8007a10: 2301 movs r3, #1 8007a12: e097 b.n 8007b44 } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 8007a14: 687b ldr r3, [r7, #4] 8007a16: 685b ldr r3, [r3, #4] 8007a18: 2b02 cmp r3, #2 8007a1a: d107 bne.n 8007a2c { /* Check the PLL ready flag */ if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) 8007a1c: 4b4d ldr r3, [pc, #308] @ (8007b54 ) 8007a1e: 681a ldr r2, [r3, #0] 8007a20: 2380 movs r3, #128 @ 0x80 8007a22: 049b lsls r3, r3, #18 8007a24: 4013 ands r3, r2 8007a26: d11f bne.n 8007a68 { return HAL_ERROR; 8007a28: 2301 movs r3, #1 8007a2a: e08b b.n 8007b44 } } /* HSI is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) 8007a2c: 687b ldr r3, [r7, #4] 8007a2e: 685b ldr r3, [r3, #4] 8007a30: 2b00 cmp r3, #0 8007a32: d107 bne.n 8007a44 { /* Check the HSI ready flag */ if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) 8007a34: 4b47 ldr r3, [pc, #284] @ (8007b54 ) 8007a36: 681a ldr r2, [r3, #0] 8007a38: 2380 movs r3, #128 @ 0x80 8007a3a: 00db lsls r3, r3, #3 8007a3c: 4013 ands r3, r2 8007a3e: d113 bne.n 8007a68 { return HAL_ERROR; 8007a40: 2301 movs r3, #1 8007a42: e07f b.n 8007b44 } } /* LSI is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_LSI) 8007a44: 687b ldr r3, [r7, #4] 8007a46: 685b ldr r3, [r3, #4] 8007a48: 2b03 cmp r3, #3 8007a4a: d106 bne.n 8007a5a { /* Check the LSI ready flag */ if (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) 8007a4c: 4b41 ldr r3, [pc, #260] @ (8007b54 ) 8007a4e: 6e1b ldr r3, [r3, #96] @ 0x60 8007a50: 2202 movs r2, #2 8007a52: 4013 ands r3, r2 8007a54: d108 bne.n 8007a68 { return HAL_ERROR; 8007a56: 2301 movs r3, #1 8007a58: e074 b.n 8007b44 } /* LSE is selected as System Clock Source */ else { /* Check the LSE ready flag */ if (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 8007a5a: 4b3e ldr r3, [pc, #248] @ (8007b54 ) 8007a5c: 6ddb ldr r3, [r3, #92] @ 0x5c 8007a5e: 2202 movs r2, #2 8007a60: 4013 ands r3, r2 8007a62: d101 bne.n 8007a68 { return HAL_ERROR; 8007a64: 2301 movs r3, #1 8007a66: e06d b.n 8007b44 } } MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); 8007a68: 4b3a ldr r3, [pc, #232] @ (8007b54 ) 8007a6a: 689b ldr r3, [r3, #8] 8007a6c: 2207 movs r2, #7 8007a6e: 4393 bics r3, r2 8007a70: 0019 movs r1, r3 8007a72: 687b ldr r3, [r7, #4] 8007a74: 685a ldr r2, [r3, #4] 8007a76: 4b37 ldr r3, [pc, #220] @ (8007b54 ) 8007a78: 430a orrs r2, r1 8007a7a: 609a str r2, [r3, #8] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8007a7c: f7fc fe4a bl 8004714 8007a80: 0003 movs r3, r0 8007a82: 60fb str r3, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8007a84: e009 b.n 8007a9a { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8007a86: f7fc fe45 bl 8004714 8007a8a: 0002 movs r2, r0 8007a8c: 68fb ldr r3, [r7, #12] 8007a8e: 1ad3 subs r3, r2, r3 8007a90: 4a2f ldr r2, [pc, #188] @ (8007b50 ) 8007a92: 4293 cmp r3, r2 8007a94: d901 bls.n 8007a9a { return HAL_TIMEOUT; 8007a96: 2303 movs r3, #3 8007a98: e054 b.n 8007b44 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8007a9a: 4b2e ldr r3, [pc, #184] @ (8007b54 ) 8007a9c: 689b ldr r3, [r3, #8] 8007a9e: 2238 movs r2, #56 @ 0x38 8007aa0: 401a ands r2, r3 8007aa2: 687b ldr r3, [r7, #4] 8007aa4: 685b ldr r3, [r3, #4] 8007aa6: 00db lsls r3, r3, #3 8007aa8: 429a cmp r2, r3 8007aaa: d1ec bne.n 8007a86 } } } /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 8007aac: 4b27 ldr r3, [pc, #156] @ (8007b4c ) 8007aae: 681b ldr r3, [r3, #0] 8007ab0: 2207 movs r2, #7 8007ab2: 4013 ands r3, r2 8007ab4: 683a ldr r2, [r7, #0] 8007ab6: 429a cmp r2, r3 8007ab8: d21e bcs.n 8007af8 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8007aba: 4b24 ldr r3, [pc, #144] @ (8007b4c ) 8007abc: 681b ldr r3, [r3, #0] 8007abe: 2207 movs r2, #7 8007ac0: 4393 bics r3, r2 8007ac2: 0019 movs r1, r3 8007ac4: 4b21 ldr r3, [pc, #132] @ (8007b4c ) 8007ac6: 683a ldr r2, [r7, #0] 8007ac8: 430a orrs r2, r1 8007aca: 601a str r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by polling the FLASH_ACR register */ tickstart = HAL_GetTick(); 8007acc: f7fc fe22 bl 8004714 8007ad0: 0003 movs r3, r0 8007ad2: 60fb str r3, [r7, #12] while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) 8007ad4: e009 b.n 8007aea { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8007ad6: f7fc fe1d bl 8004714 8007ada: 0002 movs r2, r0 8007adc: 68fb ldr r3, [r7, #12] 8007ade: 1ad3 subs r3, r2, r3 8007ae0: 4a1b ldr r2, [pc, #108] @ (8007b50 ) 8007ae2: 4293 cmp r3, r2 8007ae4: d901 bls.n 8007aea { return HAL_TIMEOUT; 8007ae6: 2303 movs r3, #3 8007ae8: e02c b.n 8007b44 while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) 8007aea: 4b18 ldr r3, [pc, #96] @ (8007b4c ) 8007aec: 681b ldr r3, [r3, #0] 8007aee: 2207 movs r2, #7 8007af0: 4013 ands r3, r2 8007af2: 683a ldr r2, [r7, #0] 8007af4: 429a cmp r2, r3 8007af6: d1ee bne.n 8007ad6 } } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8007af8: 687b ldr r3, [r7, #4] 8007afa: 681b ldr r3, [r3, #0] 8007afc: 2204 movs r2, #4 8007afe: 4013 ands r3, r2 8007b00: d009 beq.n 8007b16 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider); 8007b02: 4b14 ldr r3, [pc, #80] @ (8007b54 ) 8007b04: 689b ldr r3, [r3, #8] 8007b06: 4a15 ldr r2, [pc, #84] @ (8007b5c ) 8007b08: 4013 ands r3, r2 8007b0a: 0019 movs r1, r3 8007b0c: 687b ldr r3, [r7, #4] 8007b0e: 68da ldr r2, [r3, #12] 8007b10: 4b10 ldr r3, [pc, #64] @ (8007b54 ) 8007b12: 430a orrs r2, r1 8007b14: 609a str r2, [r3, #8] } /* Update the SystemCoreClock global variable */ SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) & 0x1FU)); 8007b16: f000 f829 bl 8007b6c 8007b1a: 0001 movs r1, r0 8007b1c: 4b0d ldr r3, [pc, #52] @ (8007b54 ) 8007b1e: 689b ldr r3, [r3, #8] 8007b20: 0a1b lsrs r3, r3, #8 8007b22: 220f movs r2, #15 8007b24: 401a ands r2, r3 8007b26: 4b0e ldr r3, [pc, #56] @ (8007b60 ) 8007b28: 0092 lsls r2, r2, #2 8007b2a: 58d3 ldr r3, [r2, r3] 8007b2c: 221f movs r2, #31 8007b2e: 4013 ands r3, r2 8007b30: 000a movs r2, r1 8007b32: 40da lsrs r2, r3 8007b34: 4b0b ldr r3, [pc, #44] @ (8007b64 ) 8007b36: 601a str r2, [r3, #0] /* Configure the source of time base considering new system clocks settings*/ return HAL_InitTick(uwTickPrio); 8007b38: 4b0b ldr r3, [pc, #44] @ (8007b68 ) 8007b3a: 681b ldr r3, [r3, #0] 8007b3c: 0018 movs r0, r3 8007b3e: f7fc fd8d bl 800465c 8007b42: 0003 movs r3, r0 } 8007b44: 0018 movs r0, r3 8007b46: 46bd mov sp, r7 8007b48: b004 add sp, #16 8007b4a: bd80 pop {r7, pc} 8007b4c: 40022000 .word 0x40022000 8007b50: 00001388 .word 0x00001388 8007b54: 40021000 .word 0x40021000 8007b58: fffff0ff .word 0xfffff0ff 8007b5c: ffff8fff .word 0xffff8fff 8007b60: 08009e9c .word 0x08009e9c 8007b64: 20000000 .word 0x20000000 8007b68: 20000004 .word 0x20000004 08007b6c : * * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 8007b6c: b580 push {r7, lr} 8007b6e: b086 sub sp, #24 8007b70: af00 add r7, sp, #0 uint32_t pllvco, pllsource, pllr, pllm, hsidiv; uint32_t sysclockfreq; if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 8007b72: 4b3c ldr r3, [pc, #240] @ (8007c64 ) 8007b74: 689b ldr r3, [r3, #8] 8007b76: 2238 movs r2, #56 @ 0x38 8007b78: 4013 ands r3, r2 8007b7a: d10f bne.n 8007b9c { /* HSISYS can be derived for HSI16 */ hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos)); 8007b7c: 4b39 ldr r3, [pc, #228] @ (8007c64 ) 8007b7e: 681b ldr r3, [r3, #0] 8007b80: 0adb lsrs r3, r3, #11 8007b82: 2207 movs r2, #7 8007b84: 4013 ands r3, r2 8007b86: 2201 movs r2, #1 8007b88: 409a lsls r2, r3 8007b8a: 0013 movs r3, r2 8007b8c: 603b str r3, [r7, #0] /* HSI used as system clock source */ sysclockfreq = (HSI_VALUE / hsidiv); 8007b8e: 6839 ldr r1, [r7, #0] 8007b90: 4835 ldr r0, [pc, #212] @ (8007c68 ) 8007b92: f7f8 fab7 bl 8000104 <__udivsi3> 8007b96: 0003 movs r3, r0 8007b98: 613b str r3, [r7, #16] 8007b9a: e05d b.n 8007c58 } else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 8007b9c: 4b31 ldr r3, [pc, #196] @ (8007c64 ) 8007b9e: 689b ldr r3, [r3, #8] 8007ba0: 2238 movs r2, #56 @ 0x38 8007ba2: 4013 ands r3, r2 8007ba4: 2b08 cmp r3, #8 8007ba6: d102 bne.n 8007bae { /* HSE used as system clock source */ sysclockfreq = HSE_VALUE; 8007ba8: 4b30 ldr r3, [pc, #192] @ (8007c6c ) 8007baa: 613b str r3, [r7, #16] 8007bac: e054 b.n 8007c58 } else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) 8007bae: 4b2d ldr r3, [pc, #180] @ (8007c64 ) 8007bb0: 689b ldr r3, [r3, #8] 8007bb2: 2238 movs r2, #56 @ 0x38 8007bb4: 4013 ands r3, r2 8007bb6: 2b10 cmp r3, #16 8007bb8: d138 bne.n 8007c2c /* PLL used as system clock source */ /* PLL_VCO = ((HSE_VALUE or HSI_VALUE)/ PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); 8007bba: 4b2a ldr r3, [pc, #168] @ (8007c64 ) 8007bbc: 68db ldr r3, [r3, #12] 8007bbe: 2203 movs r2, #3 8007bc0: 4013 ands r3, r2 8007bc2: 60fb str r3, [r7, #12] pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; 8007bc4: 4b27 ldr r3, [pc, #156] @ (8007c64 ) 8007bc6: 68db ldr r3, [r3, #12] 8007bc8: 091b lsrs r3, r3, #4 8007bca: 2207 movs r2, #7 8007bcc: 4013 ands r3, r2 8007bce: 3301 adds r3, #1 8007bd0: 60bb str r3, [r7, #8] switch (pllsource) 8007bd2: 68fb ldr r3, [r7, #12] 8007bd4: 2b03 cmp r3, #3 8007bd6: d10d bne.n 8007bf4 { case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); 8007bd8: 68b9 ldr r1, [r7, #8] 8007bda: 4824 ldr r0, [pc, #144] @ (8007c6c ) 8007bdc: f7f8 fa92 bl 8000104 <__udivsi3> 8007be0: 0003 movs r3, r0 8007be2: 0019 movs r1, r3 8007be4: 4b1f ldr r3, [pc, #124] @ (8007c64 ) 8007be6: 68db ldr r3, [r3, #12] 8007be8: 0a1b lsrs r3, r3, #8 8007bea: 227f movs r2, #127 @ 0x7f 8007bec: 4013 ands r3, r2 8007bee: 434b muls r3, r1 8007bf0: 617b str r3, [r7, #20] break; 8007bf2: e00d b.n 8007c10 case RCC_PLLSOURCE_HSI: /* HSI16 used as PLL clock source */ default: /* HSI16 used as PLL clock source */ pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos) ; 8007bf4: 68b9 ldr r1, [r7, #8] 8007bf6: 481c ldr r0, [pc, #112] @ (8007c68 ) 8007bf8: f7f8 fa84 bl 8000104 <__udivsi3> 8007bfc: 0003 movs r3, r0 8007bfe: 0019 movs r1, r3 8007c00: 4b18 ldr r3, [pc, #96] @ (8007c64 ) 8007c02: 68db ldr r3, [r3, #12] 8007c04: 0a1b lsrs r3, r3, #8 8007c06: 227f movs r2, #127 @ 0x7f 8007c08: 4013 ands r3, r2 8007c0a: 434b muls r3, r1 8007c0c: 617b str r3, [r7, #20] break; 8007c0e: 46c0 nop @ (mov r8, r8) } pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U); 8007c10: 4b14 ldr r3, [pc, #80] @ (8007c64 ) 8007c12: 68db ldr r3, [r3, #12] 8007c14: 0f5b lsrs r3, r3, #29 8007c16: 2207 movs r2, #7 8007c18: 4013 ands r3, r2 8007c1a: 3301 adds r3, #1 8007c1c: 607b str r3, [r7, #4] sysclockfreq = pllvco / pllr; 8007c1e: 6879 ldr r1, [r7, #4] 8007c20: 6978 ldr r0, [r7, #20] 8007c22: f7f8 fa6f bl 8000104 <__udivsi3> 8007c26: 0003 movs r3, r0 8007c28: 613b str r3, [r7, #16] 8007c2a: e015 b.n 8007c58 } else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSE) 8007c2c: 4b0d ldr r3, [pc, #52] @ (8007c64 ) 8007c2e: 689b ldr r3, [r3, #8] 8007c30: 2238 movs r2, #56 @ 0x38 8007c32: 4013 ands r3, r2 8007c34: 2b20 cmp r3, #32 8007c36: d103 bne.n 8007c40 { /* LSE used as system clock source */ sysclockfreq = LSE_VALUE; 8007c38: 2380 movs r3, #128 @ 0x80 8007c3a: 021b lsls r3, r3, #8 8007c3c: 613b str r3, [r7, #16] 8007c3e: e00b b.n 8007c58 } else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSI) 8007c40: 4b08 ldr r3, [pc, #32] @ (8007c64 ) 8007c42: 689b ldr r3, [r3, #8] 8007c44: 2238 movs r2, #56 @ 0x38 8007c46: 4013 ands r3, r2 8007c48: 2b18 cmp r3, #24 8007c4a: d103 bne.n 8007c54 { /* LSI used as system clock source */ sysclockfreq = LSI_VALUE; 8007c4c: 23fa movs r3, #250 @ 0xfa 8007c4e: 01db lsls r3, r3, #7 8007c50: 613b str r3, [r7, #16] 8007c52: e001 b.n 8007c58 } else { sysclockfreq = 0U; 8007c54: 2300 movs r3, #0 8007c56: 613b str r3, [r7, #16] } return sysclockfreq; 8007c58: 693b ldr r3, [r7, #16] } 8007c5a: 0018 movs r0, r3 8007c5c: 46bd mov sp, r7 8007c5e: b006 add sp, #24 8007c60: bd80 pop {r7, pc} 8007c62: 46c0 nop @ (mov r8, r8) 8007c64: 40021000 .word 0x40021000 8007c68: 00f42400 .word 0x00f42400 8007c6c: 007a1200 .word 0x007a1200 08007c70 : * the RTC clock source: in this case the access to Backup domain is enabled. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 8007c70: b580 push {r7, lr} 8007c72: b086 sub sp, #24 8007c74: af00 add r7, sp, #0 8007c76: 6078 str r0, [r7, #4] uint32_t tmpregister; uint32_t tickstart; HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ 8007c78: 2313 movs r3, #19 8007c7a: 18fb adds r3, r7, r3 8007c7c: 2200 movs r2, #0 8007c7e: 701a strb r2, [r3, #0] HAL_StatusTypeDef status = HAL_OK; /* Final status */ 8007c80: 2312 movs r3, #18 8007c82: 18fb adds r3, r7, r3 8007c84: 2200 movs r2, #0 8007c86: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*-------------------------- RTC clock source configuration ----------------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) 8007c88: 687b ldr r3, [r7, #4] 8007c8a: 681a ldr r2, [r3, #0] 8007c8c: 2380 movs r3, #128 @ 0x80 8007c8e: 029b lsls r3, r3, #10 8007c90: 4013 ands r3, r2 8007c92: d100 bne.n 8007c96 8007c94: e0a3 b.n 8007dde { FlagStatus pwrclkchanged = RESET; 8007c96: 2011 movs r0, #17 8007c98: 183b adds r3, r7, r0 8007c9a: 2200 movs r2, #0 8007c9c: 701a strb r2, [r3, #0] /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable Power Clock */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 8007c9e: 4ba5 ldr r3, [pc, #660] @ (8007f34 ) 8007ca0: 6bda ldr r2, [r3, #60] @ 0x3c 8007ca2: 2380 movs r3, #128 @ 0x80 8007ca4: 055b lsls r3, r3, #21 8007ca6: 4013 ands r3, r2 8007ca8: d110 bne.n 8007ccc { __HAL_RCC_PWR_CLK_ENABLE(); 8007caa: 4ba2 ldr r3, [pc, #648] @ (8007f34 ) 8007cac: 6bda ldr r2, [r3, #60] @ 0x3c 8007cae: 4ba1 ldr r3, [pc, #644] @ (8007f34 ) 8007cb0: 2180 movs r1, #128 @ 0x80 8007cb2: 0549 lsls r1, r1, #21 8007cb4: 430a orrs r2, r1 8007cb6: 63da str r2, [r3, #60] @ 0x3c 8007cb8: 4b9e ldr r3, [pc, #632] @ (8007f34 ) 8007cba: 6bda ldr r2, [r3, #60] @ 0x3c 8007cbc: 2380 movs r3, #128 @ 0x80 8007cbe: 055b lsls r3, r3, #21 8007cc0: 4013 ands r3, r2 8007cc2: 60bb str r3, [r7, #8] 8007cc4: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 8007cc6: 183b adds r3, r7, r0 8007cc8: 2201 movs r2, #1 8007cca: 701a strb r2, [r3, #0] } /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); 8007ccc: 4b9a ldr r3, [pc, #616] @ (8007f38 ) 8007cce: 681a ldr r2, [r3, #0] 8007cd0: 4b99 ldr r3, [pc, #612] @ (8007f38 ) 8007cd2: 2180 movs r1, #128 @ 0x80 8007cd4: 0049 lsls r1, r1, #1 8007cd6: 430a orrs r2, r1 8007cd8: 601a str r2, [r3, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8007cda: f7fc fd1b bl 8004714 8007cde: 0003 movs r3, r0 8007ce0: 60fb str r3, [r7, #12] while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 8007ce2: e00b b.n 8007cfc { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8007ce4: f7fc fd16 bl 8004714 8007ce8: 0002 movs r2, r0 8007cea: 68fb ldr r3, [r7, #12] 8007cec: 1ad3 subs r3, r2, r3 8007cee: 2b02 cmp r3, #2 8007cf0: d904 bls.n 8007cfc { ret = HAL_TIMEOUT; 8007cf2: 2313 movs r3, #19 8007cf4: 18fb adds r3, r7, r3 8007cf6: 2203 movs r2, #3 8007cf8: 701a strb r2, [r3, #0] break; 8007cfa: e005 b.n 8007d08 while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 8007cfc: 4b8e ldr r3, [pc, #568] @ (8007f38 ) 8007cfe: 681a ldr r2, [r3, #0] 8007d00: 2380 movs r3, #128 @ 0x80 8007d02: 005b lsls r3, r3, #1 8007d04: 4013 ands r3, r2 8007d06: d0ed beq.n 8007ce4 } } if (ret == HAL_OK) 8007d08: 2313 movs r3, #19 8007d0a: 18fb adds r3, r7, r3 8007d0c: 781b ldrb r3, [r3, #0] 8007d0e: 2b00 cmp r3, #0 8007d10: d154 bne.n 8007dbc { /* Reset the Backup domain only if the RTC Clock source selection is modified from default */ tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL); 8007d12: 4b88 ldr r3, [pc, #544] @ (8007f34 ) 8007d14: 6dda ldr r2, [r3, #92] @ 0x5c 8007d16: 23c0 movs r3, #192 @ 0xc0 8007d18: 009b lsls r3, r3, #2 8007d1a: 4013 ands r3, r2 8007d1c: 617b str r3, [r7, #20] /* Reset the Backup domain only if the RTC Clock source selection is modified */ if ((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection)) 8007d1e: 697b ldr r3, [r7, #20] 8007d20: 2b00 cmp r3, #0 8007d22: d019 beq.n 8007d58 8007d24: 687b ldr r3, [r7, #4] 8007d26: 6a5b ldr r3, [r3, #36] @ 0x24 8007d28: 697a ldr r2, [r7, #20] 8007d2a: 429a cmp r2, r3 8007d2c: d014 beq.n 8007d58 { /* Store the content of BDCR register before the reset of Backup Domain */ tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL)); 8007d2e: 4b81 ldr r3, [pc, #516] @ (8007f34 ) 8007d30: 6ddb ldr r3, [r3, #92] @ 0x5c 8007d32: 4a82 ldr r2, [pc, #520] @ (8007f3c ) 8007d34: 4013 ands r3, r2 8007d36: 617b str r3, [r7, #20] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 8007d38: 4b7e ldr r3, [pc, #504] @ (8007f34 ) 8007d3a: 6dda ldr r2, [r3, #92] @ 0x5c 8007d3c: 4b7d ldr r3, [pc, #500] @ (8007f34 ) 8007d3e: 2180 movs r1, #128 @ 0x80 8007d40: 0249 lsls r1, r1, #9 8007d42: 430a orrs r2, r1 8007d44: 65da str r2, [r3, #92] @ 0x5c __HAL_RCC_BACKUPRESET_RELEASE(); 8007d46: 4b7b ldr r3, [pc, #492] @ (8007f34 ) 8007d48: 6dda ldr r2, [r3, #92] @ 0x5c 8007d4a: 4b7a ldr r3, [pc, #488] @ (8007f34 ) 8007d4c: 497c ldr r1, [pc, #496] @ (8007f40 ) 8007d4e: 400a ands r2, r1 8007d50: 65da str r2, [r3, #92] @ 0x5c /* Restore the Content of BDCR register */ RCC->BDCR = tmpregister; 8007d52: 4b78 ldr r3, [pc, #480] @ (8007f34 ) 8007d54: 697a ldr r2, [r7, #20] 8007d56: 65da str r2, [r3, #92] @ 0x5c } /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON)) 8007d58: 697b ldr r3, [r7, #20] 8007d5a: 2201 movs r2, #1 8007d5c: 4013 ands r3, r2 8007d5e: d016 beq.n 8007d8e { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8007d60: f7fc fcd8 bl 8004714 8007d64: 0003 movs r3, r0 8007d66: 60fb str r3, [r7, #12] /* Wait till LSE is ready */ while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 8007d68: e00c b.n 8007d84 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8007d6a: f7fc fcd3 bl 8004714 8007d6e: 0002 movs r2, r0 8007d70: 68fb ldr r3, [r7, #12] 8007d72: 1ad3 subs r3, r2, r3 8007d74: 4a73 ldr r2, [pc, #460] @ (8007f44 ) 8007d76: 4293 cmp r3, r2 8007d78: d904 bls.n 8007d84 { ret = HAL_TIMEOUT; 8007d7a: 2313 movs r3, #19 8007d7c: 18fb adds r3, r7, r3 8007d7e: 2203 movs r2, #3 8007d80: 701a strb r2, [r3, #0] break; 8007d82: e004 b.n 8007d8e while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 8007d84: 4b6b ldr r3, [pc, #428] @ (8007f34 ) 8007d86: 6ddb ldr r3, [r3, #92] @ 0x5c 8007d88: 2202 movs r2, #2 8007d8a: 4013 ands r3, r2 8007d8c: d0ed beq.n 8007d6a } } } if (ret == HAL_OK) 8007d8e: 2313 movs r3, #19 8007d90: 18fb adds r3, r7, r3 8007d92: 781b ldrb r3, [r3, #0] 8007d94: 2b00 cmp r3, #0 8007d96: d10a bne.n 8007dae { /* Apply new RTC clock source selection */ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 8007d98: 4b66 ldr r3, [pc, #408] @ (8007f34 ) 8007d9a: 6ddb ldr r3, [r3, #92] @ 0x5c 8007d9c: 4a67 ldr r2, [pc, #412] @ (8007f3c ) 8007d9e: 4013 ands r3, r2 8007da0: 0019 movs r1, r3 8007da2: 687b ldr r3, [r7, #4] 8007da4: 6a5a ldr r2, [r3, #36] @ 0x24 8007da6: 4b63 ldr r3, [pc, #396] @ (8007f34 ) 8007da8: 430a orrs r2, r1 8007daa: 65da str r2, [r3, #92] @ 0x5c 8007dac: e00c b.n 8007dc8 } else { /* set overall return value */ status = ret; 8007dae: 2312 movs r3, #18 8007db0: 18fb adds r3, r7, r3 8007db2: 2213 movs r2, #19 8007db4: 18ba adds r2, r7, r2 8007db6: 7812 ldrb r2, [r2, #0] 8007db8: 701a strb r2, [r3, #0] 8007dba: e005 b.n 8007dc8 } } else { /* set overall return value */ status = ret; 8007dbc: 2312 movs r3, #18 8007dbe: 18fb adds r3, r7, r3 8007dc0: 2213 movs r2, #19 8007dc2: 18ba adds r2, r7, r2 8007dc4: 7812 ldrb r2, [r2, #0] 8007dc6: 701a strb r2, [r3, #0] } /* Restore clock configuration if changed */ if (pwrclkchanged == SET) 8007dc8: 2311 movs r3, #17 8007dca: 18fb adds r3, r7, r3 8007dcc: 781b ldrb r3, [r3, #0] 8007dce: 2b01 cmp r3, #1 8007dd0: d105 bne.n 8007dde { __HAL_RCC_PWR_CLK_DISABLE(); 8007dd2: 4b58 ldr r3, [pc, #352] @ (8007f34 ) 8007dd4: 6bda ldr r2, [r3, #60] @ 0x3c 8007dd6: 4b57 ldr r3, [pc, #348] @ (8007f34 ) 8007dd8: 495b ldr r1, [pc, #364] @ (8007f48 ) 8007dda: 400a ands r2, r1 8007ddc: 63da str r2, [r3, #60] @ 0x3c } } /*-------------------------- USART1 clock source configuration -------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) 8007dde: 687b ldr r3, [r7, #4] 8007de0: 681b ldr r3, [r3, #0] 8007de2: 2201 movs r2, #1 8007de4: 4013 ands r3, r2 8007de6: d009 beq.n 8007dfc { /* Check the parameters */ assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); /* Configure the USART1 clock source */ __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); 8007de8: 4b52 ldr r3, [pc, #328] @ (8007f34 ) 8007dea: 6d5b ldr r3, [r3, #84] @ 0x54 8007dec: 2203 movs r2, #3 8007dee: 4393 bics r3, r2 8007df0: 0019 movs r1, r3 8007df2: 687b ldr r3, [r7, #4] 8007df4: 685a ldr r2, [r3, #4] 8007df6: 4b4f ldr r3, [pc, #316] @ (8007f34 ) 8007df8: 430a orrs r2, r1 8007dfa: 655a str r2, [r3, #84] @ 0x54 } #endif /* RCC_CCIPR_USART3SEL */ #if defined(LPUART1) /*-------------------------- LPUART1 clock source configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) 8007dfc: 687b ldr r3, [r7, #4] 8007dfe: 681b ldr r3, [r3, #0] 8007e00: 2210 movs r2, #16 8007e02: 4013 ands r3, r2 8007e04: d009 beq.n 8007e1a { /* Check the parameters */ assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection)); /* Configure the LPUART1 clock source */ __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); 8007e06: 4b4b ldr r3, [pc, #300] @ (8007f34 ) 8007e08: 6d5b ldr r3, [r3, #84] @ 0x54 8007e0a: 4a50 ldr r2, [pc, #320] @ (8007f4c ) 8007e0c: 4013 ands r3, r2 8007e0e: 0019 movs r1, r3 8007e10: 687b ldr r3, [r7, #4] 8007e12: 689a ldr r2, [r3, #8] 8007e14: 4b47 ldr r3, [pc, #284] @ (8007f34 ) 8007e16: 430a orrs r2, r1 8007e18: 655a str r2, [r3, #84] @ 0x54 } #endif /* LPUART2 */ #if defined(RCC_CCIPR_LPTIM1SEL) /*-------------------------- LPTIM1 clock source configuration -------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1)) 8007e1a: 687b ldr r3, [r7, #4] 8007e1c: 681a ldr r2, [r3, #0] 8007e1e: 2380 movs r3, #128 @ 0x80 8007e20: 009b lsls r3, r3, #2 8007e22: 4013 ands r3, r2 8007e24: d009 beq.n 8007e3a { assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection)); __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); 8007e26: 4b43 ldr r3, [pc, #268] @ (8007f34 ) 8007e28: 6d5b ldr r3, [r3, #84] @ 0x54 8007e2a: 4a49 ldr r2, [pc, #292] @ (8007f50 ) 8007e2c: 4013 ands r3, r2 8007e2e: 0019 movs r1, r3 8007e30: 687b ldr r3, [r7, #4] 8007e32: 695a ldr r2, [r3, #20] 8007e34: 4b3f ldr r3, [pc, #252] @ (8007f34 ) 8007e36: 430a orrs r2, r1 8007e38: 655a str r2, [r3, #84] @ 0x54 } #endif /* RCC_CCIPR_LPTIM1SEL */ #if defined(RCC_CCIPR_LPTIM2SEL) /*-------------------------- LPTIM2 clock source configuration -------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2)) 8007e3a: 687b ldr r3, [r7, #4] 8007e3c: 681a ldr r2, [r3, #0] 8007e3e: 2380 movs r3, #128 @ 0x80 8007e40: 00db lsls r3, r3, #3 8007e42: 4013 ands r3, r2 8007e44: d009 beq.n 8007e5a { assert_param(IS_RCC_LPTIM2CLKSOURCE(PeriphClkInit->Lptim2ClockSelection)); __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); 8007e46: 4b3b ldr r3, [pc, #236] @ (8007f34 ) 8007e48: 6d5b ldr r3, [r3, #84] @ 0x54 8007e4a: 4a42 ldr r2, [pc, #264] @ (8007f54 ) 8007e4c: 4013 ands r3, r2 8007e4e: 0019 movs r1, r3 8007e50: 687b ldr r3, [r7, #4] 8007e52: 699a ldr r2, [r3, #24] 8007e54: 4b37 ldr r3, [pc, #220] @ (8007f34 ) 8007e56: 430a orrs r2, r1 8007e58: 655a str r2, [r3, #84] @ 0x54 } #endif /* RCC_CCIPR_LPTIM2SEL */ /*-------------------------- I2C1 clock source configuration ---------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) 8007e5a: 687b ldr r3, [r7, #4] 8007e5c: 681b ldr r3, [r3, #0] 8007e5e: 2220 movs r2, #32 8007e60: 4013 ands r3, r2 8007e62: d009 beq.n 8007e78 { /* Check the parameters */ assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); /* Configure the I2C1 clock source */ __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); 8007e64: 4b33 ldr r3, [pc, #204] @ (8007f34 ) 8007e66: 6d5b ldr r3, [r3, #84] @ 0x54 8007e68: 4a3b ldr r2, [pc, #236] @ (8007f58 ) 8007e6a: 4013 ands r3, r2 8007e6c: 0019 movs r1, r3 8007e6e: 687b ldr r3, [r7, #4] 8007e70: 68da ldr r2, [r3, #12] 8007e72: 4b30 ldr r3, [pc, #192] @ (8007f34 ) 8007e74: 430a orrs r2, r1 8007e76: 655a str r2, [r3, #84] @ 0x54 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLQCLK); } } #endif /* RNG */ /*-------------------------- ADC clock source configuration ----------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 8007e78: 687b ldr r3, [r7, #4] 8007e7a: 681a ldr r2, [r3, #0] 8007e7c: 2380 movs r3, #128 @ 0x80 8007e7e: 01db lsls r3, r3, #7 8007e80: 4013 ands r3, r2 8007e82: d015 beq.n 8007eb0 { /* Check the parameters */ assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection)); /* Configure the ADC interface clock source */ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 8007e84: 4b2b ldr r3, [pc, #172] @ (8007f34 ) 8007e86: 6d5b ldr r3, [r3, #84] @ 0x54 8007e88: 009b lsls r3, r3, #2 8007e8a: 0899 lsrs r1, r3, #2 8007e8c: 687b ldr r3, [r7, #4] 8007e8e: 69da ldr r2, [r3, #28] 8007e90: 4b28 ldr r3, [pc, #160] @ (8007f34 ) 8007e92: 430a orrs r2, r1 8007e94: 655a str r2, [r3, #84] @ 0x54 if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLADC) 8007e96: 687b ldr r3, [r7, #4] 8007e98: 69da ldr r2, [r3, #28] 8007e9a: 2380 movs r3, #128 @ 0x80 8007e9c: 05db lsls r3, r3, #23 8007e9e: 429a cmp r2, r3 8007ea0: d106 bne.n 8007eb0 { /* Enable PLLPCLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLPCLK); 8007ea2: 4b24 ldr r3, [pc, #144] @ (8007f34 ) 8007ea4: 68da ldr r2, [r3, #12] 8007ea6: 4b23 ldr r3, [pc, #140] @ (8007f34 ) 8007ea8: 2180 movs r1, #128 @ 0x80 8007eaa: 0249 lsls r1, r1, #9 8007eac: 430a orrs r2, r1 8007eae: 60da str r2, [r3, #12] } #endif /* CEC */ #if defined(RCC_CCIPR_TIM1SEL) /*-------------------------- TIM1 clock source configuration ---------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) 8007eb0: 687b ldr r3, [r7, #4] 8007eb2: 681a ldr r2, [r3, #0] 8007eb4: 2380 movs r3, #128 @ 0x80 8007eb6: 039b lsls r3, r3, #14 8007eb8: 4013 ands r3, r2 8007eba: d016 beq.n 8007eea { /* Check the parameters */ assert_param(IS_RCC_TIM1CLKSOURCE(PeriphClkInit->Tim1ClockSelection)); /* Configure the TIM1 clock source */ __HAL_RCC_TIM1_CONFIG(PeriphClkInit->Tim1ClockSelection); 8007ebc: 4b1d ldr r3, [pc, #116] @ (8007f34 ) 8007ebe: 6d5b ldr r3, [r3, #84] @ 0x54 8007ec0: 4a26 ldr r2, [pc, #152] @ (8007f5c ) 8007ec2: 4013 ands r3, r2 8007ec4: 0019 movs r1, r3 8007ec6: 687b ldr r3, [r7, #4] 8007ec8: 6a1a ldr r2, [r3, #32] 8007eca: 4b1a ldr r3, [pc, #104] @ (8007f34 ) 8007ecc: 430a orrs r2, r1 8007ece: 655a str r2, [r3, #84] @ 0x54 if (PeriphClkInit->Tim1ClockSelection == RCC_TIM1CLKSOURCE_PLL) 8007ed0: 687b ldr r3, [r7, #4] 8007ed2: 6a1a ldr r2, [r3, #32] 8007ed4: 2380 movs r3, #128 @ 0x80 8007ed6: 03db lsls r3, r3, #15 8007ed8: 429a cmp r2, r3 8007eda: d106 bne.n 8007eea { /* Enable PLLQCLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLQCLK); 8007edc: 4b15 ldr r3, [pc, #84] @ (8007f34 ) 8007ede: 68da ldr r2, [r3, #12] 8007ee0: 4b14 ldr r3, [pc, #80] @ (8007f34 ) 8007ee2: 2180 movs r1, #128 @ 0x80 8007ee4: 0449 lsls r1, r1, #17 8007ee6: 430a orrs r2, r1 8007ee8: 60da str r2, [r3, #12] } } #endif /* RCC_CCIPR_TIM15SEL */ /*-------------------------- I2S1 clock source configuration ---------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) 8007eea: 687b ldr r3, [r7, #4] 8007eec: 681a ldr r2, [r3, #0] 8007eee: 2380 movs r3, #128 @ 0x80 8007ef0: 011b lsls r3, r3, #4 8007ef2: 4013 ands r3, r2 8007ef4: d016 beq.n 8007f24 { /* Check the parameters */ assert_param(IS_RCC_I2S1CLKSOURCE(PeriphClkInit->I2s1ClockSelection)); /* Configure the I2S1 clock source */ __HAL_RCC_I2S1_CONFIG(PeriphClkInit->I2s1ClockSelection); 8007ef6: 4b0f ldr r3, [pc, #60] @ (8007f34 ) 8007ef8: 6d5b ldr r3, [r3, #84] @ 0x54 8007efa: 4a19 ldr r2, [pc, #100] @ (8007f60 ) 8007efc: 4013 ands r3, r2 8007efe: 0019 movs r1, r3 8007f00: 687b ldr r3, [r7, #4] 8007f02: 691a ldr r2, [r3, #16] 8007f04: 4b0b ldr r3, [pc, #44] @ (8007f34 ) 8007f06: 430a orrs r2, r1 8007f08: 655a str r2, [r3, #84] @ 0x54 if (PeriphClkInit->I2s1ClockSelection == RCC_I2S1CLKSOURCE_PLL) 8007f0a: 687b ldr r3, [r7, #4] 8007f0c: 691a ldr r2, [r3, #16] 8007f0e: 2380 movs r3, #128 @ 0x80 8007f10: 01db lsls r3, r3, #7 8007f12: 429a cmp r2, r3 8007f14: d106 bne.n 8007f24 { /* Enable PLLPCLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLPCLK); 8007f16: 4b07 ldr r3, [pc, #28] @ (8007f34 ) 8007f18: 68da ldr r2, [r3, #12] 8007f1a: 4b06 ldr r3, [pc, #24] @ (8007f34 ) 8007f1c: 2180 movs r1, #128 @ 0x80 8007f1e: 0249 lsls r1, r1, #9 8007f20: 430a orrs r2, r1 8007f22: 60da str r2, [r3, #12] __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLQCLK); } } #endif /* FDCAN1 || FDCAN2 */ return status; 8007f24: 2312 movs r3, #18 8007f26: 18fb adds r3, r7, r3 8007f28: 781b ldrb r3, [r3, #0] } 8007f2a: 0018 movs r0, r3 8007f2c: 46bd mov sp, r7 8007f2e: b006 add sp, #24 8007f30: bd80 pop {r7, pc} 8007f32: 46c0 nop @ (mov r8, r8) 8007f34: 40021000 .word 0x40021000 8007f38: 40007000 .word 0x40007000 8007f3c: fffffcff .word 0xfffffcff 8007f40: fffeffff .word 0xfffeffff 8007f44: 00001388 .word 0x00001388 8007f48: efffffff .word 0xefffffff 8007f4c: fffff3ff .word 0xfffff3ff 8007f50: fff3ffff .word 0xfff3ffff 8007f54: ffcfffff .word 0xffcfffff 8007f58: ffffcfff .word 0xffffcfff 8007f5c: ffbfffff .word 0xffbfffff 8007f60: ffff3fff .word 0xffff3fff 08007f64 : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { 8007f64: b580 push {r7, lr} 8007f66: b082 sub sp, #8 8007f68: af00 add r7, sp, #0 8007f6a: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8007f6c: 687b ldr r3, [r7, #4] 8007f6e: 2b00 cmp r3, #0 8007f70: d101 bne.n 8007f76 { return HAL_ERROR; 8007f72: 2301 movs r3, #1 8007f74: e04a b.n 800800c assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8007f76: 687b ldr r3, [r7, #4] 8007f78: 223d movs r2, #61 @ 0x3d 8007f7a: 5c9b ldrb r3, [r3, r2] 8007f7c: b2db uxtb r3, r3 8007f7e: 2b00 cmp r3, #0 8007f80: d107 bne.n 8007f92 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8007f82: 687b ldr r3, [r7, #4] 8007f84: 223c movs r2, #60 @ 0x3c 8007f86: 2100 movs r1, #0 8007f88: 5499 strb r1, [r3, r2] } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); 8007f8a: 687b ldr r3, [r7, #4] 8007f8c: 0018 movs r0, r3 8007f8e: f7fc f9fb bl 8004388 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8007f92: 687b ldr r3, [r7, #4] 8007f94: 223d movs r2, #61 @ 0x3d 8007f96: 2102 movs r1, #2 8007f98: 5499 strb r1, [r3, r2] /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8007f9a: 687b ldr r3, [r7, #4] 8007f9c: 681a ldr r2, [r3, #0] 8007f9e: 687b ldr r3, [r7, #4] 8007fa0: 3304 adds r3, #4 8007fa2: 0019 movs r1, r3 8007fa4: 0010 movs r0, r2 8007fa6: f000 fa6b bl 8008480 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8007faa: 687b ldr r3, [r7, #4] 8007fac: 2248 movs r2, #72 @ 0x48 8007fae: 2101 movs r1, #1 8007fb0: 5499 strb r1, [r3, r2] /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8007fb2: 687b ldr r3, [r7, #4] 8007fb4: 223e movs r2, #62 @ 0x3e 8007fb6: 2101 movs r1, #1 8007fb8: 5499 strb r1, [r3, r2] 8007fba: 687b ldr r3, [r7, #4] 8007fbc: 223f movs r2, #63 @ 0x3f 8007fbe: 2101 movs r1, #1 8007fc0: 5499 strb r1, [r3, r2] 8007fc2: 687b ldr r3, [r7, #4] 8007fc4: 2240 movs r2, #64 @ 0x40 8007fc6: 2101 movs r1, #1 8007fc8: 5499 strb r1, [r3, r2] 8007fca: 687b ldr r3, [r7, #4] 8007fcc: 2241 movs r2, #65 @ 0x41 8007fce: 2101 movs r1, #1 8007fd0: 5499 strb r1, [r3, r2] 8007fd2: 687b ldr r3, [r7, #4] 8007fd4: 2242 movs r2, #66 @ 0x42 8007fd6: 2101 movs r1, #1 8007fd8: 5499 strb r1, [r3, r2] 8007fda: 687b ldr r3, [r7, #4] 8007fdc: 2243 movs r2, #67 @ 0x43 8007fde: 2101 movs r1, #1 8007fe0: 5499 strb r1, [r3, r2] TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8007fe2: 687b ldr r3, [r7, #4] 8007fe4: 2244 movs r2, #68 @ 0x44 8007fe6: 2101 movs r1, #1 8007fe8: 5499 strb r1, [r3, r2] 8007fea: 687b ldr r3, [r7, #4] 8007fec: 2245 movs r2, #69 @ 0x45 8007fee: 2101 movs r1, #1 8007ff0: 5499 strb r1, [r3, r2] 8007ff2: 687b ldr r3, [r7, #4] 8007ff4: 2246 movs r2, #70 @ 0x46 8007ff6: 2101 movs r1, #1 8007ff8: 5499 strb r1, [r3, r2] 8007ffa: 687b ldr r3, [r7, #4] 8007ffc: 2247 movs r2, #71 @ 0x47 8007ffe: 2101 movs r1, #1 8008000: 5499 strb r1, [r3, r2] /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8008002: 687b ldr r3, [r7, #4] 8008004: 223d movs r2, #61 @ 0x3d 8008006: 2101 movs r1, #1 8008008: 5499 strb r1, [r3, r2] return HAL_OK; 800800a: 2300 movs r3, #0 } 800800c: 0018 movs r0, r3 800800e: 46bd mov sp, r7 8008010: b002 add sp, #8 8008012: bd80 pop {r7, pc} 08008014 : * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() * @param htim TIM PWM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) { 8008014: b580 push {r7, lr} 8008016: b082 sub sp, #8 8008018: af00 add r7, sp, #0 800801a: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 800801c: 687b ldr r3, [r7, #4] 800801e: 2b00 cmp r3, #0 8008020: d101 bne.n 8008026 { return HAL_ERROR; 8008022: 2301 movs r3, #1 8008024: e04a b.n 80080bc assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8008026: 687b ldr r3, [r7, #4] 8008028: 223d movs r2, #61 @ 0x3d 800802a: 5c9b ldrb r3, [r3, r2] 800802c: b2db uxtb r3, r3 800802e: 2b00 cmp r3, #0 8008030: d107 bne.n 8008042 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8008032: 687b ldr r3, [r7, #4] 8008034: 223c movs r2, #60 @ 0x3c 8008036: 2100 movs r1, #0 8008038: 5499 strb r1, [r3, r2] } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->PWM_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspInit(htim); 800803a: 687b ldr r3, [r7, #4] 800803c: 0018 movs r0, r3 800803e: f000 f841 bl 80080c4 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8008042: 687b ldr r3, [r7, #4] 8008044: 223d movs r2, #61 @ 0x3d 8008046: 2102 movs r1, #2 8008048: 5499 strb r1, [r3, r2] /* Init the base time for the PWM */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 800804a: 687b ldr r3, [r7, #4] 800804c: 681a ldr r2, [r3, #0] 800804e: 687b ldr r3, [r7, #4] 8008050: 3304 adds r3, #4 8008052: 0019 movs r1, r3 8008054: 0010 movs r0, r2 8008056: f000 fa13 bl 8008480 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 800805a: 687b ldr r3, [r7, #4] 800805c: 2248 movs r2, #72 @ 0x48 800805e: 2101 movs r1, #1 8008060: 5499 strb r1, [r3, r2] /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8008062: 687b ldr r3, [r7, #4] 8008064: 223e movs r2, #62 @ 0x3e 8008066: 2101 movs r1, #1 8008068: 5499 strb r1, [r3, r2] 800806a: 687b ldr r3, [r7, #4] 800806c: 223f movs r2, #63 @ 0x3f 800806e: 2101 movs r1, #1 8008070: 5499 strb r1, [r3, r2] 8008072: 687b ldr r3, [r7, #4] 8008074: 2240 movs r2, #64 @ 0x40 8008076: 2101 movs r1, #1 8008078: 5499 strb r1, [r3, r2] 800807a: 687b ldr r3, [r7, #4] 800807c: 2241 movs r2, #65 @ 0x41 800807e: 2101 movs r1, #1 8008080: 5499 strb r1, [r3, r2] 8008082: 687b ldr r3, [r7, #4] 8008084: 2242 movs r2, #66 @ 0x42 8008086: 2101 movs r1, #1 8008088: 5499 strb r1, [r3, r2] 800808a: 687b ldr r3, [r7, #4] 800808c: 2243 movs r2, #67 @ 0x43 800808e: 2101 movs r1, #1 8008090: 5499 strb r1, [r3, r2] TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8008092: 687b ldr r3, [r7, #4] 8008094: 2244 movs r2, #68 @ 0x44 8008096: 2101 movs r1, #1 8008098: 5499 strb r1, [r3, r2] 800809a: 687b ldr r3, [r7, #4] 800809c: 2245 movs r2, #69 @ 0x45 800809e: 2101 movs r1, #1 80080a0: 5499 strb r1, [r3, r2] 80080a2: 687b ldr r3, [r7, #4] 80080a4: 2246 movs r2, #70 @ 0x46 80080a6: 2101 movs r1, #1 80080a8: 5499 strb r1, [r3, r2] 80080aa: 687b ldr r3, [r7, #4] 80080ac: 2247 movs r2, #71 @ 0x47 80080ae: 2101 movs r1, #1 80080b0: 5499 strb r1, [r3, r2] /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 80080b2: 687b ldr r3, [r7, #4] 80080b4: 223d movs r2, #61 @ 0x3d 80080b6: 2101 movs r1, #1 80080b8: 5499 strb r1, [r3, r2] return HAL_OK; 80080ba: 2300 movs r3, #0 } 80080bc: 0018 movs r0, r3 80080be: 46bd mov sp, r7 80080c0: b002 add sp, #8 80080c2: bd80 pop {r7, pc} 080080c4 : * @brief Initializes the TIM PWM MSP. * @param htim TIM PWM handle * @retval None */ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) { 80080c4: b580 push {r7, lr} 80080c6: b082 sub sp, #8 80080c8: af00 add r7, sp, #0 80080ca: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_MspInit could be implemented in the user file */ } 80080cc: 46c0 nop @ (mov r8, r8) 80080ce: 46bd mov sp, r7 80080d0: b002 add sp, #8 80080d2: bd80 pop {r7, pc} 080080d4 : * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { 80080d4: b580 push {r7, lr} 80080d6: b086 sub sp, #24 80080d8: af00 add r7, sp, #0 80080da: 60f8 str r0, [r7, #12] 80080dc: 60b9 str r1, [r7, #8] 80080de: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 80080e0: 2317 movs r3, #23 80080e2: 18fb adds r3, r7, r3 80080e4: 2200 movs r2, #0 80080e6: 701a strb r2, [r3, #0] assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); /* Process Locked */ __HAL_LOCK(htim); 80080e8: 68fb ldr r3, [r7, #12] 80080ea: 223c movs r2, #60 @ 0x3c 80080ec: 5c9b ldrb r3, [r3, r2] 80080ee: 2b01 cmp r3, #1 80080f0: d101 bne.n 80080f6 80080f2: 2302 movs r3, #2 80080f4: e0e5 b.n 80082c2 80080f6: 68fb ldr r3, [r7, #12] 80080f8: 223c movs r2, #60 @ 0x3c 80080fa: 2101 movs r1, #1 80080fc: 5499 strb r1, [r3, r2] switch (Channel) 80080fe: 687b ldr r3, [r7, #4] 8008100: 2b14 cmp r3, #20 8008102: d900 bls.n 8008106 8008104: e0d1 b.n 80082aa 8008106: 687b ldr r3, [r7, #4] 8008108: 009a lsls r2, r3, #2 800810a: 4b70 ldr r3, [pc, #448] @ (80082cc ) 800810c: 18d3 adds r3, r2, r3 800810e: 681b ldr r3, [r3, #0] 8008110: 469f mov pc, r3 { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the Channel 1 in PWM mode */ TIM_OC1_SetConfig(htim->Instance, sConfig); 8008112: 68fb ldr r3, [r7, #12] 8008114: 681b ldr r3, [r3, #0] 8008116: 68ba ldr r2, [r7, #8] 8008118: 0011 movs r1, r2 800811a: 0018 movs r0, r3 800811c: f000 fa34 bl 8008588 /* Set the Preload enable bit for channel1 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; 8008120: 68fb ldr r3, [r7, #12] 8008122: 681b ldr r3, [r3, #0] 8008124: 699a ldr r2, [r3, #24] 8008126: 68fb ldr r3, [r7, #12] 8008128: 681b ldr r3, [r3, #0] 800812a: 2108 movs r1, #8 800812c: 430a orrs r2, r1 800812e: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; 8008130: 68fb ldr r3, [r7, #12] 8008132: 681b ldr r3, [r3, #0] 8008134: 699a ldr r2, [r3, #24] 8008136: 68fb ldr r3, [r7, #12] 8008138: 681b ldr r3, [r3, #0] 800813a: 2104 movs r1, #4 800813c: 438a bics r2, r1 800813e: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode; 8008140: 68fb ldr r3, [r7, #12] 8008142: 681b ldr r3, [r3, #0] 8008144: 6999 ldr r1, [r3, #24] 8008146: 68bb ldr r3, [r7, #8] 8008148: 691a ldr r2, [r3, #16] 800814a: 68fb ldr r3, [r7, #12] 800814c: 681b ldr r3, [r3, #0] 800814e: 430a orrs r2, r1 8008150: 619a str r2, [r3, #24] break; 8008152: e0af b.n 80082b4 { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the Channel 2 in PWM mode */ TIM_OC2_SetConfig(htim->Instance, sConfig); 8008154: 68fb ldr r3, [r7, #12] 8008156: 681b ldr r3, [r3, #0] 8008158: 68ba ldr r2, [r7, #8] 800815a: 0011 movs r1, r2 800815c: 0018 movs r0, r3 800815e: f000 fa93 bl 8008688 /* Set the Preload enable bit for channel2 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; 8008162: 68fb ldr r3, [r7, #12] 8008164: 681b ldr r3, [r3, #0] 8008166: 699a ldr r2, [r3, #24] 8008168: 68fb ldr r3, [r7, #12] 800816a: 681b ldr r3, [r3, #0] 800816c: 2180 movs r1, #128 @ 0x80 800816e: 0109 lsls r1, r1, #4 8008170: 430a orrs r2, r1 8008172: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; 8008174: 68fb ldr r3, [r7, #12] 8008176: 681b ldr r3, [r3, #0] 8008178: 699a ldr r2, [r3, #24] 800817a: 68fb ldr r3, [r7, #12] 800817c: 681b ldr r3, [r3, #0] 800817e: 4954 ldr r1, [pc, #336] @ (80082d0 ) 8008180: 400a ands r2, r1 8008182: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; 8008184: 68fb ldr r3, [r7, #12] 8008186: 681b ldr r3, [r3, #0] 8008188: 6999 ldr r1, [r3, #24] 800818a: 68bb ldr r3, [r7, #8] 800818c: 691b ldr r3, [r3, #16] 800818e: 021a lsls r2, r3, #8 8008190: 68fb ldr r3, [r7, #12] 8008192: 681b ldr r3, [r3, #0] 8008194: 430a orrs r2, r1 8008196: 619a str r2, [r3, #24] break; 8008198: e08c b.n 80082b4 { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the Channel 3 in PWM mode */ TIM_OC3_SetConfig(htim->Instance, sConfig); 800819a: 68fb ldr r3, [r7, #12] 800819c: 681b ldr r3, [r3, #0] 800819e: 68ba ldr r2, [r7, #8] 80081a0: 0011 movs r1, r2 80081a2: 0018 movs r0, r3 80081a4: f000 faee bl 8008784 /* Set the Preload enable bit for channel3 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; 80081a8: 68fb ldr r3, [r7, #12] 80081aa: 681b ldr r3, [r3, #0] 80081ac: 69da ldr r2, [r3, #28] 80081ae: 68fb ldr r3, [r7, #12] 80081b0: 681b ldr r3, [r3, #0] 80081b2: 2108 movs r1, #8 80081b4: 430a orrs r2, r1 80081b6: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; 80081b8: 68fb ldr r3, [r7, #12] 80081ba: 681b ldr r3, [r3, #0] 80081bc: 69da ldr r2, [r3, #28] 80081be: 68fb ldr r3, [r7, #12] 80081c0: 681b ldr r3, [r3, #0] 80081c2: 2104 movs r1, #4 80081c4: 438a bics r2, r1 80081c6: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode; 80081c8: 68fb ldr r3, [r7, #12] 80081ca: 681b ldr r3, [r3, #0] 80081cc: 69d9 ldr r1, [r3, #28] 80081ce: 68bb ldr r3, [r7, #8] 80081d0: 691a ldr r2, [r3, #16] 80081d2: 68fb ldr r3, [r7, #12] 80081d4: 681b ldr r3, [r3, #0] 80081d6: 430a orrs r2, r1 80081d8: 61da str r2, [r3, #28] break; 80081da: e06b b.n 80082b4 { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the Channel 4 in PWM mode */ TIM_OC4_SetConfig(htim->Instance, sConfig); 80081dc: 68fb ldr r3, [r7, #12] 80081de: 681b ldr r3, [r3, #0] 80081e0: 68ba ldr r2, [r7, #8] 80081e2: 0011 movs r1, r2 80081e4: 0018 movs r0, r3 80081e6: f000 fb4f bl 8008888 /* Set the Preload enable bit for channel4 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; 80081ea: 68fb ldr r3, [r7, #12] 80081ec: 681b ldr r3, [r3, #0] 80081ee: 69da ldr r2, [r3, #28] 80081f0: 68fb ldr r3, [r7, #12] 80081f2: 681b ldr r3, [r3, #0] 80081f4: 2180 movs r1, #128 @ 0x80 80081f6: 0109 lsls r1, r1, #4 80081f8: 430a orrs r2, r1 80081fa: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; 80081fc: 68fb ldr r3, [r7, #12] 80081fe: 681b ldr r3, [r3, #0] 8008200: 69da ldr r2, [r3, #28] 8008202: 68fb ldr r3, [r7, #12] 8008204: 681b ldr r3, [r3, #0] 8008206: 4932 ldr r1, [pc, #200] @ (80082d0 ) 8008208: 400a ands r2, r1 800820a: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; 800820c: 68fb ldr r3, [r7, #12] 800820e: 681b ldr r3, [r3, #0] 8008210: 69d9 ldr r1, [r3, #28] 8008212: 68bb ldr r3, [r7, #8] 8008214: 691b ldr r3, [r3, #16] 8008216: 021a lsls r2, r3, #8 8008218: 68fb ldr r3, [r7, #12] 800821a: 681b ldr r3, [r3, #0] 800821c: 430a orrs r2, r1 800821e: 61da str r2, [r3, #28] break; 8008220: e048 b.n 80082b4 { /* Check the parameters */ assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); /* Configure the Channel 5 in PWM mode */ TIM_OC5_SetConfig(htim->Instance, sConfig); 8008222: 68fb ldr r3, [r7, #12] 8008224: 681b ldr r3, [r3, #0] 8008226: 68ba ldr r2, [r7, #8] 8008228: 0011 movs r1, r2 800822a: 0018 movs r0, r3 800822c: f000 fb90 bl 8008950 /* Set the Preload enable bit for channel5*/ htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; 8008230: 68fb ldr r3, [r7, #12] 8008232: 681b ldr r3, [r3, #0] 8008234: 6d5a ldr r2, [r3, #84] @ 0x54 8008236: 68fb ldr r3, [r7, #12] 8008238: 681b ldr r3, [r3, #0] 800823a: 2108 movs r1, #8 800823c: 430a orrs r2, r1 800823e: 655a str r2, [r3, #84] @ 0x54 /* Configure the Output Fast mode */ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; 8008240: 68fb ldr r3, [r7, #12] 8008242: 681b ldr r3, [r3, #0] 8008244: 6d5a ldr r2, [r3, #84] @ 0x54 8008246: 68fb ldr r3, [r7, #12] 8008248: 681b ldr r3, [r3, #0] 800824a: 2104 movs r1, #4 800824c: 438a bics r2, r1 800824e: 655a str r2, [r3, #84] @ 0x54 htim->Instance->CCMR3 |= sConfig->OCFastMode; 8008250: 68fb ldr r3, [r7, #12] 8008252: 681b ldr r3, [r3, #0] 8008254: 6d59 ldr r1, [r3, #84] @ 0x54 8008256: 68bb ldr r3, [r7, #8] 8008258: 691a ldr r2, [r3, #16] 800825a: 68fb ldr r3, [r7, #12] 800825c: 681b ldr r3, [r3, #0] 800825e: 430a orrs r2, r1 8008260: 655a str r2, [r3, #84] @ 0x54 break; 8008262: e027 b.n 80082b4 { /* Check the parameters */ assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); /* Configure the Channel 6 in PWM mode */ TIM_OC6_SetConfig(htim->Instance, sConfig); 8008264: 68fb ldr r3, [r7, #12] 8008266: 681b ldr r3, [r3, #0] 8008268: 68ba ldr r2, [r7, #8] 800826a: 0011 movs r1, r2 800826c: 0018 movs r0, r3 800826e: f000 fbc9 bl 8008a04 /* Set the Preload enable bit for channel6 */ htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; 8008272: 68fb ldr r3, [r7, #12] 8008274: 681b ldr r3, [r3, #0] 8008276: 6d5a ldr r2, [r3, #84] @ 0x54 8008278: 68fb ldr r3, [r7, #12] 800827a: 681b ldr r3, [r3, #0] 800827c: 2180 movs r1, #128 @ 0x80 800827e: 0109 lsls r1, r1, #4 8008280: 430a orrs r2, r1 8008282: 655a str r2, [r3, #84] @ 0x54 /* Configure the Output Fast mode */ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; 8008284: 68fb ldr r3, [r7, #12] 8008286: 681b ldr r3, [r3, #0] 8008288: 6d5a ldr r2, [r3, #84] @ 0x54 800828a: 68fb ldr r3, [r7, #12] 800828c: 681b ldr r3, [r3, #0] 800828e: 4910 ldr r1, [pc, #64] @ (80082d0 ) 8008290: 400a ands r2, r1 8008292: 655a str r2, [r3, #84] @ 0x54 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; 8008294: 68fb ldr r3, [r7, #12] 8008296: 681b ldr r3, [r3, #0] 8008298: 6d59 ldr r1, [r3, #84] @ 0x54 800829a: 68bb ldr r3, [r7, #8] 800829c: 691b ldr r3, [r3, #16] 800829e: 021a lsls r2, r3, #8 80082a0: 68fb ldr r3, [r7, #12] 80082a2: 681b ldr r3, [r3, #0] 80082a4: 430a orrs r2, r1 80082a6: 655a str r2, [r3, #84] @ 0x54 break; 80082a8: e004 b.n 80082b4 } default: status = HAL_ERROR; 80082aa: 2317 movs r3, #23 80082ac: 18fb adds r3, r7, r3 80082ae: 2201 movs r2, #1 80082b0: 701a strb r2, [r3, #0] break; 80082b2: 46c0 nop @ (mov r8, r8) } __HAL_UNLOCK(htim); 80082b4: 68fb ldr r3, [r7, #12] 80082b6: 223c movs r2, #60 @ 0x3c 80082b8: 2100 movs r1, #0 80082ba: 5499 strb r1, [r3, r2] return status; 80082bc: 2317 movs r3, #23 80082be: 18fb adds r3, r7, r3 80082c0: 781b ldrb r3, [r3, #0] } 80082c2: 0018 movs r0, r3 80082c4: 46bd mov sp, r7 80082c6: b006 add sp, #24 80082c8: bd80 pop {r7, pc} 80082ca: 46c0 nop @ (mov r8, r8) 80082cc: 08009edc .word 0x08009edc 80082d0: fffffbff .word 0xfffffbff 080082d4 : * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) { 80082d4: b580 push {r7, lr} 80082d6: b084 sub sp, #16 80082d8: af00 add r7, sp, #0 80082da: 6078 str r0, [r7, #4] 80082dc: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 80082de: 230f movs r3, #15 80082e0: 18fb adds r3, r7, r3 80082e2: 2200 movs r2, #0 80082e4: 701a strb r2, [r3, #0] uint32_t tmpsmcr; /* Process Locked */ __HAL_LOCK(htim); 80082e6: 687b ldr r3, [r7, #4] 80082e8: 223c movs r2, #60 @ 0x3c 80082ea: 5c9b ldrb r3, [r3, r2] 80082ec: 2b01 cmp r3, #1 80082ee: d101 bne.n 80082f4 80082f0: 2302 movs r3, #2 80082f2: e0bc b.n 800846e 80082f4: 687b ldr r3, [r7, #4] 80082f6: 223c movs r2, #60 @ 0x3c 80082f8: 2101 movs r1, #1 80082fa: 5499 strb r1, [r3, r2] htim->State = HAL_TIM_STATE_BUSY; 80082fc: 687b ldr r3, [r7, #4] 80082fe: 223d movs r2, #61 @ 0x3d 8008300: 2102 movs r1, #2 8008302: 5499 strb r1, [r3, r2] /* Check the parameters */ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ tmpsmcr = htim->Instance->SMCR; 8008304: 687b ldr r3, [r7, #4] 8008306: 681b ldr r3, [r3, #0] 8008308: 689b ldr r3, [r3, #8] 800830a: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); 800830c: 68bb ldr r3, [r7, #8] 800830e: 4a5a ldr r2, [pc, #360] @ (8008478 ) 8008310: 4013 ands r3, r2 8008312: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 8008314: 68bb ldr r3, [r7, #8] 8008316: 4a59 ldr r2, [pc, #356] @ (800847c ) 8008318: 4013 ands r3, r2 800831a: 60bb str r3, [r7, #8] htim->Instance->SMCR = tmpsmcr; 800831c: 687b ldr r3, [r7, #4] 800831e: 681b ldr r3, [r3, #0] 8008320: 68ba ldr r2, [r7, #8] 8008322: 609a str r2, [r3, #8] switch (sClockSourceConfig->ClockSource) 8008324: 683b ldr r3, [r7, #0] 8008326: 681b ldr r3, [r3, #0] 8008328: 2280 movs r2, #128 @ 0x80 800832a: 0192 lsls r2, r2, #6 800832c: 4293 cmp r3, r2 800832e: d040 beq.n 80083b2 8008330: 2280 movs r2, #128 @ 0x80 8008332: 0192 lsls r2, r2, #6 8008334: 4293 cmp r3, r2 8008336: d900 bls.n 800833a 8008338: e088 b.n 800844c 800833a: 2280 movs r2, #128 @ 0x80 800833c: 0152 lsls r2, r2, #5 800833e: 4293 cmp r3, r2 8008340: d100 bne.n 8008344 8008342: e088 b.n 8008456 8008344: 2280 movs r2, #128 @ 0x80 8008346: 0152 lsls r2, r2, #5 8008348: 4293 cmp r3, r2 800834a: d900 bls.n 800834e 800834c: e07e b.n 800844c 800834e: 2b70 cmp r3, #112 @ 0x70 8008350: d018 beq.n 8008384 8008352: d900 bls.n 8008356 8008354: e07a b.n 800844c 8008356: 2b60 cmp r3, #96 @ 0x60 8008358: d04f beq.n 80083fa 800835a: d900 bls.n 800835e 800835c: e076 b.n 800844c 800835e: 2b50 cmp r3, #80 @ 0x50 8008360: d03b beq.n 80083da 8008362: d900 bls.n 8008366 8008364: e072 b.n 800844c 8008366: 2b40 cmp r3, #64 @ 0x40 8008368: d057 beq.n 800841a 800836a: d900 bls.n 800836e 800836c: e06e b.n 800844c 800836e: 2b30 cmp r3, #48 @ 0x30 8008370: d063 beq.n 800843a 8008372: d86b bhi.n 800844c 8008374: 2b20 cmp r3, #32 8008376: d060 beq.n 800843a 8008378: d868 bhi.n 800844c 800837a: 2b00 cmp r3, #0 800837c: d05d beq.n 800843a 800837e: 2b10 cmp r3, #16 8008380: d05b beq.n 800843a 8008382: e063 b.n 800844c assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 8008384: 687b ldr r3, [r7, #4] 8008386: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 8008388: 683b ldr r3, [r7, #0] 800838a: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 800838c: 683b ldr r3, [r7, #0] 800838e: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 8008390: 683b ldr r3, [r7, #0] 8008392: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 8008394: f000 fc10 bl 8008bb8 /* Select the External clock mode1 and the ETRF trigger */ tmpsmcr = htim->Instance->SMCR; 8008398: 687b ldr r3, [r7, #4] 800839a: 681b ldr r3, [r3, #0] 800839c: 689b ldr r3, [r3, #8] 800839e: 60bb str r3, [r7, #8] tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); 80083a0: 68bb ldr r3, [r7, #8] 80083a2: 2277 movs r2, #119 @ 0x77 80083a4: 4313 orrs r3, r2 80083a6: 60bb str r3, [r7, #8] /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 80083a8: 687b ldr r3, [r7, #4] 80083aa: 681b ldr r3, [r3, #0] 80083ac: 68ba ldr r2, [r7, #8] 80083ae: 609a str r2, [r3, #8] break; 80083b0: e052 b.n 8008458 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 80083b2: 687b ldr r3, [r7, #4] 80083b4: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 80083b6: 683b ldr r3, [r7, #0] 80083b8: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 80083ba: 683b ldr r3, [r7, #0] 80083bc: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 80083be: 683b ldr r3, [r7, #0] 80083c0: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 80083c2: f000 fbf9 bl 8008bb8 /* Enable the External clock mode2 */ htim->Instance->SMCR |= TIM_SMCR_ECE; 80083c6: 687b ldr r3, [r7, #4] 80083c8: 681b ldr r3, [r3, #0] 80083ca: 689a ldr r2, [r3, #8] 80083cc: 687b ldr r3, [r7, #4] 80083ce: 681b ldr r3, [r3, #0] 80083d0: 2180 movs r1, #128 @ 0x80 80083d2: 01c9 lsls r1, r1, #7 80083d4: 430a orrs r2, r1 80083d6: 609a str r2, [r3, #8] break; 80083d8: e03e b.n 8008458 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 80083da: 687b ldr r3, [r7, #4] 80083dc: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 80083de: 683b ldr r3, [r7, #0] 80083e0: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 80083e2: 683b ldr r3, [r7, #0] 80083e4: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 80083e6: 001a movs r2, r3 80083e8: f000 fb6a bl 8008ac0 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); 80083ec: 687b ldr r3, [r7, #4] 80083ee: 681b ldr r3, [r3, #0] 80083f0: 2150 movs r1, #80 @ 0x50 80083f2: 0018 movs r0, r3 80083f4: f000 fbc4 bl 8008b80 break; 80083f8: e02e b.n 8008458 /* Check TI2 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI2_ConfigInputStage(htim->Instance, 80083fa: 687b ldr r3, [r7, #4] 80083fc: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 80083fe: 683b ldr r3, [r7, #0] 8008400: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 8008402: 683b ldr r3, [r7, #0] 8008404: 68db ldr r3, [r3, #12] TIM_TI2_ConfigInputStage(htim->Instance, 8008406: 001a movs r2, r3 8008408: f000 fb88 bl 8008b1c TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); 800840c: 687b ldr r3, [r7, #4] 800840e: 681b ldr r3, [r3, #0] 8008410: 2160 movs r1, #96 @ 0x60 8008412: 0018 movs r0, r3 8008414: f000 fbb4 bl 8008b80 break; 8008418: e01e b.n 8008458 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 800841a: 687b ldr r3, [r7, #4] 800841c: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 800841e: 683b ldr r3, [r7, #0] 8008420: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 8008422: 683b ldr r3, [r7, #0] 8008424: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 8008426: 001a movs r2, r3 8008428: f000 fb4a bl 8008ac0 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); 800842c: 687b ldr r3, [r7, #4] 800842e: 681b ldr r3, [r3, #0] 8008430: 2140 movs r1, #64 @ 0x40 8008432: 0018 movs r0, r3 8008434: f000 fba4 bl 8008b80 break; 8008438: e00e b.n 8008458 case TIM_CLOCKSOURCE_ITR3: { /* Check whether or not the timer instance supports internal trigger input */ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); 800843a: 687b ldr r3, [r7, #4] 800843c: 681a ldr r2, [r3, #0] 800843e: 683b ldr r3, [r7, #0] 8008440: 681b ldr r3, [r3, #0] 8008442: 0019 movs r1, r3 8008444: 0010 movs r0, r2 8008446: f000 fb9b bl 8008b80 break; 800844a: e005 b.n 8008458 } default: status = HAL_ERROR; 800844c: 230f movs r3, #15 800844e: 18fb adds r3, r7, r3 8008450: 2201 movs r2, #1 8008452: 701a strb r2, [r3, #0] break; 8008454: e000 b.n 8008458 break; 8008456: 46c0 nop @ (mov r8, r8) } htim->State = HAL_TIM_STATE_READY; 8008458: 687b ldr r3, [r7, #4] 800845a: 223d movs r2, #61 @ 0x3d 800845c: 2101 movs r1, #1 800845e: 5499 strb r1, [r3, r2] __HAL_UNLOCK(htim); 8008460: 687b ldr r3, [r7, #4] 8008462: 223c movs r2, #60 @ 0x3c 8008464: 2100 movs r1, #0 8008466: 5499 strb r1, [r3, r2] return status; 8008468: 230f movs r3, #15 800846a: 18fb adds r3, r7, r3 800846c: 781b ldrb r3, [r3, #0] } 800846e: 0018 movs r0, r3 8008470: 46bd mov sp, r7 8008472: b004 add sp, #16 8008474: bd80 pop {r7, pc} 8008476: 46c0 nop @ (mov r8, r8) 8008478: ffceff88 .word 0xffceff88 800847c: ffff00ff .word 0xffff00ff 08008480 : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { 8008480: b580 push {r7, lr} 8008482: b084 sub sp, #16 8008484: af00 add r7, sp, #0 8008486: 6078 str r0, [r7, #4] 8008488: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 800848a: 687b ldr r3, [r7, #4] 800848c: 681b ldr r3, [r3, #0] 800848e: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 8008490: 687b ldr r3, [r7, #4] 8008492: 4a37 ldr r2, [pc, #220] @ (8008570 ) 8008494: 4293 cmp r3, r2 8008496: d008 beq.n 80084aa 8008498: 687a ldr r2, [r7, #4] 800849a: 2380 movs r3, #128 @ 0x80 800849c: 05db lsls r3, r3, #23 800849e: 429a cmp r2, r3 80084a0: d003 beq.n 80084aa 80084a2: 687b ldr r3, [r7, #4] 80084a4: 4a33 ldr r2, [pc, #204] @ (8008574 ) 80084a6: 4293 cmp r3, r2 80084a8: d108 bne.n 80084bc { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 80084aa: 68fb ldr r3, [r7, #12] 80084ac: 2270 movs r2, #112 @ 0x70 80084ae: 4393 bics r3, r2 80084b0: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 80084b2: 683b ldr r3, [r7, #0] 80084b4: 685b ldr r3, [r3, #4] 80084b6: 68fa ldr r2, [r7, #12] 80084b8: 4313 orrs r3, r2 80084ba: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 80084bc: 687b ldr r3, [r7, #4] 80084be: 4a2c ldr r2, [pc, #176] @ (8008570 ) 80084c0: 4293 cmp r3, r2 80084c2: d014 beq.n 80084ee 80084c4: 687a ldr r2, [r7, #4] 80084c6: 2380 movs r3, #128 @ 0x80 80084c8: 05db lsls r3, r3, #23 80084ca: 429a cmp r2, r3 80084cc: d00f beq.n 80084ee 80084ce: 687b ldr r3, [r7, #4] 80084d0: 4a28 ldr r2, [pc, #160] @ (8008574 ) 80084d2: 4293 cmp r3, r2 80084d4: d00b beq.n 80084ee 80084d6: 687b ldr r3, [r7, #4] 80084d8: 4a27 ldr r2, [pc, #156] @ (8008578 ) 80084da: 4293 cmp r3, r2 80084dc: d007 beq.n 80084ee 80084de: 687b ldr r3, [r7, #4] 80084e0: 4a26 ldr r2, [pc, #152] @ (800857c ) 80084e2: 4293 cmp r3, r2 80084e4: d003 beq.n 80084ee 80084e6: 687b ldr r3, [r7, #4] 80084e8: 4a25 ldr r2, [pc, #148] @ (8008580 ) 80084ea: 4293 cmp r3, r2 80084ec: d108 bne.n 8008500 { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 80084ee: 68fb ldr r3, [r7, #12] 80084f0: 4a24 ldr r2, [pc, #144] @ (8008584 ) 80084f2: 4013 ands r3, r2 80084f4: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 80084f6: 683b ldr r3, [r7, #0] 80084f8: 68db ldr r3, [r3, #12] 80084fa: 68fa ldr r2, [r7, #12] 80084fc: 4313 orrs r3, r2 80084fe: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 8008500: 68fb ldr r3, [r7, #12] 8008502: 2280 movs r2, #128 @ 0x80 8008504: 4393 bics r3, r2 8008506: 001a movs r2, r3 8008508: 683b ldr r3, [r7, #0] 800850a: 695b ldr r3, [r3, #20] 800850c: 4313 orrs r3, r2 800850e: 60fb str r3, [r7, #12] TIMx->CR1 = tmpcr1; 8008510: 687b ldr r3, [r7, #4] 8008512: 68fa ldr r2, [r7, #12] 8008514: 601a str r2, [r3, #0] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 8008516: 683b ldr r3, [r7, #0] 8008518: 689a ldr r2, [r3, #8] 800851a: 687b ldr r3, [r7, #4] 800851c: 62da str r2, [r3, #44] @ 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 800851e: 683b ldr r3, [r7, #0] 8008520: 681a ldr r2, [r3, #0] 8008522: 687b ldr r3, [r7, #4] 8008524: 629a str r2, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 8008526: 687b ldr r3, [r7, #4] 8008528: 4a11 ldr r2, [pc, #68] @ (8008570 ) 800852a: 4293 cmp r3, r2 800852c: d007 beq.n 800853e 800852e: 687b ldr r3, [r7, #4] 8008530: 4a12 ldr r2, [pc, #72] @ (800857c ) 8008532: 4293 cmp r3, r2 8008534: d003 beq.n 800853e 8008536: 687b ldr r3, [r7, #4] 8008538: 4a11 ldr r2, [pc, #68] @ (8008580 ) 800853a: 4293 cmp r3, r2 800853c: d103 bne.n 8008546 { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 800853e: 683b ldr r3, [r7, #0] 8008540: 691a ldr r2, [r3, #16] 8008542: 687b ldr r3, [r7, #4] 8008544: 631a str r2, [r3, #48] @ 0x30 } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 8008546: 687b ldr r3, [r7, #4] 8008548: 2201 movs r2, #1 800854a: 615a str r2, [r3, #20] /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) 800854c: 687b ldr r3, [r7, #4] 800854e: 691b ldr r3, [r3, #16] 8008550: 2201 movs r2, #1 8008552: 4013 ands r3, r2 8008554: 2b01 cmp r3, #1 8008556: d106 bne.n 8008566 { /* Clear the update flag */ CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); 8008558: 687b ldr r3, [r7, #4] 800855a: 691b ldr r3, [r3, #16] 800855c: 2201 movs r2, #1 800855e: 4393 bics r3, r2 8008560: 001a movs r2, r3 8008562: 687b ldr r3, [r7, #4] 8008564: 611a str r2, [r3, #16] } } 8008566: 46c0 nop @ (mov r8, r8) 8008568: 46bd mov sp, r7 800856a: b004 add sp, #16 800856c: bd80 pop {r7, pc} 800856e: 46c0 nop @ (mov r8, r8) 8008570: 40012c00 .word 0x40012c00 8008574: 40000400 .word 0x40000400 8008578: 40002000 .word 0x40002000 800857c: 40014400 .word 0x40014400 8008580: 40014800 .word 0x40014800 8008584: fffffcff .word 0xfffffcff 08008588 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8008588: b580 push {r7, lr} 800858a: b086 sub sp, #24 800858c: af00 add r7, sp, #0 800858e: 6078 str r0, [r7, #4] 8008590: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8008592: 687b ldr r3, [r7, #4] 8008594: 6a1b ldr r3, [r3, #32] 8008596: 617b str r3, [r7, #20] /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; 8008598: 687b ldr r3, [r7, #4] 800859a: 6a1b ldr r3, [r3, #32] 800859c: 2201 movs r2, #1 800859e: 4393 bics r3, r2 80085a0: 001a movs r2, r3 80085a2: 687b ldr r3, [r7, #4] 80085a4: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 80085a6: 687b ldr r3, [r7, #4] 80085a8: 685b ldr r3, [r3, #4] 80085aa: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 80085ac: 687b ldr r3, [r7, #4] 80085ae: 699b ldr r3, [r3, #24] 80085b0: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~TIM_CCMR1_OC1M; 80085b2: 68fb ldr r3, [r7, #12] 80085b4: 4a2e ldr r2, [pc, #184] @ (8008670 ) 80085b6: 4013 ands r3, r2 80085b8: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC1S; 80085ba: 68fb ldr r3, [r7, #12] 80085bc: 2203 movs r2, #3 80085be: 4393 bics r3, r2 80085c0: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 80085c2: 683b ldr r3, [r7, #0] 80085c4: 681b ldr r3, [r3, #0] 80085c6: 68fa ldr r2, [r7, #12] 80085c8: 4313 orrs r3, r2 80085ca: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC1P; 80085cc: 697b ldr r3, [r7, #20] 80085ce: 2202 movs r2, #2 80085d0: 4393 bics r3, r2 80085d2: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= OC_Config->OCPolarity; 80085d4: 683b ldr r3, [r7, #0] 80085d6: 689b ldr r3, [r3, #8] 80085d8: 697a ldr r2, [r7, #20] 80085da: 4313 orrs r3, r2 80085dc: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) 80085de: 687b ldr r3, [r7, #4] 80085e0: 4a24 ldr r2, [pc, #144] @ (8008674 ) 80085e2: 4293 cmp r3, r2 80085e4: d007 beq.n 80085f6 80085e6: 687b ldr r3, [r7, #4] 80085e8: 4a23 ldr r2, [pc, #140] @ (8008678 ) 80085ea: 4293 cmp r3, r2 80085ec: d003 beq.n 80085f6 80085ee: 687b ldr r3, [r7, #4] 80085f0: 4a22 ldr r2, [pc, #136] @ (800867c ) 80085f2: 4293 cmp r3, r2 80085f4: d10c bne.n 8008610 { /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; 80085f6: 697b ldr r3, [r7, #20] 80085f8: 2208 movs r2, #8 80085fa: 4393 bics r3, r2 80085fc: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; 80085fe: 683b ldr r3, [r7, #0] 8008600: 68db ldr r3, [r3, #12] 8008602: 697a ldr r2, [r7, #20] 8008604: 4313 orrs r3, r2 8008606: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC1NE; 8008608: 697b ldr r3, [r7, #20] 800860a: 2204 movs r2, #4 800860c: 4393 bics r3, r2 800860e: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8008610: 687b ldr r3, [r7, #4] 8008612: 4a18 ldr r2, [pc, #96] @ (8008674 ) 8008614: 4293 cmp r3, r2 8008616: d007 beq.n 8008628 8008618: 687b ldr r3, [r7, #4] 800861a: 4a17 ldr r2, [pc, #92] @ (8008678 ) 800861c: 4293 cmp r3, r2 800861e: d003 beq.n 8008628 8008620: 687b ldr r3, [r7, #4] 8008622: 4a16 ldr r2, [pc, #88] @ (800867c ) 8008624: 4293 cmp r3, r2 8008626: d111 bne.n 800864c /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS1; 8008628: 693b ldr r3, [r7, #16] 800862a: 4a15 ldr r2, [pc, #84] @ (8008680 ) 800862c: 4013 ands r3, r2 800862e: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS1N; 8008630: 693b ldr r3, [r7, #16] 8008632: 4a14 ldr r2, [pc, #80] @ (8008684 ) 8008634: 4013 ands r3, r2 8008636: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= OC_Config->OCIdleState; 8008638: 683b ldr r3, [r7, #0] 800863a: 695b ldr r3, [r3, #20] 800863c: 693a ldr r2, [r7, #16] 800863e: 4313 orrs r3, r2 8008640: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= OC_Config->OCNIdleState; 8008642: 683b ldr r3, [r7, #0] 8008644: 699b ldr r3, [r3, #24] 8008646: 693a ldr r2, [r7, #16] 8008648: 4313 orrs r3, r2 800864a: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 800864c: 687b ldr r3, [r7, #4] 800864e: 693a ldr r2, [r7, #16] 8008650: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 8008652: 687b ldr r3, [r7, #4] 8008654: 68fa ldr r2, [r7, #12] 8008656: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR1 = OC_Config->Pulse; 8008658: 683b ldr r3, [r7, #0] 800865a: 685a ldr r2, [r3, #4] 800865c: 687b ldr r3, [r7, #4] 800865e: 635a str r2, [r3, #52] @ 0x34 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8008660: 687b ldr r3, [r7, #4] 8008662: 697a ldr r2, [r7, #20] 8008664: 621a str r2, [r3, #32] } 8008666: 46c0 nop @ (mov r8, r8) 8008668: 46bd mov sp, r7 800866a: b006 add sp, #24 800866c: bd80 pop {r7, pc} 800866e: 46c0 nop @ (mov r8, r8) 8008670: fffeff8f .word 0xfffeff8f 8008674: 40012c00 .word 0x40012c00 8008678: 40014400 .word 0x40014400 800867c: 40014800 .word 0x40014800 8008680: fffffeff .word 0xfffffeff 8008684: fffffdff .word 0xfffffdff 08008688 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8008688: b580 push {r7, lr} 800868a: b086 sub sp, #24 800868c: af00 add r7, sp, #0 800868e: 6078 str r0, [r7, #4] 8008690: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8008692: 687b ldr r3, [r7, #4] 8008694: 6a1b ldr r3, [r3, #32] 8008696: 617b str r3, [r7, #20] /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; 8008698: 687b ldr r3, [r7, #4] 800869a: 6a1b ldr r3, [r3, #32] 800869c: 2210 movs r2, #16 800869e: 4393 bics r3, r2 80086a0: 001a movs r2, r3 80086a2: 687b ldr r3, [r7, #4] 80086a4: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 80086a6: 687b ldr r3, [r7, #4] 80086a8: 685b ldr r3, [r3, #4] 80086aa: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 80086ac: 687b ldr r3, [r7, #4] 80086ae: 699b ldr r3, [r3, #24] 80086b0: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR1_OC2M; 80086b2: 68fb ldr r3, [r7, #12] 80086b4: 4a2c ldr r2, [pc, #176] @ (8008768 ) 80086b6: 4013 ands r3, r2 80086b8: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC2S; 80086ba: 68fb ldr r3, [r7, #12] 80086bc: 4a2b ldr r2, [pc, #172] @ (800876c ) 80086be: 4013 ands r3, r2 80086c0: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 80086c2: 683b ldr r3, [r7, #0] 80086c4: 681b ldr r3, [r3, #0] 80086c6: 021b lsls r3, r3, #8 80086c8: 68fa ldr r2, [r7, #12] 80086ca: 4313 orrs r3, r2 80086cc: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC2P; 80086ce: 697b ldr r3, [r7, #20] 80086d0: 2220 movs r2, #32 80086d2: 4393 bics r3, r2 80086d4: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 4U); 80086d6: 683b ldr r3, [r7, #0] 80086d8: 689b ldr r3, [r3, #8] 80086da: 011b lsls r3, r3, #4 80086dc: 697a ldr r2, [r7, #20] 80086de: 4313 orrs r3, r2 80086e0: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) 80086e2: 687b ldr r3, [r7, #4] 80086e4: 4a22 ldr r2, [pc, #136] @ (8008770 ) 80086e6: 4293 cmp r3, r2 80086e8: d10d bne.n 8008706 { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; 80086ea: 697b ldr r3, [r7, #20] 80086ec: 2280 movs r2, #128 @ 0x80 80086ee: 4393 bics r3, r2 80086f0: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 4U); 80086f2: 683b ldr r3, [r7, #0] 80086f4: 68db ldr r3, [r3, #12] 80086f6: 011b lsls r3, r3, #4 80086f8: 697a ldr r2, [r7, #20] 80086fa: 4313 orrs r3, r2 80086fc: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; 80086fe: 697b ldr r3, [r7, #20] 8008700: 2240 movs r2, #64 @ 0x40 8008702: 4393 bics r3, r2 8008704: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8008706: 687b ldr r3, [r7, #4] 8008708: 4a19 ldr r2, [pc, #100] @ (8008770 ) 800870a: 4293 cmp r3, r2 800870c: d007 beq.n 800871e 800870e: 687b ldr r3, [r7, #4] 8008710: 4a18 ldr r2, [pc, #96] @ (8008774 ) 8008712: 4293 cmp r3, r2 8008714: d003 beq.n 800871e 8008716: 687b ldr r3, [r7, #4] 8008718: 4a17 ldr r2, [pc, #92] @ (8008778 ) 800871a: 4293 cmp r3, r2 800871c: d113 bne.n 8008746 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS2; 800871e: 693b ldr r3, [r7, #16] 8008720: 4a16 ldr r2, [pc, #88] @ (800877c ) 8008722: 4013 ands r3, r2 8008724: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS2N; 8008726: 693b ldr r3, [r7, #16] 8008728: 4a15 ldr r2, [pc, #84] @ (8008780 ) 800872a: 4013 ands r3, r2 800872c: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 2U); 800872e: 683b ldr r3, [r7, #0] 8008730: 695b ldr r3, [r3, #20] 8008732: 009b lsls r3, r3, #2 8008734: 693a ldr r2, [r7, #16] 8008736: 4313 orrs r3, r2 8008738: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 2U); 800873a: 683b ldr r3, [r7, #0] 800873c: 699b ldr r3, [r3, #24] 800873e: 009b lsls r3, r3, #2 8008740: 693a ldr r2, [r7, #16] 8008742: 4313 orrs r3, r2 8008744: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8008746: 687b ldr r3, [r7, #4] 8008748: 693a ldr r2, [r7, #16] 800874a: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 800874c: 687b ldr r3, [r7, #4] 800874e: 68fa ldr r2, [r7, #12] 8008750: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR2 = OC_Config->Pulse; 8008752: 683b ldr r3, [r7, #0] 8008754: 685a ldr r2, [r3, #4] 8008756: 687b ldr r3, [r7, #4] 8008758: 639a str r2, [r3, #56] @ 0x38 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 800875a: 687b ldr r3, [r7, #4] 800875c: 697a ldr r2, [r7, #20] 800875e: 621a str r2, [r3, #32] } 8008760: 46c0 nop @ (mov r8, r8) 8008762: 46bd mov sp, r7 8008764: b006 add sp, #24 8008766: bd80 pop {r7, pc} 8008768: feff8fff .word 0xfeff8fff 800876c: fffffcff .word 0xfffffcff 8008770: 40012c00 .word 0x40012c00 8008774: 40014400 .word 0x40014400 8008778: 40014800 .word 0x40014800 800877c: fffffbff .word 0xfffffbff 8008780: fffff7ff .word 0xfffff7ff 08008784 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8008784: b580 push {r7, lr} 8008786: b086 sub sp, #24 8008788: af00 add r7, sp, #0 800878a: 6078 str r0, [r7, #4] 800878c: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 800878e: 687b ldr r3, [r7, #4] 8008790: 6a1b ldr r3, [r3, #32] 8008792: 617b str r3, [r7, #20] /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; 8008794: 687b ldr r3, [r7, #4] 8008796: 6a1b ldr r3, [r3, #32] 8008798: 4a31 ldr r2, [pc, #196] @ (8008860 ) 800879a: 401a ands r2, r3 800879c: 687b ldr r3, [r7, #4] 800879e: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 80087a0: 687b ldr r3, [r7, #4] 80087a2: 685b ldr r3, [r3, #4] 80087a4: 613b str r3, [r7, #16] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 80087a6: 687b ldr r3, [r7, #4] 80087a8: 69db ldr r3, [r3, #28] 80087aa: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC3M; 80087ac: 68fb ldr r3, [r7, #12] 80087ae: 4a2d ldr r2, [pc, #180] @ (8008864 ) 80087b0: 4013 ands r3, r2 80087b2: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC3S; 80087b4: 68fb ldr r3, [r7, #12] 80087b6: 2203 movs r2, #3 80087b8: 4393 bics r3, r2 80087ba: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 80087bc: 683b ldr r3, [r7, #0] 80087be: 681b ldr r3, [r3, #0] 80087c0: 68fa ldr r2, [r7, #12] 80087c2: 4313 orrs r3, r2 80087c4: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; 80087c6: 697b ldr r3, [r7, #20] 80087c8: 4a27 ldr r2, [pc, #156] @ (8008868 ) 80087ca: 4013 ands r3, r2 80087cc: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 8U); 80087ce: 683b ldr r3, [r7, #0] 80087d0: 689b ldr r3, [r3, #8] 80087d2: 021b lsls r3, r3, #8 80087d4: 697a ldr r2, [r7, #20] 80087d6: 4313 orrs r3, r2 80087d8: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) 80087da: 687b ldr r3, [r7, #4] 80087dc: 4a23 ldr r2, [pc, #140] @ (800886c ) 80087de: 4293 cmp r3, r2 80087e0: d10d bne.n 80087fe { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; 80087e2: 697b ldr r3, [r7, #20] 80087e4: 4a22 ldr r2, [pc, #136] @ (8008870 ) 80087e6: 4013 ands r3, r2 80087e8: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); 80087ea: 683b ldr r3, [r7, #0] 80087ec: 68db ldr r3, [r3, #12] 80087ee: 021b lsls r3, r3, #8 80087f0: 697a ldr r2, [r7, #20] 80087f2: 4313 orrs r3, r2 80087f4: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC3NE; 80087f6: 697b ldr r3, [r7, #20] 80087f8: 4a1e ldr r2, [pc, #120] @ (8008874 ) 80087fa: 4013 ands r3, r2 80087fc: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 80087fe: 687b ldr r3, [r7, #4] 8008800: 4a1a ldr r2, [pc, #104] @ (800886c ) 8008802: 4293 cmp r3, r2 8008804: d007 beq.n 8008816 8008806: 687b ldr r3, [r7, #4] 8008808: 4a1b ldr r2, [pc, #108] @ (8008878 ) 800880a: 4293 cmp r3, r2 800880c: d003 beq.n 8008816 800880e: 687b ldr r3, [r7, #4] 8008810: 4a1a ldr r2, [pc, #104] @ (800887c ) 8008812: 4293 cmp r3, r2 8008814: d113 bne.n 800883e /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS3; 8008816: 693b ldr r3, [r7, #16] 8008818: 4a19 ldr r2, [pc, #100] @ (8008880 ) 800881a: 4013 ands r3, r2 800881c: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS3N; 800881e: 693b ldr r3, [r7, #16] 8008820: 4a18 ldr r2, [pc, #96] @ (8008884 ) 8008822: 4013 ands r3, r2 8008824: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 4U); 8008826: 683b ldr r3, [r7, #0] 8008828: 695b ldr r3, [r3, #20] 800882a: 011b lsls r3, r3, #4 800882c: 693a ldr r2, [r7, #16] 800882e: 4313 orrs r3, r2 8008830: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 4U); 8008832: 683b ldr r3, [r7, #0] 8008834: 699b ldr r3, [r3, #24] 8008836: 011b lsls r3, r3, #4 8008838: 693a ldr r2, [r7, #16] 800883a: 4313 orrs r3, r2 800883c: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 800883e: 687b ldr r3, [r7, #4] 8008840: 693a ldr r2, [r7, #16] 8008842: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 8008844: 687b ldr r3, [r7, #4] 8008846: 68fa ldr r2, [r7, #12] 8008848: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR3 = OC_Config->Pulse; 800884a: 683b ldr r3, [r7, #0] 800884c: 685a ldr r2, [r3, #4] 800884e: 687b ldr r3, [r7, #4] 8008850: 63da str r2, [r3, #60] @ 0x3c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8008852: 687b ldr r3, [r7, #4] 8008854: 697a ldr r2, [r7, #20] 8008856: 621a str r2, [r3, #32] } 8008858: 46c0 nop @ (mov r8, r8) 800885a: 46bd mov sp, r7 800885c: b006 add sp, #24 800885e: bd80 pop {r7, pc} 8008860: fffffeff .word 0xfffffeff 8008864: fffeff8f .word 0xfffeff8f 8008868: fffffdff .word 0xfffffdff 800886c: 40012c00 .word 0x40012c00 8008870: fffff7ff .word 0xfffff7ff 8008874: fffffbff .word 0xfffffbff 8008878: 40014400 .word 0x40014400 800887c: 40014800 .word 0x40014800 8008880: ffffefff .word 0xffffefff 8008884: ffffdfff .word 0xffffdfff 08008888 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8008888: b580 push {r7, lr} 800888a: b086 sub sp, #24 800888c: af00 add r7, sp, #0 800888e: 6078 str r0, [r7, #4] 8008890: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8008892: 687b ldr r3, [r7, #4] 8008894: 6a1b ldr r3, [r3, #32] 8008896: 613b str r3, [r7, #16] /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; 8008898: 687b ldr r3, [r7, #4] 800889a: 6a1b ldr r3, [r3, #32] 800889c: 4a24 ldr r2, [pc, #144] @ (8008930 ) 800889e: 401a ands r2, r3 80088a0: 687b ldr r3, [r7, #4] 80088a2: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 80088a4: 687b ldr r3, [r7, #4] 80088a6: 685b ldr r3, [r3, #4] 80088a8: 617b str r3, [r7, #20] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 80088aa: 687b ldr r3, [r7, #4] 80088ac: 69db ldr r3, [r3, #28] 80088ae: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC4M; 80088b0: 68fb ldr r3, [r7, #12] 80088b2: 4a20 ldr r2, [pc, #128] @ (8008934 ) 80088b4: 4013 ands r3, r2 80088b6: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC4S; 80088b8: 68fb ldr r3, [r7, #12] 80088ba: 4a1f ldr r2, [pc, #124] @ (8008938 ) 80088bc: 4013 ands r3, r2 80088be: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 80088c0: 683b ldr r3, [r7, #0] 80088c2: 681b ldr r3, [r3, #0] 80088c4: 021b lsls r3, r3, #8 80088c6: 68fa ldr r2, [r7, #12] 80088c8: 4313 orrs r3, r2 80088ca: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; 80088cc: 693b ldr r3, [r7, #16] 80088ce: 4a1b ldr r2, [pc, #108] @ (800893c ) 80088d0: 4013 ands r3, r2 80088d2: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 12U); 80088d4: 683b ldr r3, [r7, #0] 80088d6: 689b ldr r3, [r3, #8] 80088d8: 031b lsls r3, r3, #12 80088da: 693a ldr r2, [r7, #16] 80088dc: 4313 orrs r3, r2 80088de: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 80088e0: 687b ldr r3, [r7, #4] 80088e2: 4a17 ldr r2, [pc, #92] @ (8008940 ) 80088e4: 4293 cmp r3, r2 80088e6: d007 beq.n 80088f8 80088e8: 687b ldr r3, [r7, #4] 80088ea: 4a16 ldr r2, [pc, #88] @ (8008944 ) 80088ec: 4293 cmp r3, r2 80088ee: d003 beq.n 80088f8 80088f0: 687b ldr r3, [r7, #4] 80088f2: 4a15 ldr r2, [pc, #84] @ (8008948 ) 80088f4: 4293 cmp r3, r2 80088f6: d109 bne.n 800890c { /* Check parameters */ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS4; 80088f8: 697b ldr r3, [r7, #20] 80088fa: 4a14 ldr r2, [pc, #80] @ (800894c ) 80088fc: 4013 ands r3, r2 80088fe: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 6U); 8008900: 683b ldr r3, [r7, #0] 8008902: 695b ldr r3, [r3, #20] 8008904: 019b lsls r3, r3, #6 8008906: 697a ldr r2, [r7, #20] 8008908: 4313 orrs r3, r2 800890a: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 800890c: 687b ldr r3, [r7, #4] 800890e: 697a ldr r2, [r7, #20] 8008910: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 8008912: 687b ldr r3, [r7, #4] 8008914: 68fa ldr r2, [r7, #12] 8008916: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR4 = OC_Config->Pulse; 8008918: 683b ldr r3, [r7, #0] 800891a: 685a ldr r2, [r3, #4] 800891c: 687b ldr r3, [r7, #4] 800891e: 641a str r2, [r3, #64] @ 0x40 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8008920: 687b ldr r3, [r7, #4] 8008922: 693a ldr r2, [r7, #16] 8008924: 621a str r2, [r3, #32] } 8008926: 46c0 nop @ (mov r8, r8) 8008928: 46bd mov sp, r7 800892a: b006 add sp, #24 800892c: bd80 pop {r7, pc} 800892e: 46c0 nop @ (mov r8, r8) 8008930: ffffefff .word 0xffffefff 8008934: feff8fff .word 0xfeff8fff 8008938: fffffcff .word 0xfffffcff 800893c: ffffdfff .word 0xffffdfff 8008940: 40012c00 .word 0x40012c00 8008944: 40014400 .word 0x40014400 8008948: 40014800 .word 0x40014800 800894c: ffffbfff .word 0xffffbfff 08008950 : * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8008950: b580 push {r7, lr} 8008952: b086 sub sp, #24 8008954: af00 add r7, sp, #0 8008956: 6078 str r0, [r7, #4] 8008958: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 800895a: 687b ldr r3, [r7, #4] 800895c: 6a1b ldr r3, [r3, #32] 800895e: 613b str r3, [r7, #16] /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC5E; 8008960: 687b ldr r3, [r7, #4] 8008962: 6a1b ldr r3, [r3, #32] 8008964: 4a21 ldr r2, [pc, #132] @ (80089ec ) 8008966: 401a ands r2, r3 8008968: 687b ldr r3, [r7, #4] 800896a: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 800896c: 687b ldr r3, [r7, #4] 800896e: 685b ldr r3, [r3, #4] 8008970: 617b str r3, [r7, #20] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR3; 8008972: 687b ldr r3, [r7, #4] 8008974: 6d5b ldr r3, [r3, #84] @ 0x54 8008976: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~(TIM_CCMR3_OC5M); 8008978: 68fb ldr r3, [r7, #12] 800897a: 4a1d ldr r2, [pc, #116] @ (80089f0 ) 800897c: 4013 ands r3, r2 800897e: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 8008980: 683b ldr r3, [r7, #0] 8008982: 681b ldr r3, [r3, #0] 8008984: 68fa ldr r2, [r7, #12] 8008986: 4313 orrs r3, r2 8008988: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC5P; 800898a: 693b ldr r3, [r7, #16] 800898c: 4a19 ldr r2, [pc, #100] @ (80089f4 ) 800898e: 4013 ands r3, r2 8008990: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 16U); 8008992: 683b ldr r3, [r7, #0] 8008994: 689b ldr r3, [r3, #8] 8008996: 041b lsls r3, r3, #16 8008998: 693a ldr r2, [r7, #16] 800899a: 4313 orrs r3, r2 800899c: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 800899e: 687b ldr r3, [r7, #4] 80089a0: 4a15 ldr r2, [pc, #84] @ (80089f8 ) 80089a2: 4293 cmp r3, r2 80089a4: d007 beq.n 80089b6 80089a6: 687b ldr r3, [r7, #4] 80089a8: 4a14 ldr r2, [pc, #80] @ (80089fc ) 80089aa: 4293 cmp r3, r2 80089ac: d003 beq.n 80089b6 80089ae: 687b ldr r3, [r7, #4] 80089b0: 4a13 ldr r2, [pc, #76] @ (8008a00 ) 80089b2: 4293 cmp r3, r2 80089b4: d109 bne.n 80089ca { /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS5; 80089b6: 697b ldr r3, [r7, #20] 80089b8: 4a0c ldr r2, [pc, #48] @ (80089ec ) 80089ba: 4013 ands r3, r2 80089bc: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 8U); 80089be: 683b ldr r3, [r7, #0] 80089c0: 695b ldr r3, [r3, #20] 80089c2: 021b lsls r3, r3, #8 80089c4: 697a ldr r2, [r7, #20] 80089c6: 4313 orrs r3, r2 80089c8: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 80089ca: 687b ldr r3, [r7, #4] 80089cc: 697a ldr r2, [r7, #20] 80089ce: 605a str r2, [r3, #4] /* Write to TIMx CCMR3 */ TIMx->CCMR3 = tmpccmrx; 80089d0: 687b ldr r3, [r7, #4] 80089d2: 68fa ldr r2, [r7, #12] 80089d4: 655a str r2, [r3, #84] @ 0x54 /* Set the Capture Compare Register value */ TIMx->CCR5 = OC_Config->Pulse; 80089d6: 683b ldr r3, [r7, #0] 80089d8: 685a ldr r2, [r3, #4] 80089da: 687b ldr r3, [r7, #4] 80089dc: 659a str r2, [r3, #88] @ 0x58 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 80089de: 687b ldr r3, [r7, #4] 80089e0: 693a ldr r2, [r7, #16] 80089e2: 621a str r2, [r3, #32] } 80089e4: 46c0 nop @ (mov r8, r8) 80089e6: 46bd mov sp, r7 80089e8: b006 add sp, #24 80089ea: bd80 pop {r7, pc} 80089ec: fffeffff .word 0xfffeffff 80089f0: fffeff8f .word 0xfffeff8f 80089f4: fffdffff .word 0xfffdffff 80089f8: 40012c00 .word 0x40012c00 80089fc: 40014400 .word 0x40014400 8008a00: 40014800 .word 0x40014800 08008a04 : * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8008a04: b580 push {r7, lr} 8008a06: b086 sub sp, #24 8008a08: af00 add r7, sp, #0 8008a0a: 6078 str r0, [r7, #4] 8008a0c: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8008a0e: 687b ldr r3, [r7, #4] 8008a10: 6a1b ldr r3, [r3, #32] 8008a12: 613b str r3, [r7, #16] /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC6E; 8008a14: 687b ldr r3, [r7, #4] 8008a16: 6a1b ldr r3, [r3, #32] 8008a18: 4a22 ldr r2, [pc, #136] @ (8008aa4 ) 8008a1a: 401a ands r2, r3 8008a1c: 687b ldr r3, [r7, #4] 8008a1e: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8008a20: 687b ldr r3, [r7, #4] 8008a22: 685b ldr r3, [r3, #4] 8008a24: 617b str r3, [r7, #20] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR3; 8008a26: 687b ldr r3, [r7, #4] 8008a28: 6d5b ldr r3, [r3, #84] @ 0x54 8008a2a: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~(TIM_CCMR3_OC6M); 8008a2c: 68fb ldr r3, [r7, #12] 8008a2e: 4a1e ldr r2, [pc, #120] @ (8008aa8 ) 8008a30: 4013 ands r3, r2 8008a32: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8008a34: 683b ldr r3, [r7, #0] 8008a36: 681b ldr r3, [r3, #0] 8008a38: 021b lsls r3, r3, #8 8008a3a: 68fa ldr r2, [r7, #12] 8008a3c: 4313 orrs r3, r2 8008a3e: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= (uint32_t)~TIM_CCER_CC6P; 8008a40: 693b ldr r3, [r7, #16] 8008a42: 4a1a ldr r2, [pc, #104] @ (8008aac ) 8008a44: 4013 ands r3, r2 8008a46: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 20U); 8008a48: 683b ldr r3, [r7, #0] 8008a4a: 689b ldr r3, [r3, #8] 8008a4c: 051b lsls r3, r3, #20 8008a4e: 693a ldr r2, [r7, #16] 8008a50: 4313 orrs r3, r2 8008a52: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 8008a54: 687b ldr r3, [r7, #4] 8008a56: 4a16 ldr r2, [pc, #88] @ (8008ab0 ) 8008a58: 4293 cmp r3, r2 8008a5a: d007 beq.n 8008a6c 8008a5c: 687b ldr r3, [r7, #4] 8008a5e: 4a15 ldr r2, [pc, #84] @ (8008ab4 ) 8008a60: 4293 cmp r3, r2 8008a62: d003 beq.n 8008a6c 8008a64: 687b ldr r3, [r7, #4] 8008a66: 4a14 ldr r2, [pc, #80] @ (8008ab8 ) 8008a68: 4293 cmp r3, r2 8008a6a: d109 bne.n 8008a80 { /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS6; 8008a6c: 697b ldr r3, [r7, #20] 8008a6e: 4a13 ldr r2, [pc, #76] @ (8008abc ) 8008a70: 4013 ands r3, r2 8008a72: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 10U); 8008a74: 683b ldr r3, [r7, #0] 8008a76: 695b ldr r3, [r3, #20] 8008a78: 029b lsls r3, r3, #10 8008a7a: 697a ldr r2, [r7, #20] 8008a7c: 4313 orrs r3, r2 8008a7e: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8008a80: 687b ldr r3, [r7, #4] 8008a82: 697a ldr r2, [r7, #20] 8008a84: 605a str r2, [r3, #4] /* Write to TIMx CCMR3 */ TIMx->CCMR3 = tmpccmrx; 8008a86: 687b ldr r3, [r7, #4] 8008a88: 68fa ldr r2, [r7, #12] 8008a8a: 655a str r2, [r3, #84] @ 0x54 /* Set the Capture Compare Register value */ TIMx->CCR6 = OC_Config->Pulse; 8008a8c: 683b ldr r3, [r7, #0] 8008a8e: 685a ldr r2, [r3, #4] 8008a90: 687b ldr r3, [r7, #4] 8008a92: 65da str r2, [r3, #92] @ 0x5c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8008a94: 687b ldr r3, [r7, #4] 8008a96: 693a ldr r2, [r7, #16] 8008a98: 621a str r2, [r3, #32] } 8008a9a: 46c0 nop @ (mov r8, r8) 8008a9c: 46bd mov sp, r7 8008a9e: b006 add sp, #24 8008aa0: bd80 pop {r7, pc} 8008aa2: 46c0 nop @ (mov r8, r8) 8008aa4: ffefffff .word 0xffefffff 8008aa8: feff8fff .word 0xfeff8fff 8008aac: ffdfffff .word 0xffdfffff 8008ab0: 40012c00 .word 0x40012c00 8008ab4: 40014400 .word 0x40014400 8008ab8: 40014800 .word 0x40014800 8008abc: fffbffff .word 0xfffbffff 08008ac0 : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 8008ac0: b580 push {r7, lr} 8008ac2: b086 sub sp, #24 8008ac4: af00 add r7, sp, #0 8008ac6: 60f8 str r0, [r7, #12] 8008ac8: 60b9 str r1, [r7, #8] 8008aca: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; 8008acc: 68fb ldr r3, [r7, #12] 8008ace: 6a1b ldr r3, [r3, #32] 8008ad0: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC1E; 8008ad2: 68fb ldr r3, [r7, #12] 8008ad4: 6a1b ldr r3, [r3, #32] 8008ad6: 2201 movs r2, #1 8008ad8: 4393 bics r3, r2 8008ada: 001a movs r2, r3 8008adc: 68fb ldr r3, [r7, #12] 8008ade: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8008ae0: 68fb ldr r3, [r7, #12] 8008ae2: 699b ldr r3, [r3, #24] 8008ae4: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; 8008ae6: 693b ldr r3, [r7, #16] 8008ae8: 22f0 movs r2, #240 @ 0xf0 8008aea: 4393 bics r3, r2 8008aec: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 4U); 8008aee: 687b ldr r3, [r7, #4] 8008af0: 011b lsls r3, r3, #4 8008af2: 693a ldr r2, [r7, #16] 8008af4: 4313 orrs r3, r2 8008af6: 613b str r3, [r7, #16] /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 8008af8: 697b ldr r3, [r7, #20] 8008afa: 220a movs r2, #10 8008afc: 4393 bics r3, r2 8008afe: 617b str r3, [r7, #20] tmpccer |= TIM_ICPolarity; 8008b00: 697a ldr r2, [r7, #20] 8008b02: 68bb ldr r3, [r7, #8] 8008b04: 4313 orrs r3, r2 8008b06: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; 8008b08: 68fb ldr r3, [r7, #12] 8008b0a: 693a ldr r2, [r7, #16] 8008b0c: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8008b0e: 68fb ldr r3, [r7, #12] 8008b10: 697a ldr r2, [r7, #20] 8008b12: 621a str r2, [r3, #32] } 8008b14: 46c0 nop @ (mov r8, r8) 8008b16: 46bd mov sp, r7 8008b18: b006 add sp, #24 8008b1a: bd80 pop {r7, pc} 08008b1c : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 8008b1c: b580 push {r7, lr} 8008b1e: b086 sub sp, #24 8008b20: af00 add r7, sp, #0 8008b22: 60f8 str r0, [r7, #12] 8008b24: 60b9 str r1, [r7, #8] 8008b26: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ tmpccer = TIMx->CCER; 8008b28: 68fb ldr r3, [r7, #12] 8008b2a: 6a1b ldr r3, [r3, #32] 8008b2c: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC2E; 8008b2e: 68fb ldr r3, [r7, #12] 8008b30: 6a1b ldr r3, [r3, #32] 8008b32: 2210 movs r2, #16 8008b34: 4393 bics r3, r2 8008b36: 001a movs r2, r3 8008b38: 68fb ldr r3, [r7, #12] 8008b3a: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8008b3c: 68fb ldr r3, [r7, #12] 8008b3e: 699b ldr r3, [r3, #24] 8008b40: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; 8008b42: 693b ldr r3, [r7, #16] 8008b44: 4a0d ldr r2, [pc, #52] @ (8008b7c ) 8008b46: 4013 ands r3, r2 8008b48: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 12U); 8008b4a: 687b ldr r3, [r7, #4] 8008b4c: 031b lsls r3, r3, #12 8008b4e: 693a ldr r2, [r7, #16] 8008b50: 4313 orrs r3, r2 8008b52: 613b str r3, [r7, #16] /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); 8008b54: 697b ldr r3, [r7, #20] 8008b56: 22a0 movs r2, #160 @ 0xa0 8008b58: 4393 bics r3, r2 8008b5a: 617b str r3, [r7, #20] tmpccer |= (TIM_ICPolarity << 4U); 8008b5c: 68bb ldr r3, [r7, #8] 8008b5e: 011b lsls r3, r3, #4 8008b60: 697a ldr r2, [r7, #20] 8008b62: 4313 orrs r3, r2 8008b64: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; 8008b66: 68fb ldr r3, [r7, #12] 8008b68: 693a ldr r2, [r7, #16] 8008b6a: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8008b6c: 68fb ldr r3, [r7, #12] 8008b6e: 697a ldr r2, [r7, #20] 8008b70: 621a str r2, [r3, #32] } 8008b72: 46c0 nop @ (mov r8, r8) 8008b74: 46bd mov sp, r7 8008b76: b006 add sp, #24 8008b78: bd80 pop {r7, pc} 8008b7a: 46c0 nop @ (mov r8, r8) 8008b7c: ffff0fff .word 0xffff0fff 08008b80 : * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 * @arg TIM_TS_ETRF: External Trigger input * @retval None */ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) { 8008b80: b580 push {r7, lr} 8008b82: b084 sub sp, #16 8008b84: af00 add r7, sp, #0 8008b86: 6078 str r0, [r7, #4] 8008b88: 6039 str r1, [r7, #0] uint32_t tmpsmcr; /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; 8008b8a: 687b ldr r3, [r7, #4] 8008b8c: 689b ldr r3, [r3, #8] 8008b8e: 60fb str r3, [r7, #12] /* Reset the TS Bits */ tmpsmcr &= ~TIM_SMCR_TS; 8008b90: 68fb ldr r3, [r7, #12] 8008b92: 4a08 ldr r2, [pc, #32] @ (8008bb4 ) 8008b94: 4013 ands r3, r2 8008b96: 60fb str r3, [r7, #12] /* Set the Input Trigger source and the slave mode*/ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); 8008b98: 683a ldr r2, [r7, #0] 8008b9a: 68fb ldr r3, [r7, #12] 8008b9c: 4313 orrs r3, r2 8008b9e: 2207 movs r2, #7 8008ba0: 4313 orrs r3, r2 8008ba2: 60fb str r3, [r7, #12] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 8008ba4: 687b ldr r3, [r7, #4] 8008ba6: 68fa ldr r2, [r7, #12] 8008ba8: 609a str r2, [r3, #8] } 8008baa: 46c0 nop @ (mov r8, r8) 8008bac: 46bd mov sp, r7 8008bae: b004 add sp, #16 8008bb0: bd80 pop {r7, pc} 8008bb2: 46c0 nop @ (mov r8, r8) 8008bb4: ffcfff8f .word 0xffcfff8f 08008bb8 : * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) { 8008bb8: b580 push {r7, lr} 8008bba: b086 sub sp, #24 8008bbc: af00 add r7, sp, #0 8008bbe: 60f8 str r0, [r7, #12] 8008bc0: 60b9 str r1, [r7, #8] 8008bc2: 607a str r2, [r7, #4] 8008bc4: 603b str r3, [r7, #0] uint32_t tmpsmcr; tmpsmcr = TIMx->SMCR; 8008bc6: 68fb ldr r3, [r7, #12] 8008bc8: 689b ldr r3, [r3, #8] 8008bca: 617b str r3, [r7, #20] /* Reset the ETR Bits */ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 8008bcc: 697b ldr r3, [r7, #20] 8008bce: 4a09 ldr r2, [pc, #36] @ (8008bf4 ) 8008bd0: 4013 ands r3, r2 8008bd2: 617b str r3, [r7, #20] /* Set the Prescaler, the Filter value and the Polarity */ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 8008bd4: 683b ldr r3, [r7, #0] 8008bd6: 021a lsls r2, r3, #8 8008bd8: 687b ldr r3, [r7, #4] 8008bda: 431a orrs r2, r3 8008bdc: 68bb ldr r3, [r7, #8] 8008bde: 4313 orrs r3, r2 8008be0: 697a ldr r2, [r7, #20] 8008be2: 4313 orrs r3, r2 8008be4: 617b str r3, [r7, #20] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 8008be6: 68fb ldr r3, [r7, #12] 8008be8: 697a ldr r2, [r7, #20] 8008bea: 609a str r2, [r3, #8] } 8008bec: 46c0 nop @ (mov r8, r8) 8008bee: 46bd mov sp, r7 8008bf0: b006 add sp, #24 8008bf2: bd80 pop {r7, pc} 8008bf4: ffff00ff .word 0xffff00ff 08008bf8 : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig) { 8008bf8: b580 push {r7, lr} 8008bfa: b084 sub sp, #16 8008bfc: af00 add r7, sp, #0 8008bfe: 6078 str r0, [r7, #4] 8008c00: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 8008c02: 687b ldr r3, [r7, #4] 8008c04: 223c movs r2, #60 @ 0x3c 8008c06: 5c9b ldrb r3, [r3, r2] 8008c08: 2b01 cmp r3, #1 8008c0a: d101 bne.n 8008c10 8008c0c: 2302 movs r3, #2 8008c0e: e050 b.n 8008cb2 8008c10: 687b ldr r3, [r7, #4] 8008c12: 223c movs r2, #60 @ 0x3c 8008c14: 2101 movs r1, #1 8008c16: 5499 strb r1, [r3, r2] /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 8008c18: 687b ldr r3, [r7, #4] 8008c1a: 223d movs r2, #61 @ 0x3d 8008c1c: 2102 movs r1, #2 8008c1e: 5499 strb r1, [r3, r2] /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 8008c20: 687b ldr r3, [r7, #4] 8008c22: 681b ldr r3, [r3, #0] 8008c24: 685b ldr r3, [r3, #4] 8008c26: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 8008c28: 687b ldr r3, [r7, #4] 8008c2a: 681b ldr r3, [r3, #0] 8008c2c: 689b ldr r3, [r3, #8] 8008c2e: 60bb str r3, [r7, #8] /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) 8008c30: 687b ldr r3, [r7, #4] 8008c32: 681b ldr r3, [r3, #0] 8008c34: 4a21 ldr r2, [pc, #132] @ (8008cbc ) 8008c36: 4293 cmp r3, r2 8008c38: d108 bne.n 8008c4c { /* Check the parameters */ assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); /* Clear the MMS2 bits */ tmpcr2 &= ~TIM_CR2_MMS2; 8008c3a: 68fb ldr r3, [r7, #12] 8008c3c: 4a20 ldr r2, [pc, #128] @ (8008cc0 ) 8008c3e: 4013 ands r3, r2 8008c40: 60fb str r3, [r7, #12] /* Select the TRGO2 source*/ tmpcr2 |= sMasterConfig->MasterOutputTrigger2; 8008c42: 683b ldr r3, [r7, #0] 8008c44: 685b ldr r3, [r3, #4] 8008c46: 68fa ldr r2, [r7, #12] 8008c48: 4313 orrs r3, r2 8008c4a: 60fb str r3, [r7, #12] } /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 8008c4c: 68fb ldr r3, [r7, #12] 8008c4e: 2270 movs r2, #112 @ 0x70 8008c50: 4393 bics r3, r2 8008c52: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 8008c54: 683b ldr r3, [r7, #0] 8008c56: 681b ldr r3, [r3, #0] 8008c58: 68fa ldr r2, [r7, #12] 8008c5a: 4313 orrs r3, r2 8008c5c: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 8008c5e: 687b ldr r3, [r7, #4] 8008c60: 681b ldr r3, [r3, #0] 8008c62: 68fa ldr r2, [r7, #12] 8008c64: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8008c66: 687b ldr r3, [r7, #4] 8008c68: 681b ldr r3, [r3, #0] 8008c6a: 4a14 ldr r2, [pc, #80] @ (8008cbc ) 8008c6c: 4293 cmp r3, r2 8008c6e: d00a beq.n 8008c86 8008c70: 687b ldr r3, [r7, #4] 8008c72: 681a ldr r2, [r3, #0] 8008c74: 2380 movs r3, #128 @ 0x80 8008c76: 05db lsls r3, r3, #23 8008c78: 429a cmp r2, r3 8008c7a: d004 beq.n 8008c86 8008c7c: 687b ldr r3, [r7, #4] 8008c7e: 681b ldr r3, [r3, #0] 8008c80: 4a10 ldr r2, [pc, #64] @ (8008cc4 ) 8008c82: 4293 cmp r3, r2 8008c84: d10c bne.n 8008ca0 { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 8008c86: 68bb ldr r3, [r7, #8] 8008c88: 2280 movs r2, #128 @ 0x80 8008c8a: 4393 bics r3, r2 8008c8c: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 8008c8e: 683b ldr r3, [r7, #0] 8008c90: 689b ldr r3, [r3, #8] 8008c92: 68ba ldr r2, [r7, #8] 8008c94: 4313 orrs r3, r2 8008c96: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 8008c98: 687b ldr r3, [r7, #4] 8008c9a: 681b ldr r3, [r3, #0] 8008c9c: 68ba ldr r2, [r7, #8] 8008c9e: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 8008ca0: 687b ldr r3, [r7, #4] 8008ca2: 223d movs r2, #61 @ 0x3d 8008ca4: 2101 movs r1, #1 8008ca6: 5499 strb r1, [r3, r2] __HAL_UNLOCK(htim); 8008ca8: 687b ldr r3, [r7, #4] 8008caa: 223c movs r2, #60 @ 0x3c 8008cac: 2100 movs r1, #0 8008cae: 5499 strb r1, [r3, r2] return HAL_OK; 8008cb0: 2300 movs r3, #0 } 8008cb2: 0018 movs r0, r3 8008cb4: 46bd mov sp, r7 8008cb6: b004 add sp, #16 8008cb8: bd80 pop {r7, pc} 8008cba: 46c0 nop @ (mov r8, r8) 8008cbc: 40012c00 .word 0x40012c00 8008cc0: ff0fffff .word 0xff0fffff 8008cc4: 40000400 .word 0x40000400 08008cc8 : * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) { 8008cc8: b580 push {r7, lr} 8008cca: b084 sub sp, #16 8008ccc: af00 add r7, sp, #0 8008cce: 6078 str r0, [r7, #4] 8008cd0: 6039 str r1, [r7, #0] /* Keep this variable initialized to 0 as it is used to configure BDTR register */ uint32_t tmpbdtr = 0U; 8008cd2: 2300 movs r3, #0 8008cd4: 60fb str r3, [r7, #12] assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter)); assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode)); /* Check input state */ __HAL_LOCK(htim); 8008cd6: 687b ldr r3, [r7, #4] 8008cd8: 223c movs r2, #60 @ 0x3c 8008cda: 5c9b ldrb r3, [r3, r2] 8008cdc: 2b01 cmp r3, #1 8008cde: d101 bne.n 8008ce4 8008ce0: 2302 movs r3, #2 8008ce2: e06f b.n 8008dc4 8008ce4: 687b ldr r3, [r7, #4] 8008ce6: 223c movs r2, #60 @ 0x3c 8008ce8: 2101 movs r1, #1 8008cea: 5499 strb r1, [r3, r2] /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, the OSSI State, the dead time value and the Automatic Output Enable Bit */ /* Set the BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); 8008cec: 68fb ldr r3, [r7, #12] 8008cee: 22ff movs r2, #255 @ 0xff 8008cf0: 4393 bics r3, r2 8008cf2: 001a movs r2, r3 8008cf4: 683b ldr r3, [r7, #0] 8008cf6: 68db ldr r3, [r3, #12] 8008cf8: 4313 orrs r3, r2 8008cfa: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); 8008cfc: 68fb ldr r3, [r7, #12] 8008cfe: 4a33 ldr r2, [pc, #204] @ (8008dcc ) 8008d00: 401a ands r2, r3 8008d02: 683b ldr r3, [r7, #0] 8008d04: 689b ldr r3, [r3, #8] 8008d06: 4313 orrs r3, r2 8008d08: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); 8008d0a: 68fb ldr r3, [r7, #12] 8008d0c: 4a30 ldr r2, [pc, #192] @ (8008dd0 ) 8008d0e: 401a ands r2, r3 8008d10: 683b ldr r3, [r7, #0] 8008d12: 685b ldr r3, [r3, #4] 8008d14: 4313 orrs r3, r2 8008d16: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); 8008d18: 68fb ldr r3, [r7, #12] 8008d1a: 4a2e ldr r2, [pc, #184] @ (8008dd4 ) 8008d1c: 401a ands r2, r3 8008d1e: 683b ldr r3, [r7, #0] 8008d20: 681b ldr r3, [r3, #0] 8008d22: 4313 orrs r3, r2 8008d24: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); 8008d26: 68fb ldr r3, [r7, #12] 8008d28: 4a2b ldr r2, [pc, #172] @ (8008dd8 ) 8008d2a: 401a ands r2, r3 8008d2c: 683b ldr r3, [r7, #0] 8008d2e: 691b ldr r3, [r3, #16] 8008d30: 4313 orrs r3, r2 8008d32: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); 8008d34: 68fb ldr r3, [r7, #12] 8008d36: 4a29 ldr r2, [pc, #164] @ (8008ddc ) 8008d38: 401a ands r2, r3 8008d3a: 683b ldr r3, [r7, #0] 8008d3c: 695b ldr r3, [r3, #20] 8008d3e: 4313 orrs r3, r2 8008d40: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); 8008d42: 68fb ldr r3, [r7, #12] 8008d44: 4a26 ldr r2, [pc, #152] @ (8008de0 ) 8008d46: 401a ands r2, r3 8008d48: 683b ldr r3, [r7, #0] 8008d4a: 6b1b ldr r3, [r3, #48] @ 0x30 8008d4c: 4313 orrs r3, r2 8008d4e: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); 8008d50: 68fb ldr r3, [r7, #12] 8008d52: 4a24 ldr r2, [pc, #144] @ (8008de4 ) 8008d54: 401a ands r2, r3 8008d56: 683b ldr r3, [r7, #0] 8008d58: 699b ldr r3, [r3, #24] 8008d5a: 041b lsls r3, r3, #16 8008d5c: 4313 orrs r3, r2 8008d5e: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); 8008d60: 68fb ldr r3, [r7, #12] 8008d62: 4a21 ldr r2, [pc, #132] @ (8008de8 ) 8008d64: 401a ands r2, r3 8008d66: 683b ldr r3, [r7, #0] 8008d68: 69db ldr r3, [r3, #28] 8008d6a: 4313 orrs r3, r2 8008d6c: 60fb str r3, [r7, #12] if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) 8008d6e: 687b ldr r3, [r7, #4] 8008d70: 681b ldr r3, [r3, #0] 8008d72: 4a1e ldr r2, [pc, #120] @ (8008dec ) 8008d74: 4293 cmp r3, r2 8008d76: d11c bne.n 8008db2 assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity)); assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter)); assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode)); /* Set the BREAK2 input related BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos)); 8008d78: 68fb ldr r3, [r7, #12] 8008d7a: 4a1d ldr r2, [pc, #116] @ (8008df0 ) 8008d7c: 401a ands r2, r3 8008d7e: 683b ldr r3, [r7, #0] 8008d80: 6a9b ldr r3, [r3, #40] @ 0x28 8008d82: 051b lsls r3, r3, #20 8008d84: 4313 orrs r3, r2 8008d86: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); 8008d88: 68fb ldr r3, [r7, #12] 8008d8a: 4a1a ldr r2, [pc, #104] @ (8008df4 ) 8008d8c: 401a ands r2, r3 8008d8e: 683b ldr r3, [r7, #0] 8008d90: 6a1b ldr r3, [r3, #32] 8008d92: 4313 orrs r3, r2 8008d94: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); 8008d96: 68fb ldr r3, [r7, #12] 8008d98: 4a17 ldr r2, [pc, #92] @ (8008df8 ) 8008d9a: 401a ands r2, r3 8008d9c: 683b ldr r3, [r7, #0] 8008d9e: 6a5b ldr r3, [r3, #36] @ 0x24 8008da0: 4313 orrs r3, r2 8008da2: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode); 8008da4: 68fb ldr r3, [r7, #12] 8008da6: 4a15 ldr r2, [pc, #84] @ (8008dfc ) 8008da8: 401a ands r2, r3 8008daa: 683b ldr r3, [r7, #0] 8008dac: 6adb ldr r3, [r3, #44] @ 0x2c 8008dae: 4313 orrs r3, r2 8008db0: 60fb str r3, [r7, #12] } /* Set TIMx_BDTR */ htim->Instance->BDTR = tmpbdtr; 8008db2: 687b ldr r3, [r7, #4] 8008db4: 681b ldr r3, [r3, #0] 8008db6: 68fa ldr r2, [r7, #12] 8008db8: 645a str r2, [r3, #68] @ 0x44 __HAL_UNLOCK(htim); 8008dba: 687b ldr r3, [r7, #4] 8008dbc: 223c movs r2, #60 @ 0x3c 8008dbe: 2100 movs r1, #0 8008dc0: 5499 strb r1, [r3, r2] return HAL_OK; 8008dc2: 2300 movs r3, #0 } 8008dc4: 0018 movs r0, r3 8008dc6: 46bd mov sp, r7 8008dc8: b004 add sp, #16 8008dca: bd80 pop {r7, pc} 8008dcc: fffffcff .word 0xfffffcff 8008dd0: fffffbff .word 0xfffffbff 8008dd4: fffff7ff .word 0xfffff7ff 8008dd8: ffffefff .word 0xffffefff 8008ddc: ffffdfff .word 0xffffdfff 8008de0: ffffbfff .word 0xffffbfff 8008de4: fff0ffff .word 0xfff0ffff 8008de8: efffffff .word 0xefffffff 8008dec: 40012c00 .word 0x40012c00 8008df0: ff0fffff .word 0xff0fffff 8008df4: feffffff .word 0xfeffffff 8008df8: fdffffff .word 0xfdffffff 8008dfc: dfffffff .word 0xdfffffff 08008e00 : 8008e00: b510 push {r4, lr} 8008e02: 4b03 ldr r3, [pc, #12] @ (8008e10 ) 8008e04: 000a movs r2, r1 8008e06: 0001 movs r1, r0 8008e08: 6818 ldr r0, [r3, #0] 8008e0a: f000 f803 bl 8008e14 <_calloc_r> 8008e0e: bd10 pop {r4, pc} 8008e10: 2000000c .word 0x2000000c 08008e14 <_calloc_r>: 8008e14: b570 push {r4, r5, r6, lr} 8008e16: 0c0b lsrs r3, r1, #16 8008e18: 0c15 lsrs r5, r2, #16 8008e1a: 2b00 cmp r3, #0 8008e1c: d11e bne.n 8008e5c <_calloc_r+0x48> 8008e1e: 2d00 cmp r5, #0 8008e20: d10c bne.n 8008e3c <_calloc_r+0x28> 8008e22: b289 uxth r1, r1 8008e24: b294 uxth r4, r2 8008e26: 434c muls r4, r1 8008e28: 0021 movs r1, r4 8008e2a: f000 f843 bl 8008eb4 <_malloc_r> 8008e2e: 1e05 subs r5, r0, #0 8008e30: d01a beq.n 8008e68 <_calloc_r+0x54> 8008e32: 0022 movs r2, r4 8008e34: 2100 movs r1, #0 8008e36: f000 f8cd bl 8008fd4 8008e3a: e016 b.n 8008e6a <_calloc_r+0x56> 8008e3c: 1c2b adds r3, r5, #0 8008e3e: 1c0c adds r4, r1, #0 8008e40: b289 uxth r1, r1 8008e42: b292 uxth r2, r2 8008e44: 434a muls r2, r1 8008e46: b29b uxth r3, r3 8008e48: b2a1 uxth r1, r4 8008e4a: 4359 muls r1, r3 8008e4c: 0c14 lsrs r4, r2, #16 8008e4e: 190c adds r4, r1, r4 8008e50: 0c23 lsrs r3, r4, #16 8008e52: d107 bne.n 8008e64 <_calloc_r+0x50> 8008e54: 0424 lsls r4, r4, #16 8008e56: b292 uxth r2, r2 8008e58: 4314 orrs r4, r2 8008e5a: e7e5 b.n 8008e28 <_calloc_r+0x14> 8008e5c: 2d00 cmp r5, #0 8008e5e: d101 bne.n 8008e64 <_calloc_r+0x50> 8008e60: 1c14 adds r4, r2, #0 8008e62: e7ed b.n 8008e40 <_calloc_r+0x2c> 8008e64: 230c movs r3, #12 8008e66: 6003 str r3, [r0, #0] 8008e68: 2500 movs r5, #0 8008e6a: 0028 movs r0, r5 8008e6c: bd70 pop {r4, r5, r6, pc} ... 08008e70 : 8008e70: b570 push {r4, r5, r6, lr} 8008e72: 4e0f ldr r6, [pc, #60] @ (8008eb0 ) 8008e74: 000d movs r5, r1 8008e76: 6831 ldr r1, [r6, #0] 8008e78: 0004 movs r4, r0 8008e7a: 2900 cmp r1, #0 8008e7c: d102 bne.n 8008e84 8008e7e: f000 f8b1 bl 8008fe4 <_sbrk_r> 8008e82: 6030 str r0, [r6, #0] 8008e84: 0029 movs r1, r5 8008e86: 0020 movs r0, r4 8008e88: f000 f8ac bl 8008fe4 <_sbrk_r> 8008e8c: 1c43 adds r3, r0, #1 8008e8e: d103 bne.n 8008e98 8008e90: 2501 movs r5, #1 8008e92: 426d negs r5, r5 8008e94: 0028 movs r0, r5 8008e96: bd70 pop {r4, r5, r6, pc} 8008e98: 2303 movs r3, #3 8008e9a: 1cc5 adds r5, r0, #3 8008e9c: 439d bics r5, r3 8008e9e: 42a8 cmp r0, r5 8008ea0: d0f8 beq.n 8008e94 8008ea2: 1a29 subs r1, r5, r0 8008ea4: 0020 movs r0, r4 8008ea6: f000 f89d bl 8008fe4 <_sbrk_r> 8008eaa: 3001 adds r0, #1 8008eac: d1f2 bne.n 8008e94 8008eae: e7ef b.n 8008e90 8008eb0: 200009f4 .word 0x200009f4 08008eb4 <_malloc_r>: 8008eb4: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} 8008eb6: 2203 movs r2, #3 8008eb8: 1ccb adds r3, r1, #3 8008eba: 4393 bics r3, r2 8008ebc: 3308 adds r3, #8 8008ebe: 0005 movs r5, r0 8008ec0: 001f movs r7, r3 8008ec2: 2b0c cmp r3, #12 8008ec4: d234 bcs.n 8008f30 <_malloc_r+0x7c> 8008ec6: 270c movs r7, #12 8008ec8: 42b9 cmp r1, r7 8008eca: d833 bhi.n 8008f34 <_malloc_r+0x80> 8008ecc: 0028 movs r0, r5 8008ece: f000 f871 bl 8008fb4 <__malloc_lock> 8008ed2: 4e37 ldr r6, [pc, #220] @ (8008fb0 <_malloc_r+0xfc>) 8008ed4: 6833 ldr r3, [r6, #0] 8008ed6: 001c movs r4, r3 8008ed8: 2c00 cmp r4, #0 8008eda: d12f bne.n 8008f3c <_malloc_r+0x88> 8008edc: 0039 movs r1, r7 8008ede: 0028 movs r0, r5 8008ee0: f7ff ffc6 bl 8008e70 8008ee4: 0004 movs r4, r0 8008ee6: 1c43 adds r3, r0, #1 8008ee8: d15f bne.n 8008faa <_malloc_r+0xf6> 8008eea: 6834 ldr r4, [r6, #0] 8008eec: 9400 str r4, [sp, #0] 8008eee: 9b00 ldr r3, [sp, #0] 8008ef0: 2b00 cmp r3, #0 8008ef2: d14a bne.n 8008f8a <_malloc_r+0xd6> 8008ef4: 2c00 cmp r4, #0 8008ef6: d052 beq.n 8008f9e <_malloc_r+0xea> 8008ef8: 6823 ldr r3, [r4, #0] 8008efa: 0028 movs r0, r5 8008efc: 18e3 adds r3, r4, r3 8008efe: 9900 ldr r1, [sp, #0] 8008f00: 9301 str r3, [sp, #4] 8008f02: f000 f86f bl 8008fe4 <_sbrk_r> 8008f06: 9b01 ldr r3, [sp, #4] 8008f08: 4283 cmp r3, r0 8008f0a: d148 bne.n 8008f9e <_malloc_r+0xea> 8008f0c: 6823 ldr r3, [r4, #0] 8008f0e: 0028 movs r0, r5 8008f10: 1aff subs r7, r7, r3 8008f12: 0039 movs r1, r7 8008f14: f7ff ffac bl 8008e70 8008f18: 3001 adds r0, #1 8008f1a: d040 beq.n 8008f9e <_malloc_r+0xea> 8008f1c: 6823 ldr r3, [r4, #0] 8008f1e: 19db adds r3, r3, r7 8008f20: 6023 str r3, [r4, #0] 8008f22: 6833 ldr r3, [r6, #0] 8008f24: 685a ldr r2, [r3, #4] 8008f26: 2a00 cmp r2, #0 8008f28: d133 bne.n 8008f92 <_malloc_r+0xde> 8008f2a: 9b00 ldr r3, [sp, #0] 8008f2c: 6033 str r3, [r6, #0] 8008f2e: e019 b.n 8008f64 <_malloc_r+0xb0> 8008f30: 2b00 cmp r3, #0 8008f32: dac9 bge.n 8008ec8 <_malloc_r+0x14> 8008f34: 230c movs r3, #12 8008f36: 602b str r3, [r5, #0] 8008f38: 2000 movs r0, #0 8008f3a: bdfe pop {r1, r2, r3, r4, r5, r6, r7, pc} 8008f3c: 6821 ldr r1, [r4, #0] 8008f3e: 1bc9 subs r1, r1, r7 8008f40: d420 bmi.n 8008f84 <_malloc_r+0xd0> 8008f42: 290b cmp r1, #11 8008f44: d90a bls.n 8008f5c <_malloc_r+0xa8> 8008f46: 19e2 adds r2, r4, r7 8008f48: 6027 str r7, [r4, #0] 8008f4a: 42a3 cmp r3, r4 8008f4c: d104 bne.n 8008f58 <_malloc_r+0xa4> 8008f4e: 6032 str r2, [r6, #0] 8008f50: 6863 ldr r3, [r4, #4] 8008f52: 6011 str r1, [r2, #0] 8008f54: 6053 str r3, [r2, #4] 8008f56: e005 b.n 8008f64 <_malloc_r+0xb0> 8008f58: 605a str r2, [r3, #4] 8008f5a: e7f9 b.n 8008f50 <_malloc_r+0x9c> 8008f5c: 6862 ldr r2, [r4, #4] 8008f5e: 42a3 cmp r3, r4 8008f60: d10e bne.n 8008f80 <_malloc_r+0xcc> 8008f62: 6032 str r2, [r6, #0] 8008f64: 0028 movs r0, r5 8008f66: f000 f82d bl 8008fc4 <__malloc_unlock> 8008f6a: 0020 movs r0, r4 8008f6c: 2207 movs r2, #7 8008f6e: 300b adds r0, #11 8008f70: 1d23 adds r3, r4, #4 8008f72: 4390 bics r0, r2 8008f74: 1ac2 subs r2, r0, r3 8008f76: 4298 cmp r0, r3 8008f78: d0df beq.n 8008f3a <_malloc_r+0x86> 8008f7a: 1a1b subs r3, r3, r0 8008f7c: 50a3 str r3, [r4, r2] 8008f7e: e7dc b.n 8008f3a <_malloc_r+0x86> 8008f80: 605a str r2, [r3, #4] 8008f82: e7ef b.n 8008f64 <_malloc_r+0xb0> 8008f84: 0023 movs r3, r4 8008f86: 6864 ldr r4, [r4, #4] 8008f88: e7a6 b.n 8008ed8 <_malloc_r+0x24> 8008f8a: 9c00 ldr r4, [sp, #0] 8008f8c: 6863 ldr r3, [r4, #4] 8008f8e: 9300 str r3, [sp, #0] 8008f90: e7ad b.n 8008eee <_malloc_r+0x3a> 8008f92: 001a movs r2, r3 8008f94: 685b ldr r3, [r3, #4] 8008f96: 42a3 cmp r3, r4 8008f98: d1fb bne.n 8008f92 <_malloc_r+0xde> 8008f9a: 2300 movs r3, #0 8008f9c: e7da b.n 8008f54 <_malloc_r+0xa0> 8008f9e: 230c movs r3, #12 8008fa0: 0028 movs r0, r5 8008fa2: 602b str r3, [r5, #0] 8008fa4: f000 f80e bl 8008fc4 <__malloc_unlock> 8008fa8: e7c6 b.n 8008f38 <_malloc_r+0x84> 8008faa: 6007 str r7, [r0, #0] 8008fac: e7da b.n 8008f64 <_malloc_r+0xb0> 8008fae: 46c0 nop @ (mov r8, r8) 8008fb0: 200009f8 .word 0x200009f8 08008fb4 <__malloc_lock>: 8008fb4: b510 push {r4, lr} 8008fb6: 4802 ldr r0, [pc, #8] @ (8008fc0 <__malloc_lock+0xc>) 8008fb8: f000 f850 bl 800905c <__retarget_lock_acquire_recursive> 8008fbc: bd10 pop {r4, pc} 8008fbe: 46c0 nop @ (mov r8, r8) 8008fc0: 20000b38 .word 0x20000b38 08008fc4 <__malloc_unlock>: 8008fc4: b510 push {r4, lr} 8008fc6: 4802 ldr r0, [pc, #8] @ (8008fd0 <__malloc_unlock+0xc>) 8008fc8: f000 f849 bl 800905e <__retarget_lock_release_recursive> 8008fcc: bd10 pop {r4, pc} 8008fce: 46c0 nop @ (mov r8, r8) 8008fd0: 20000b38 .word 0x20000b38 08008fd4 : 8008fd4: 0003 movs r3, r0 8008fd6: 1882 adds r2, r0, r2 8008fd8: 4293 cmp r3, r2 8008fda: d100 bne.n 8008fde 8008fdc: 4770 bx lr 8008fde: 7019 strb r1, [r3, #0] 8008fe0: 3301 adds r3, #1 8008fe2: e7f9 b.n 8008fd8 08008fe4 <_sbrk_r>: 8008fe4: 2300 movs r3, #0 8008fe6: b570 push {r4, r5, r6, lr} 8008fe8: 4d06 ldr r5, [pc, #24] @ (8009004 <_sbrk_r+0x20>) 8008fea: 0004 movs r4, r0 8008fec: 0008 movs r0, r1 8008fee: 602b str r3, [r5, #0] 8008ff0: f7fb faae bl 8004550 <_sbrk> 8008ff4: 1c43 adds r3, r0, #1 8008ff6: d103 bne.n 8009000 <_sbrk_r+0x1c> 8008ff8: 682b ldr r3, [r5, #0] 8008ffa: 2b00 cmp r3, #0 8008ffc: d000 beq.n 8009000 <_sbrk_r+0x1c> 8008ffe: 6023 str r3, [r4, #0] 8009000: bd70 pop {r4, r5, r6, pc} 8009002: 46c0 nop @ (mov r8, r8) 8009004: 20000b34 .word 0x20000b34 08009008 <__errno>: 8009008: 4b01 ldr r3, [pc, #4] @ (8009010 <__errno+0x8>) 800900a: 6818 ldr r0, [r3, #0] 800900c: 4770 bx lr 800900e: 46c0 nop @ (mov r8, r8) 8009010: 2000000c .word 0x2000000c 08009014 <__libc_init_array>: 8009014: b570 push {r4, r5, r6, lr} 8009016: 2600 movs r6, #0 8009018: 4c0c ldr r4, [pc, #48] @ (800904c <__libc_init_array+0x38>) 800901a: 4d0d ldr r5, [pc, #52] @ (8009050 <__libc_init_array+0x3c>) 800901c: 1b64 subs r4, r4, r5 800901e: 10a4 asrs r4, r4, #2 8009020: 42a6 cmp r6, r4 8009022: d109 bne.n 8009038 <__libc_init_array+0x24> 8009024: 2600 movs r6, #0 8009026: f000 fecd bl 8009dc4 <_init> 800902a: 4c0a ldr r4, [pc, #40] @ (8009054 <__libc_init_array+0x40>) 800902c: 4d0a ldr r5, [pc, #40] @ (8009058 <__libc_init_array+0x44>) 800902e: 1b64 subs r4, r4, r5 8009030: 10a4 asrs r4, r4, #2 8009032: 42a6 cmp r6, r4 8009034: d105 bne.n 8009042 <__libc_init_array+0x2e> 8009036: bd70 pop {r4, r5, r6, pc} 8009038: 00b3 lsls r3, r6, #2 800903a: 58eb ldr r3, [r5, r3] 800903c: 4798 blx r3 800903e: 3601 adds r6, #1 8009040: e7ee b.n 8009020 <__libc_init_array+0xc> 8009042: 00b3 lsls r3, r6, #2 8009044: 58eb ldr r3, [r5, r3] 8009046: 4798 blx r3 8009048: 3601 adds r6, #1 800904a: e7f2 b.n 8009032 <__libc_init_array+0x1e> 800904c: 08009fe0 .word 0x08009fe0 8009050: 08009fe0 .word 0x08009fe0 8009054: 08009fe4 .word 0x08009fe4 8009058: 08009fe0 .word 0x08009fe0 0800905c <__retarget_lock_acquire_recursive>: 800905c: 4770 bx lr 0800905e <__retarget_lock_release_recursive>: 800905e: 4770 bx lr 08009060 : 8009060: b5f8 push {r3, r4, r5, r6, r7, lr} 8009062: 0004 movs r4, r0 8009064: 000d movs r5, r1 8009066: f000 f91f bl 80092a8 <__ieee754_asin> 800906a: 0022 movs r2, r4 800906c: 0006 movs r6, r0 800906e: 000f movs r7, r1 8009070: 002b movs r3, r5 8009072: 0020 movs r0, r4 8009074: 0029 movs r1, r5 8009076: f7f9 fdf3 bl 8002c60 <__aeabi_dcmpun> 800907a: 2800 cmp r0, #0 800907c: d112 bne.n 80090a4 800907e: 0020 movs r0, r4 8009080: 0029 movs r1, r5 8009082: f000 f81b bl 80090bc 8009086: 2200 movs r2, #0 8009088: 4b08 ldr r3, [pc, #32] @ (80090ac ) 800908a: f7f7 f8f1 bl 8000270 <__aeabi_dcmpgt> 800908e: 2800 cmp r0, #0 8009090: d008 beq.n 80090a4 8009092: f7ff ffb9 bl 8009008 <__errno> 8009096: 2321 movs r3, #33 @ 0x21 8009098: 6003 str r3, [r0, #0] 800909a: 4805 ldr r0, [pc, #20] @ (80090b0 ) 800909c: f000 f816 bl 80090cc 80090a0: 0006 movs r6, r0 80090a2: 000f movs r7, r1 80090a4: 0030 movs r0, r6 80090a6: 0039 movs r1, r7 80090a8: bdf8 pop {r3, r4, r5, r6, r7, pc} 80090aa: 46c0 nop @ (mov r8, r8) 80090ac: 3ff00000 .word 0x3ff00000 80090b0: 08009f30 .word 0x08009f30 080090b4 : 80090b4: b510 push {r4, lr} 80090b6: f000 fad1 bl 800965c <__ieee754_atan2> 80090ba: bd10 pop {r4, pc} 080090bc : 80090bc: 0049 lsls r1, r1, #1 80090be: 084b lsrs r3, r1, #1 80090c0: 0019 movs r1, r3 80090c2: 4770 bx lr 080090c4 : 80090c4: b510 push {r4, lr} 80090c6: f000 fcef bl 8009aa8 <__ieee754_atan2f> 80090ca: bd10 pop {r4, pc} 080090cc : 80090cc: 2000 movs r0, #0 80090ce: 4901 ldr r1, [pc, #4] @ (80090d4 ) 80090d0: 4770 bx lr 80090d2: 46c0 nop @ (mov r8, r8) 80090d4: 7ff80000 .word 0x7ff80000 080090d8 <__ieee754_sqrt>: 80090d8: b5f0 push {r4, r5, r6, r7, lr} 80090da: 000a movs r2, r1 80090dc: 000d movs r5, r1 80090de: 496d ldr r1, [pc, #436] @ (8009294 <__ieee754_sqrt+0x1bc>) 80090e0: 0004 movs r4, r0 80090e2: 0003 movs r3, r0 80090e4: 0008 movs r0, r1 80090e6: b087 sub sp, #28 80090e8: 4028 ands r0, r5 80090ea: 4288 cmp r0, r1 80090ec: d111 bne.n 8009112 <__ieee754_sqrt+0x3a> 80090ee: 0022 movs r2, r4 80090f0: 002b movs r3, r5 80090f2: 0020 movs r0, r4 80090f4: 0029 movs r1, r5 80090f6: f7f8 ff4f bl 8001f98 <__aeabi_dmul> 80090fa: 0002 movs r2, r0 80090fc: 000b movs r3, r1 80090fe: 0020 movs r0, r4 8009100: 0029 movs r1, r5 8009102: f7f7 ffa1 bl 8001048 <__aeabi_dadd> 8009106: 0004 movs r4, r0 8009108: 000d movs r5, r1 800910a: 0020 movs r0, r4 800910c: 0029 movs r1, r5 800910e: b007 add sp, #28 8009110: bdf0 pop {r4, r5, r6, r7, pc} 8009112: 2d00 cmp r5, #0 8009114: dc11 bgt.n 800913a <__ieee754_sqrt+0x62> 8009116: 0069 lsls r1, r5, #1 8009118: 0849 lsrs r1, r1, #1 800911a: 4321 orrs r1, r4 800911c: d0f5 beq.n 800910a <__ieee754_sqrt+0x32> 800911e: 2000 movs r0, #0 8009120: 4285 cmp r5, r0 8009122: d010 beq.n 8009146 <__ieee754_sqrt+0x6e> 8009124: 0022 movs r2, r4 8009126: 002b movs r3, r5 8009128: 0020 movs r0, r4 800912a: 0029 movs r1, r5 800912c: f7f9 f9fc bl 8002528 <__aeabi_dsub> 8009130: 0002 movs r2, r0 8009132: 000b movs r3, r1 8009134: f7f8 faec bl 8001710 <__aeabi_ddiv> 8009138: e7e5 b.n 8009106 <__ieee754_sqrt+0x2e> 800913a: 1528 asrs r0, r5, #20 800913c: d115 bne.n 800916a <__ieee754_sqrt+0x92> 800913e: 2480 movs r4, #128 @ 0x80 8009140: 2100 movs r1, #0 8009142: 0364 lsls r4, r4, #13 8009144: e007 b.n 8009156 <__ieee754_sqrt+0x7e> 8009146: 0ada lsrs r2, r3, #11 8009148: 3815 subs r0, #21 800914a: 055b lsls r3, r3, #21 800914c: 2a00 cmp r2, #0 800914e: d0fa beq.n 8009146 <__ieee754_sqrt+0x6e> 8009150: e7f5 b.n 800913e <__ieee754_sqrt+0x66> 8009152: 0052 lsls r2, r2, #1 8009154: 3101 adds r1, #1 8009156: 4222 tst r2, r4 8009158: d0fb beq.n 8009152 <__ieee754_sqrt+0x7a> 800915a: 1e4c subs r4, r1, #1 800915c: 1b00 subs r0, r0, r4 800915e: 2420 movs r4, #32 8009160: 001d movs r5, r3 8009162: 1a64 subs r4, r4, r1 8009164: 40e5 lsrs r5, r4 8009166: 408b lsls r3, r1 8009168: 432a orrs r2, r5 800916a: 494b ldr r1, [pc, #300] @ (8009298 <__ieee754_sqrt+0x1c0>) 800916c: 0312 lsls r2, r2, #12 800916e: 1844 adds r4, r0, r1 8009170: 2180 movs r1, #128 @ 0x80 8009172: 0b12 lsrs r2, r2, #12 8009174: 0349 lsls r1, r1, #13 8009176: 4311 orrs r1, r2 8009178: 07c0 lsls r0, r0, #31 800917a: d403 bmi.n 8009184 <__ieee754_sqrt+0xac> 800917c: 0fda lsrs r2, r3, #31 800917e: 0049 lsls r1, r1, #1 8009180: 1851 adds r1, r2, r1 8009182: 005b lsls r3, r3, #1 8009184: 2500 movs r5, #0 8009186: 1062 asrs r2, r4, #1 8009188: 0049 lsls r1, r1, #1 800918a: 2480 movs r4, #128 @ 0x80 800918c: 9205 str r2, [sp, #20] 800918e: 0fda lsrs r2, r3, #31 8009190: 1852 adds r2, r2, r1 8009192: 2016 movs r0, #22 8009194: 0029 movs r1, r5 8009196: 005b lsls r3, r3, #1 8009198: 03a4 lsls r4, r4, #14 800919a: 190e adds r6, r1, r4 800919c: 4296 cmp r6, r2 800919e: dc02 bgt.n 80091a6 <__ieee754_sqrt+0xce> 80091a0: 1931 adds r1, r6, r4 80091a2: 1b92 subs r2, r2, r6 80091a4: 192d adds r5, r5, r4 80091a6: 0fde lsrs r6, r3, #31 80091a8: 0052 lsls r2, r2, #1 80091aa: 3801 subs r0, #1 80091ac: 1992 adds r2, r2, r6 80091ae: 005b lsls r3, r3, #1 80091b0: 0864 lsrs r4, r4, #1 80091b2: 2800 cmp r0, #0 80091b4: d1f1 bne.n 800919a <__ieee754_sqrt+0xc2> 80091b6: 2620 movs r6, #32 80091b8: 2780 movs r7, #128 @ 0x80 80091ba: 0004 movs r4, r0 80091bc: 9604 str r6, [sp, #16] 80091be: 063f lsls r7, r7, #24 80091c0: 19c6 adds r6, r0, r7 80091c2: 46b4 mov ip, r6 80091c4: 4291 cmp r1, r2 80091c6: db02 blt.n 80091ce <__ieee754_sqrt+0xf6> 80091c8: d114 bne.n 80091f4 <__ieee754_sqrt+0x11c> 80091ca: 429e cmp r6, r3 80091cc: d812 bhi.n 80091f4 <__ieee754_sqrt+0x11c> 80091ce: 4660 mov r0, ip 80091d0: 4666 mov r6, ip 80091d2: 19c0 adds r0, r0, r7 80091d4: 9100 str r1, [sp, #0] 80091d6: 2e00 cmp r6, #0 80091d8: da03 bge.n 80091e2 <__ieee754_sqrt+0x10a> 80091da: 43c6 mvns r6, r0 80091dc: 0ff6 lsrs r6, r6, #31 80091de: 198e adds r6, r1, r6 80091e0: 9600 str r6, [sp, #0] 80091e2: 1a52 subs r2, r2, r1 80091e4: 4563 cmp r3, ip 80091e6: 4189 sbcs r1, r1 80091e8: 4249 negs r1, r1 80091ea: 1a52 subs r2, r2, r1 80091ec: 4661 mov r1, ip 80091ee: 1a5b subs r3, r3, r1 80091f0: 9900 ldr r1, [sp, #0] 80091f2: 19e4 adds r4, r4, r7 80091f4: 0fde lsrs r6, r3, #31 80091f6: 0052 lsls r2, r2, #1 80091f8: 1992 adds r2, r2, r6 80091fa: 9e04 ldr r6, [sp, #16] 80091fc: 005b lsls r3, r3, #1 80091fe: 3e01 subs r6, #1 8009200: 087f lsrs r7, r7, #1 8009202: 9604 str r6, [sp, #16] 8009204: 2e00 cmp r6, #0 8009206: d1db bne.n 80091c0 <__ieee754_sqrt+0xe8> 8009208: 431a orrs r2, r3 800920a: d01f beq.n 800924c <__ieee754_sqrt+0x174> 800920c: 4e23 ldr r6, [pc, #140] @ (800929c <__ieee754_sqrt+0x1c4>) 800920e: 4f24 ldr r7, [pc, #144] @ (80092a0 <__ieee754_sqrt+0x1c8>) 8009210: 6830 ldr r0, [r6, #0] 8009212: 6871 ldr r1, [r6, #4] 8009214: 683a ldr r2, [r7, #0] 8009216: 687b ldr r3, [r7, #4] 8009218: 9200 str r2, [sp, #0] 800921a: 9301 str r3, [sp, #4] 800921c: 6832 ldr r2, [r6, #0] 800921e: 6873 ldr r3, [r6, #4] 8009220: 9202 str r2, [sp, #8] 8009222: 9303 str r3, [sp, #12] 8009224: 9a00 ldr r2, [sp, #0] 8009226: 9b01 ldr r3, [sp, #4] 8009228: f7f9 f97e bl 8002528 <__aeabi_dsub> 800922c: 0002 movs r2, r0 800922e: 000b movs r3, r1 8009230: 9802 ldr r0, [sp, #8] 8009232: 9903 ldr r1, [sp, #12] 8009234: f7f7 f812 bl 800025c <__aeabi_dcmple> 8009238: 2800 cmp r0, #0 800923a: d007 beq.n 800924c <__ieee754_sqrt+0x174> 800923c: 6830 ldr r0, [r6, #0] 800923e: 6871 ldr r1, [r6, #4] 8009240: 683a ldr r2, [r7, #0] 8009242: 687b ldr r3, [r7, #4] 8009244: 1c67 adds r7, r4, #1 8009246: d10f bne.n 8009268 <__ieee754_sqrt+0x190> 8009248: 9c04 ldr r4, [sp, #16] 800924a: 3501 adds r5, #1 800924c: 4b15 ldr r3, [pc, #84] @ (80092a4 <__ieee754_sqrt+0x1cc>) 800924e: 106a asrs r2, r5, #1 8009250: 18d2 adds r2, r2, r3 8009252: 0863 lsrs r3, r4, #1 8009254: 07ed lsls r5, r5, #31 8009256: d502 bpl.n 800925e <__ieee754_sqrt+0x186> 8009258: 2180 movs r1, #128 @ 0x80 800925a: 0609 lsls r1, r1, #24 800925c: 430b orrs r3, r1 800925e: 9905 ldr r1, [sp, #20] 8009260: 001c movs r4, r3 8009262: 0509 lsls r1, r1, #20 8009264: 188d adds r5, r1, r2 8009266: e750 b.n 800910a <__ieee754_sqrt+0x32> 8009268: f7f7 feee bl 8001048 <__aeabi_dadd> 800926c: 6877 ldr r7, [r6, #4] 800926e: 6836 ldr r6, [r6, #0] 8009270: 0002 movs r2, r0 8009272: 000b movs r3, r1 8009274: 0030 movs r0, r6 8009276: 0039 movs r1, r7 8009278: f7f6 ffe6 bl 8000248 <__aeabi_dcmplt> 800927c: 2800 cmp r0, #0 800927e: d004 beq.n 800928a <__ieee754_sqrt+0x1b2> 8009280: 3402 adds r4, #2 8009282: 4263 negs r3, r4 8009284: 4163 adcs r3, r4 8009286: 18ed adds r5, r5, r3 8009288: e7e0 b.n 800924c <__ieee754_sqrt+0x174> 800928a: 2301 movs r3, #1 800928c: 3401 adds r4, #1 800928e: 439c bics r4, r3 8009290: e7dc b.n 800924c <__ieee754_sqrt+0x174> 8009292: 46c0 nop @ (mov r8, r8) 8009294: 7ff00000 .word 0x7ff00000 8009298: fffffc01 .word 0xfffffc01 800929c: 20000068 .word 0x20000068 80092a0: 20000060 .word 0x20000060 80092a4: 3fe00000 .word 0x3fe00000 080092a8 <__ieee754_asin>: 80092a8: b5f0 push {r4, r5, r6, r7, lr} 80092aa: 4bcb ldr r3, [pc, #812] @ (80095d8 <__ieee754_asin+0x330>) 80092ac: b08b sub sp, #44 @ 0x2c 80092ae: 004c lsls r4, r1, #1 80092b0: 0006 movs r6, r0 80092b2: 000f movs r7, r1 80092b4: 9109 str r1, [sp, #36] @ 0x24 80092b6: 0864 lsrs r4, r4, #1 80092b8: 429c cmp r4, r3 80092ba: d924 bls.n 8009306 <__ieee754_asin+0x5e> 80092bc: 4bc7 ldr r3, [pc, #796] @ (80095dc <__ieee754_asin+0x334>) 80092be: 18e4 adds r4, r4, r3 80092c0: 4304 orrs r4, r0 80092c2: d112 bne.n 80092ea <__ieee754_asin+0x42> 80092c4: 4ac6 ldr r2, [pc, #792] @ (80095e0 <__ieee754_asin+0x338>) 80092c6: 4bc7 ldr r3, [pc, #796] @ (80095e4 <__ieee754_asin+0x33c>) 80092c8: f7f8 fe66 bl 8001f98 <__aeabi_dmul> 80092cc: 4ac6 ldr r2, [pc, #792] @ (80095e8 <__ieee754_asin+0x340>) 80092ce: 0004 movs r4, r0 80092d0: 000d movs r5, r1 80092d2: 4bc6 ldr r3, [pc, #792] @ (80095ec <__ieee754_asin+0x344>) 80092d4: 0030 movs r0, r6 80092d6: 0039 movs r1, r7 80092d8: f7f8 fe5e bl 8001f98 <__aeabi_dmul> 80092dc: 0002 movs r2, r0 80092de: 000b movs r3, r1 80092e0: 0020 movs r0, r4 80092e2: 0029 movs r1, r5 80092e4: f7f7 feb0 bl 8001048 <__aeabi_dadd> 80092e8: e007 b.n 80092fa <__ieee754_asin+0x52> 80092ea: 0002 movs r2, r0 80092ec: 000b movs r3, r1 80092ee: f7f9 f91b bl 8002528 <__aeabi_dsub> 80092f2: 0002 movs r2, r0 80092f4: 000b movs r3, r1 80092f6: f7f8 fa0b bl 8001710 <__aeabi_ddiv> 80092fa: 0006 movs r6, r0 80092fc: 000f movs r7, r1 80092fe: 0030 movs r0, r6 8009300: 0039 movs r1, r7 8009302: b00b add sp, #44 @ 0x2c 8009304: bdf0 pop {r4, r5, r6, r7, pc} 8009306: 4bba ldr r3, [pc, #744] @ (80095f0 <__ieee754_asin+0x348>) 8009308: 429c cmp r4, r3 800930a: d80e bhi.n 800932a <__ieee754_asin+0x82> 800930c: 23f9 movs r3, #249 @ 0xf9 800930e: 059b lsls r3, r3, #22 8009310: 429c cmp r4, r3 8009312: d300 bcc.n 8009316 <__ieee754_asin+0x6e> 8009314: e09d b.n 8009452 <__ieee754_asin+0x1aa> 8009316: 4ab7 ldr r2, [pc, #732] @ (80095f4 <__ieee754_asin+0x34c>) 8009318: 4bb7 ldr r3, [pc, #732] @ (80095f8 <__ieee754_asin+0x350>) 800931a: f7f7 fe95 bl 8001048 <__aeabi_dadd> 800931e: 2200 movs r2, #0 8009320: 4bb6 ldr r3, [pc, #728] @ (80095fc <__ieee754_asin+0x354>) 8009322: f7f6 ffa5 bl 8000270 <__aeabi_dcmpgt> 8009326: 2800 cmp r0, #0 8009328: d1e9 bne.n 80092fe <__ieee754_asin+0x56> 800932a: 0030 movs r0, r6 800932c: 0039 movs r1, r7 800932e: f7ff fec5 bl 80090bc 8009332: 0002 movs r2, r0 8009334: 000b movs r3, r1 8009336: 2000 movs r0, #0 8009338: 49b0 ldr r1, [pc, #704] @ (80095fc <__ieee754_asin+0x354>) 800933a: f7f9 f8f5 bl 8002528 <__aeabi_dsub> 800933e: 2200 movs r2, #0 8009340: 4baf ldr r3, [pc, #700] @ (8009600 <__ieee754_asin+0x358>) 8009342: f7f8 fe29 bl 8001f98 <__aeabi_dmul> 8009346: 0006 movs r6, r0 8009348: 000f movs r7, r1 800934a: 4aae ldr r2, [pc, #696] @ (8009604 <__ieee754_asin+0x35c>) 800934c: 4bae ldr r3, [pc, #696] @ (8009608 <__ieee754_asin+0x360>) 800934e: f7f8 fe23 bl 8001f98 <__aeabi_dmul> 8009352: 4aae ldr r2, [pc, #696] @ (800960c <__ieee754_asin+0x364>) 8009354: 4bae ldr r3, [pc, #696] @ (8009610 <__ieee754_asin+0x368>) 8009356: f7f7 fe77 bl 8001048 <__aeabi_dadd> 800935a: 0032 movs r2, r6 800935c: 003b movs r3, r7 800935e: f7f8 fe1b bl 8001f98 <__aeabi_dmul> 8009362: 4aac ldr r2, [pc, #688] @ (8009614 <__ieee754_asin+0x36c>) 8009364: 4bac ldr r3, [pc, #688] @ (8009618 <__ieee754_asin+0x370>) 8009366: f7f9 f8df bl 8002528 <__aeabi_dsub> 800936a: 0032 movs r2, r6 800936c: 003b movs r3, r7 800936e: f7f8 fe13 bl 8001f98 <__aeabi_dmul> 8009372: 4aaa ldr r2, [pc, #680] @ (800961c <__ieee754_asin+0x374>) 8009374: 4baa ldr r3, [pc, #680] @ (8009620 <__ieee754_asin+0x378>) 8009376: f7f7 fe67 bl 8001048 <__aeabi_dadd> 800937a: 0032 movs r2, r6 800937c: 003b movs r3, r7 800937e: f7f8 fe0b bl 8001f98 <__aeabi_dmul> 8009382: 4aa8 ldr r2, [pc, #672] @ (8009624 <__ieee754_asin+0x37c>) 8009384: 4ba8 ldr r3, [pc, #672] @ (8009628 <__ieee754_asin+0x380>) 8009386: f7f9 f8cf bl 8002528 <__aeabi_dsub> 800938a: 0032 movs r2, r6 800938c: 003b movs r3, r7 800938e: f7f8 fe03 bl 8001f98 <__aeabi_dmul> 8009392: 4aa6 ldr r2, [pc, #664] @ (800962c <__ieee754_asin+0x384>) 8009394: 4ba6 ldr r3, [pc, #664] @ (8009630 <__ieee754_asin+0x388>) 8009396: f7f7 fe57 bl 8001048 <__aeabi_dadd> 800939a: 0032 movs r2, r6 800939c: 003b movs r3, r7 800939e: f7f8 fdfb bl 8001f98 <__aeabi_dmul> 80093a2: 4aa4 ldr r2, [pc, #656] @ (8009634 <__ieee754_asin+0x38c>) 80093a4: 9004 str r0, [sp, #16] 80093a6: 9105 str r1, [sp, #20] 80093a8: 4ba3 ldr r3, [pc, #652] @ (8009638 <__ieee754_asin+0x390>) 80093aa: 0030 movs r0, r6 80093ac: 0039 movs r1, r7 80093ae: f7f8 fdf3 bl 8001f98 <__aeabi_dmul> 80093b2: 4aa2 ldr r2, [pc, #648] @ (800963c <__ieee754_asin+0x394>) 80093b4: 4ba2 ldr r3, [pc, #648] @ (8009640 <__ieee754_asin+0x398>) 80093b6: f7f9 f8b7 bl 8002528 <__aeabi_dsub> 80093ba: 0032 movs r2, r6 80093bc: 003b movs r3, r7 80093be: f7f8 fdeb bl 8001f98 <__aeabi_dmul> 80093c2: 4aa0 ldr r2, [pc, #640] @ (8009644 <__ieee754_asin+0x39c>) 80093c4: 4ba0 ldr r3, [pc, #640] @ (8009648 <__ieee754_asin+0x3a0>) 80093c6: f7f7 fe3f bl 8001048 <__aeabi_dadd> 80093ca: 0032 movs r2, r6 80093cc: 003b movs r3, r7 80093ce: f7f8 fde3 bl 8001f98 <__aeabi_dmul> 80093d2: 4a9e ldr r2, [pc, #632] @ (800964c <__ieee754_asin+0x3a4>) 80093d4: 4b9e ldr r3, [pc, #632] @ (8009650 <__ieee754_asin+0x3a8>) 80093d6: f7f9 f8a7 bl 8002528 <__aeabi_dsub> 80093da: 0032 movs r2, r6 80093dc: 003b movs r3, r7 80093de: f7f8 fddb bl 8001f98 <__aeabi_dmul> 80093e2: 4b86 ldr r3, [pc, #536] @ (80095fc <__ieee754_asin+0x354>) 80093e4: 2200 movs r2, #0 80093e6: f7f7 fe2f bl 8001048 <__aeabi_dadd> 80093ea: 9006 str r0, [sp, #24] 80093ec: 9107 str r1, [sp, #28] 80093ee: 0030 movs r0, r6 80093f0: 0039 movs r1, r7 80093f2: f7ff fe71 bl 80090d8 <__ieee754_sqrt> 80093f6: 4b97 ldr r3, [pc, #604] @ (8009654 <__ieee754_asin+0x3ac>) 80093f8: 9000 str r0, [sp, #0] 80093fa: 9101 str r1, [sp, #4] 80093fc: 429c cmp r4, r3 80093fe: d800 bhi.n 8009402 <__ieee754_asin+0x15a> 8009400: e08c b.n 800951c <__ieee754_asin+0x274> 8009402: 9a06 ldr r2, [sp, #24] 8009404: 9b07 ldr r3, [sp, #28] 8009406: 9804 ldr r0, [sp, #16] 8009408: 9905 ldr r1, [sp, #20] 800940a: f7f8 f981 bl 8001710 <__aeabi_ddiv> 800940e: 9a00 ldr r2, [sp, #0] 8009410: 9b01 ldr r3, [sp, #4] 8009412: f7f8 fdc1 bl 8001f98 <__aeabi_dmul> 8009416: 9a00 ldr r2, [sp, #0] 8009418: 9b01 ldr r3, [sp, #4] 800941a: f7f7 fe15 bl 8001048 <__aeabi_dadd> 800941e: 0002 movs r2, r0 8009420: 000b movs r3, r1 8009422: f7f7 fe11 bl 8001048 <__aeabi_dadd> 8009426: 4a70 ldr r2, [pc, #448] @ (80095e8 <__ieee754_asin+0x340>) 8009428: 4b70 ldr r3, [pc, #448] @ (80095ec <__ieee754_asin+0x344>) 800942a: f7f9 f87d bl 8002528 <__aeabi_dsub> 800942e: 0002 movs r2, r0 8009430: 000b movs r3, r1 8009432: 486b ldr r0, [pc, #428] @ (80095e0 <__ieee754_asin+0x338>) 8009434: 496b ldr r1, [pc, #428] @ (80095e4 <__ieee754_asin+0x33c>) 8009436: f7f9 f877 bl 8002528 <__aeabi_dsub> 800943a: 9b09 ldr r3, [sp, #36] @ 0x24 800943c: 0006 movs r6, r0 800943e: 000f movs r7, r1 8009440: 2b00 cmp r3, #0 8009442: dd00 ble.n 8009446 <__ieee754_asin+0x19e> 8009444: e75b b.n 80092fe <__ieee754_asin+0x56> 8009446: 2180 movs r1, #128 @ 0x80 8009448: 0609 lsls r1, r1, #24 800944a: 187b adds r3, r7, r1 800944c: 0006 movs r6, r0 800944e: 001f movs r7, r3 8009450: e755 b.n 80092fe <__ieee754_asin+0x56> 8009452: 0002 movs r2, r0 8009454: 000b movs r3, r1 8009456: f7f8 fd9f bl 8001f98 <__aeabi_dmul> 800945a: 0004 movs r4, r0 800945c: 000d movs r5, r1 800945e: 4a69 ldr r2, [pc, #420] @ (8009604 <__ieee754_asin+0x35c>) 8009460: 4b69 ldr r3, [pc, #420] @ (8009608 <__ieee754_asin+0x360>) 8009462: f7f8 fd99 bl 8001f98 <__aeabi_dmul> 8009466: 4a69 ldr r2, [pc, #420] @ (800960c <__ieee754_asin+0x364>) 8009468: 4b69 ldr r3, [pc, #420] @ (8009610 <__ieee754_asin+0x368>) 800946a: f7f7 fded bl 8001048 <__aeabi_dadd> 800946e: 0022 movs r2, r4 8009470: 002b movs r3, r5 8009472: f7f8 fd91 bl 8001f98 <__aeabi_dmul> 8009476: 4a67 ldr r2, [pc, #412] @ (8009614 <__ieee754_asin+0x36c>) 8009478: 4b67 ldr r3, [pc, #412] @ (8009618 <__ieee754_asin+0x370>) 800947a: f7f9 f855 bl 8002528 <__aeabi_dsub> 800947e: 0022 movs r2, r4 8009480: 002b movs r3, r5 8009482: f7f8 fd89 bl 8001f98 <__aeabi_dmul> 8009486: 4a65 ldr r2, [pc, #404] @ (800961c <__ieee754_asin+0x374>) 8009488: 4b65 ldr r3, [pc, #404] @ (8009620 <__ieee754_asin+0x378>) 800948a: f7f7 fddd bl 8001048 <__aeabi_dadd> 800948e: 0022 movs r2, r4 8009490: 002b movs r3, r5 8009492: f7f8 fd81 bl 8001f98 <__aeabi_dmul> 8009496: 4a63 ldr r2, [pc, #396] @ (8009624 <__ieee754_asin+0x37c>) 8009498: 4b63 ldr r3, [pc, #396] @ (8009628 <__ieee754_asin+0x380>) 800949a: f7f9 f845 bl 8002528 <__aeabi_dsub> 800949e: 0022 movs r2, r4 80094a0: 002b movs r3, r5 80094a2: f7f8 fd79 bl 8001f98 <__aeabi_dmul> 80094a6: 4a61 ldr r2, [pc, #388] @ (800962c <__ieee754_asin+0x384>) 80094a8: 4b61 ldr r3, [pc, #388] @ (8009630 <__ieee754_asin+0x388>) 80094aa: f7f7 fdcd bl 8001048 <__aeabi_dadd> 80094ae: 0022 movs r2, r4 80094b0: 002b movs r3, r5 80094b2: f7f8 fd71 bl 8001f98 <__aeabi_dmul> 80094b6: 4a5f ldr r2, [pc, #380] @ (8009634 <__ieee754_asin+0x38c>) 80094b8: 9000 str r0, [sp, #0] 80094ba: 9101 str r1, [sp, #4] 80094bc: 4b5e ldr r3, [pc, #376] @ (8009638 <__ieee754_asin+0x390>) 80094be: 0020 movs r0, r4 80094c0: 0029 movs r1, r5 80094c2: f7f8 fd69 bl 8001f98 <__aeabi_dmul> 80094c6: 4a5d ldr r2, [pc, #372] @ (800963c <__ieee754_asin+0x394>) 80094c8: 4b5d ldr r3, [pc, #372] @ (8009640 <__ieee754_asin+0x398>) 80094ca: f7f9 f82d bl 8002528 <__aeabi_dsub> 80094ce: 0022 movs r2, r4 80094d0: 002b movs r3, r5 80094d2: f7f8 fd61 bl 8001f98 <__aeabi_dmul> 80094d6: 4a5b ldr r2, [pc, #364] @ (8009644 <__ieee754_asin+0x39c>) 80094d8: 4b5b ldr r3, [pc, #364] @ (8009648 <__ieee754_asin+0x3a0>) 80094da: f7f7 fdb5 bl 8001048 <__aeabi_dadd> 80094de: 0022 movs r2, r4 80094e0: 002b movs r3, r5 80094e2: f7f8 fd59 bl 8001f98 <__aeabi_dmul> 80094e6: 4a59 ldr r2, [pc, #356] @ (800964c <__ieee754_asin+0x3a4>) 80094e8: 4b59 ldr r3, [pc, #356] @ (8009650 <__ieee754_asin+0x3a8>) 80094ea: f7f9 f81d bl 8002528 <__aeabi_dsub> 80094ee: 0022 movs r2, r4 80094f0: 002b movs r3, r5 80094f2: f7f8 fd51 bl 8001f98 <__aeabi_dmul> 80094f6: 2200 movs r2, #0 80094f8: 4b40 ldr r3, [pc, #256] @ (80095fc <__ieee754_asin+0x354>) 80094fa: f7f7 fda5 bl 8001048 <__aeabi_dadd> 80094fe: 0002 movs r2, r0 8009500: 000b movs r3, r1 8009502: 9800 ldr r0, [sp, #0] 8009504: 9901 ldr r1, [sp, #4] 8009506: f7f8 f903 bl 8001710 <__aeabi_ddiv> 800950a: 0032 movs r2, r6 800950c: 003b movs r3, r7 800950e: f7f8 fd43 bl 8001f98 <__aeabi_dmul> 8009512: 0002 movs r2, r0 8009514: 000b movs r3, r1 8009516: 0030 movs r0, r6 8009518: 0039 movs r1, r7 800951a: e6e3 b.n 80092e4 <__ieee754_asin+0x3c> 800951c: 9a00 ldr r2, [sp, #0] 800951e: 9b01 ldr r3, [sp, #4] 8009520: 2200 movs r2, #0 8009522: 9202 str r2, [sp, #8] 8009524: 9303 str r3, [sp, #12] 8009526: 9a00 ldr r2, [sp, #0] 8009528: 9b01 ldr r3, [sp, #4] 800952a: 0010 movs r0, r2 800952c: 0019 movs r1, r3 800952e: f7f7 fd8b bl 8001048 <__aeabi_dadd> 8009532: 9a06 ldr r2, [sp, #24] 8009534: 9b07 ldr r3, [sp, #28] 8009536: 0004 movs r4, r0 8009538: 000d movs r5, r1 800953a: 9804 ldr r0, [sp, #16] 800953c: 9905 ldr r1, [sp, #20] 800953e: f7f8 f8e7 bl 8001710 <__aeabi_ddiv> 8009542: 0002 movs r2, r0 8009544: 000b movs r3, r1 8009546: 0020 movs r0, r4 8009548: 0029 movs r1, r5 800954a: f7f8 fd25 bl 8001f98 <__aeabi_dmul> 800954e: 9a02 ldr r2, [sp, #8] 8009550: 9b03 ldr r3, [sp, #12] 8009552: 9004 str r0, [sp, #16] 8009554: 9105 str r1, [sp, #20] 8009556: 0010 movs r0, r2 8009558: 0019 movs r1, r3 800955a: f7f8 fd1d bl 8001f98 <__aeabi_dmul> 800955e: 0002 movs r2, r0 8009560: 000b movs r3, r1 8009562: 0030 movs r0, r6 8009564: 0039 movs r1, r7 8009566: f7f8 ffdf bl 8002528 <__aeabi_dsub> 800956a: 9a02 ldr r2, [sp, #8] 800956c: 9b03 ldr r3, [sp, #12] 800956e: 0004 movs r4, r0 8009570: 000d movs r5, r1 8009572: 9800 ldr r0, [sp, #0] 8009574: 9901 ldr r1, [sp, #4] 8009576: f7f7 fd67 bl 8001048 <__aeabi_dadd> 800957a: 0002 movs r2, r0 800957c: 000b movs r3, r1 800957e: 0020 movs r0, r4 8009580: 0029 movs r1, r5 8009582: f7f8 f8c5 bl 8001710 <__aeabi_ddiv> 8009586: 0002 movs r2, r0 8009588: 000b movs r3, r1 800958a: f7f7 fd5d bl 8001048 <__aeabi_dadd> 800958e: 0002 movs r2, r0 8009590: 000b movs r3, r1 8009592: 4815 ldr r0, [pc, #84] @ (80095e8 <__ieee754_asin+0x340>) 8009594: 4915 ldr r1, [pc, #84] @ (80095ec <__ieee754_asin+0x344>) 8009596: f7f8 ffc7 bl 8002528 <__aeabi_dsub> 800959a: 0002 movs r2, r0 800959c: 000b movs r3, r1 800959e: 9804 ldr r0, [sp, #16] 80095a0: 9905 ldr r1, [sp, #20] 80095a2: f7f8 ffc1 bl 8002528 <__aeabi_dsub> 80095a6: 9a02 ldr r2, [sp, #8] 80095a8: 9b03 ldr r3, [sp, #12] 80095aa: 0004 movs r4, r0 80095ac: 000d movs r5, r1 80095ae: 0010 movs r0, r2 80095b0: 0019 movs r1, r3 80095b2: f7f7 fd49 bl 8001048 <__aeabi_dadd> 80095b6: 0002 movs r2, r0 80095b8: 000b movs r3, r1 80095ba: 4809 ldr r0, [pc, #36] @ (80095e0 <__ieee754_asin+0x338>) 80095bc: 4926 ldr r1, [pc, #152] @ (8009658 <__ieee754_asin+0x3b0>) 80095be: f7f8 ffb3 bl 8002528 <__aeabi_dsub> 80095c2: 0002 movs r2, r0 80095c4: 000b movs r3, r1 80095c6: 0020 movs r0, r4 80095c8: 0029 movs r1, r5 80095ca: f7f8 ffad bl 8002528 <__aeabi_dsub> 80095ce: 0002 movs r2, r0 80095d0: 000b movs r3, r1 80095d2: 4803 ldr r0, [pc, #12] @ (80095e0 <__ieee754_asin+0x338>) 80095d4: 4920 ldr r1, [pc, #128] @ (8009658 <__ieee754_asin+0x3b0>) 80095d6: e72e b.n 8009436 <__ieee754_asin+0x18e> 80095d8: 3fefffff .word 0x3fefffff 80095dc: c0100000 .word 0xc0100000 80095e0: 54442d18 .word 0x54442d18 80095e4: 3ff921fb .word 0x3ff921fb 80095e8: 33145c07 .word 0x33145c07 80095ec: 3c91a626 .word 0x3c91a626 80095f0: 3fdfffff .word 0x3fdfffff 80095f4: 8800759c .word 0x8800759c 80095f8: 7e37e43c .word 0x7e37e43c 80095fc: 3ff00000 .word 0x3ff00000 8009600: 3fe00000 .word 0x3fe00000 8009604: 0dfdf709 .word 0x0dfdf709 8009608: 3f023de1 .word 0x3f023de1 800960c: 7501b288 .word 0x7501b288 8009610: 3f49efe0 .word 0x3f49efe0 8009614: b5688f3b .word 0xb5688f3b 8009618: 3fa48228 .word 0x3fa48228 800961c: 0e884455 .word 0x0e884455 8009620: 3fc9c155 .word 0x3fc9c155 8009624: 03eb6f7d .word 0x03eb6f7d 8009628: 3fd4d612 .word 0x3fd4d612 800962c: 55555555 .word 0x55555555 8009630: 3fc55555 .word 0x3fc55555 8009634: b12e9282 .word 0xb12e9282 8009638: 3fb3b8c5 .word 0x3fb3b8c5 800963c: 1b8d0159 .word 0x1b8d0159 8009640: 3fe6066c .word 0x3fe6066c 8009644: 9c598ac8 .word 0x9c598ac8 8009648: 40002ae5 .word 0x40002ae5 800964c: 1c8a2d4b .word 0x1c8a2d4b 8009650: 40033a27 .word 0x40033a27 8009654: 3fef3332 .word 0x3fef3332 8009658: 3fe921fb .word 0x3fe921fb 0800965c <__ieee754_atan2>: 800965c: b5f0 push {r4, r5, r6, r7, lr} 800965e: 4254 negs r4, r2 8009660: 005e lsls r6, r3, #1 8009662: 4314 orrs r4, r2 8009664: 4f44 ldr r7, [pc, #272] @ (8009778 <__ieee754_atan2+0x11c>) 8009666: b085 sub sp, #20 8009668: 0876 lsrs r6, r6, #1 800966a: 0fe4 lsrs r4, r4, #31 800966c: 9302 str r3, [sp, #8] 800966e: 4334 orrs r4, r6 8009670: 42bc cmp r4, r7 8009672: d809 bhi.n 8009688 <__ieee754_atan2+0x2c> 8009674: 4244 negs r4, r0 8009676: 004d lsls r5, r1, #1 8009678: 4304 orrs r4, r0 800967a: 086d lsrs r5, r5, #1 800967c: 0fe4 lsrs r4, r4, #31 800967e: 9101 str r1, [sp, #4] 8009680: 9003 str r0, [sp, #12] 8009682: 432c orrs r4, r5 8009684: 42bc cmp r4, r7 8009686: d903 bls.n 8009690 <__ieee754_atan2+0x34> 8009688: f7f7 fcde bl 8001048 <__aeabi_dadd> 800968c: b005 add sp, #20 800968e: bdf0 pop {r4, r5, r6, r7, pc} 8009690: 4c3a ldr r4, [pc, #232] @ (800977c <__ieee754_atan2+0x120>) 8009692: 191c adds r4, r3, r4 8009694: 4314 orrs r4, r2 8009696: d102 bne.n 800969e <__ieee754_atan2+0x42> 8009698: f000 f886 bl 80097a8 800969c: e7f6 b.n 800968c <__ieee754_atan2+0x30> 800969e: 179c asrs r4, r3, #30 80096a0: 46a4 mov ip, r4 80096a2: 2402 movs r4, #2 80096a4: 4667 mov r7, ip 80096a6: 403c ands r4, r7 80096a8: 9f01 ldr r7, [sp, #4] 80096aa: 0fff lsrs r7, r7, #31 80096ac: 433c orrs r4, r7 80096ae: 9f03 ldr r7, [sp, #12] 80096b0: 432f orrs r7, r5 80096b2: d106 bne.n 80096c2 <__ieee754_atan2+0x66> 80096b4: 2c02 cmp r4, #2 80096b6: d056 beq.n 8009766 <__ieee754_atan2+0x10a> 80096b8: 2c03 cmp r4, #3 80096ba: d1e7 bne.n 800968c <__ieee754_atan2+0x30> 80096bc: 4830 ldr r0, [pc, #192] @ (8009780 <__ieee754_atan2+0x124>) 80096be: 4931 ldr r1, [pc, #196] @ (8009784 <__ieee754_atan2+0x128>) 80096c0: e7e4 b.n 800968c <__ieee754_atan2+0x30> 80096c2: 0037 movs r7, r6 80096c4: 4317 orrs r7, r2 80096c6: d105 bne.n 80096d4 <__ieee754_atan2+0x78> 80096c8: 9b01 ldr r3, [sp, #4] 80096ca: 482d ldr r0, [pc, #180] @ (8009780 <__ieee754_atan2+0x124>) 80096cc: 2b00 cmp r3, #0 80096ce: da50 bge.n 8009772 <__ieee754_atan2+0x116> 80096d0: 492d ldr r1, [pc, #180] @ (8009788 <__ieee754_atan2+0x12c>) 80096d2: e7db b.n 800968c <__ieee754_atan2+0x30> 80096d4: 4f28 ldr r7, [pc, #160] @ (8009778 <__ieee754_atan2+0x11c>) 80096d6: 42be cmp r6, r7 80096d8: d110 bne.n 80096fc <__ieee754_atan2+0xa0> 80096da: 3c01 subs r4, #1 80096dc: 42b5 cmp r5, r6 80096de: d105 bne.n 80096ec <__ieee754_atan2+0x90> 80096e0: 4b2a ldr r3, [pc, #168] @ (800978c <__ieee754_atan2+0x130>) 80096e2: 2c02 cmp r4, #2 80096e4: d905 bls.n 80096f2 <__ieee754_atan2+0x96> 80096e6: 4826 ldr r0, [pc, #152] @ (8009780 <__ieee754_atan2+0x124>) 80096e8: 4929 ldr r1, [pc, #164] @ (8009790 <__ieee754_atan2+0x134>) 80096ea: e7cf b.n 800968c <__ieee754_atan2+0x30> 80096ec: 2c02 cmp r4, #2 80096ee: d83d bhi.n 800976c <__ieee754_atan2+0x110> 80096f0: 4b28 ldr r3, [pc, #160] @ (8009794 <__ieee754_atan2+0x138>) 80096f2: 00e4 lsls r4, r4, #3 80096f4: 191b adds r3, r3, r4 80096f6: 6818 ldr r0, [r3, #0] 80096f8: 6859 ldr r1, [r3, #4] 80096fa: e7c7 b.n 800968c <__ieee754_atan2+0x30> 80096fc: 4f1e ldr r7, [pc, #120] @ (8009778 <__ieee754_atan2+0x11c>) 80096fe: 42bd cmp r5, r7 8009700: d0e2 beq.n 80096c8 <__ieee754_atan2+0x6c> 8009702: 1bad subs r5, r5, r6 8009704: 152d asrs r5, r5, #20 8009706: 2d3c cmp r5, #60 @ 0x3c 8009708: dc17 bgt.n 800973a <__ieee754_atan2+0xde> 800970a: 9e02 ldr r6, [sp, #8] 800970c: 2e00 cmp r6, #0 800970e: da01 bge.n 8009714 <__ieee754_atan2+0xb8> 8009710: 353c adds r5, #60 @ 0x3c 8009712: db15 blt.n 8009740 <__ieee754_atan2+0xe4> 8009714: f7f7 fffc bl 8001710 <__aeabi_ddiv> 8009718: f7ff fcd0 bl 80090bc 800971c: f000 f844 bl 80097a8 8009720: 2c01 cmp r4, #1 8009722: d010 beq.n 8009746 <__ieee754_atan2+0xea> 8009724: 2c02 cmp r4, #2 8009726: d013 beq.n 8009750 <__ieee754_atan2+0xf4> 8009728: 2c00 cmp r4, #0 800972a: d0af beq.n 800968c <__ieee754_atan2+0x30> 800972c: 4a1a ldr r2, [pc, #104] @ (8009798 <__ieee754_atan2+0x13c>) 800972e: 4b1b ldr r3, [pc, #108] @ (800979c <__ieee754_atan2+0x140>) 8009730: f7f8 fefa bl 8002528 <__aeabi_dsub> 8009734: 4a12 ldr r2, [pc, #72] @ (8009780 <__ieee754_atan2+0x124>) 8009736: 4b1a ldr r3, [pc, #104] @ (80097a0 <__ieee754_atan2+0x144>) 8009738: e012 b.n 8009760 <__ieee754_atan2+0x104> 800973a: 4811 ldr r0, [pc, #68] @ (8009780 <__ieee754_atan2+0x124>) 800973c: 4919 ldr r1, [pc, #100] @ (80097a4 <__ieee754_atan2+0x148>) 800973e: e7ef b.n 8009720 <__ieee754_atan2+0xc4> 8009740: 2000 movs r0, #0 8009742: 2100 movs r1, #0 8009744: e7ec b.n 8009720 <__ieee754_atan2+0xc4> 8009746: 2480 movs r4, #128 @ 0x80 8009748: 0624 lsls r4, r4, #24 800974a: 190b adds r3, r1, r4 800974c: 0019 movs r1, r3 800974e: e79d b.n 800968c <__ieee754_atan2+0x30> 8009750: 4a11 ldr r2, [pc, #68] @ (8009798 <__ieee754_atan2+0x13c>) 8009752: 4b12 ldr r3, [pc, #72] @ (800979c <__ieee754_atan2+0x140>) 8009754: f7f8 fee8 bl 8002528 <__aeabi_dsub> 8009758: 0002 movs r2, r0 800975a: 000b movs r3, r1 800975c: 4808 ldr r0, [pc, #32] @ (8009780 <__ieee754_atan2+0x124>) 800975e: 4910 ldr r1, [pc, #64] @ (80097a0 <__ieee754_atan2+0x144>) 8009760: f7f8 fee2 bl 8002528 <__aeabi_dsub> 8009764: e792 b.n 800968c <__ieee754_atan2+0x30> 8009766: 4806 ldr r0, [pc, #24] @ (8009780 <__ieee754_atan2+0x124>) 8009768: 490d ldr r1, [pc, #52] @ (80097a0 <__ieee754_atan2+0x144>) 800976a: e78f b.n 800968c <__ieee754_atan2+0x30> 800976c: 2000 movs r0, #0 800976e: 2100 movs r1, #0 8009770: e78c b.n 800968c <__ieee754_atan2+0x30> 8009772: 490c ldr r1, [pc, #48] @ (80097a4 <__ieee754_atan2+0x148>) 8009774: e78a b.n 800968c <__ieee754_atan2+0x30> 8009776: 46c0 nop @ (mov r8, r8) 8009778: 7ff00000 .word 0x7ff00000 800977c: c0100000 .word 0xc0100000 8009780: 54442d18 .word 0x54442d18 8009784: c00921fb .word 0xc00921fb 8009788: bff921fb .word 0xbff921fb 800978c: 08009f50 .word 0x08009f50 8009790: 3fe921fb .word 0x3fe921fb 8009794: 08009f38 .word 0x08009f38 8009798: 33145c07 .word 0x33145c07 800979c: 3ca1a626 .word 0x3ca1a626 80097a0: 400921fb .word 0x400921fb 80097a4: 3ff921fb .word 0x3ff921fb 080097a8 : 80097a8: b5f0 push {r4, r5, r6, r7, lr} 80097aa: 4b98 ldr r3, [pc, #608] @ (8009a0c ) 80097ac: b085 sub sp, #20 80097ae: 004e lsls r6, r1, #1 80097b0: 0004 movs r4, r0 80097b2: 000d movs r5, r1 80097b4: 9103 str r1, [sp, #12] 80097b6: 0876 lsrs r6, r6, #1 80097b8: 429e cmp r6, r3 80097ba: d918 bls.n 80097ee 80097bc: 4b94 ldr r3, [pc, #592] @ (8009a10 ) 80097be: 429e cmp r6, r3 80097c0: d802 bhi.n 80097c8 80097c2: d10a bne.n 80097da 80097c4: 2800 cmp r0, #0 80097c6: d008 beq.n 80097da 80097c8: 0022 movs r2, r4 80097ca: 002b movs r3, r5 80097cc: 0020 movs r0, r4 80097ce: 0029 movs r1, r5 80097d0: f7f7 fc3a bl 8001048 <__aeabi_dadd> 80097d4: 0004 movs r4, r0 80097d6: 000d movs r5, r1 80097d8: e005 b.n 80097e6 80097da: 9b03 ldr r3, [sp, #12] 80097dc: 4c8d ldr r4, [pc, #564] @ (8009a14 ) 80097de: 2b00 cmp r3, #0 80097e0: dc00 bgt.n 80097e4 80097e2: e111 b.n 8009a08 80097e4: 4d8c ldr r5, [pc, #560] @ (8009a18 ) 80097e6: 0020 movs r0, r4 80097e8: 0029 movs r1, r5 80097ea: b005 add sp, #20 80097ec: bdf0 pop {r4, r5, r6, r7, pc} 80097ee: 4b8b ldr r3, [pc, #556] @ (8009a1c ) 80097f0: 429e cmp r6, r3 80097f2: d80f bhi.n 8009814 80097f4: 4b8a ldr r3, [pc, #552] @ (8009a20 ) 80097f6: 429e cmp r6, r3 80097f8: d809 bhi.n 800980e 80097fa: 4a8a ldr r2, [pc, #552] @ (8009a24 ) 80097fc: 4b8a ldr r3, [pc, #552] @ (8009a28 ) 80097fe: f7f7 fc23 bl 8001048 <__aeabi_dadd> 8009802: 2200 movs r2, #0 8009804: 4b89 ldr r3, [pc, #548] @ (8009a2c ) 8009806: f7f6 fd33 bl 8000270 <__aeabi_dcmpgt> 800980a: 2800 cmp r0, #0 800980c: d1eb bne.n 80097e6 800980e: 2301 movs r3, #1 8009810: 425b negs r3, r3 8009812: e025 b.n 8009860 8009814: f7ff fc52 bl 80090bc 8009818: 4b85 ldr r3, [pc, #532] @ (8009a30 ) 800981a: 0004 movs r4, r0 800981c: 000d movs r5, r1 800981e: 429e cmp r6, r3 8009820: d900 bls.n 8009824 8009822: e0aa b.n 800997a 8009824: 4b83 ldr r3, [pc, #524] @ (8009a34 ) 8009826: 429e cmp r6, r3 8009828: d900 bls.n 800982c 800982a: e090 b.n 800994e 800982c: 0002 movs r2, r0 800982e: 000b movs r3, r1 8009830: f7f7 fc0a bl 8001048 <__aeabi_dadd> 8009834: 2200 movs r2, #0 8009836: 4b7d ldr r3, [pc, #500] @ (8009a2c ) 8009838: f7f8 fe76 bl 8002528 <__aeabi_dsub> 800983c: 2380 movs r3, #128 @ 0x80 800983e: 0006 movs r6, r0 8009840: 000f movs r7, r1 8009842: 2200 movs r2, #0 8009844: 0020 movs r0, r4 8009846: 0029 movs r1, r5 8009848: 05db lsls r3, r3, #23 800984a: f7f7 fbfd bl 8001048 <__aeabi_dadd> 800984e: 000b movs r3, r1 8009850: 0002 movs r2, r0 8009852: 0039 movs r1, r7 8009854: 0030 movs r0, r6 8009856: f7f7 ff5b bl 8001710 <__aeabi_ddiv> 800985a: 2300 movs r3, #0 800985c: 0004 movs r4, r0 800985e: 000d movs r5, r1 8009860: 0022 movs r2, r4 8009862: 9302 str r3, [sp, #8] 8009864: 0020 movs r0, r4 8009866: 002b movs r3, r5 8009868: 0029 movs r1, r5 800986a: f7f8 fb95 bl 8001f98 <__aeabi_dmul> 800986e: 0002 movs r2, r0 8009870: 000b movs r3, r1 8009872: 9000 str r0, [sp, #0] 8009874: 9101 str r1, [sp, #4] 8009876: f7f8 fb8f bl 8001f98 <__aeabi_dmul> 800987a: 0006 movs r6, r0 800987c: 000f movs r7, r1 800987e: 4a6e ldr r2, [pc, #440] @ (8009a38 ) 8009880: 4b6e ldr r3, [pc, #440] @ (8009a3c ) 8009882: f7f8 fb89 bl 8001f98 <__aeabi_dmul> 8009886: 4a6e ldr r2, [pc, #440] @ (8009a40 ) 8009888: 4b6e ldr r3, [pc, #440] @ (8009a44 ) 800988a: f7f7 fbdd bl 8001048 <__aeabi_dadd> 800988e: 0032 movs r2, r6 8009890: 003b movs r3, r7 8009892: f7f8 fb81 bl 8001f98 <__aeabi_dmul> 8009896: 4a6c ldr r2, [pc, #432] @ (8009a48 ) 8009898: 4b6c ldr r3, [pc, #432] @ (8009a4c ) 800989a: f7f7 fbd5 bl 8001048 <__aeabi_dadd> 800989e: 0032 movs r2, r6 80098a0: 003b movs r3, r7 80098a2: f7f8 fb79 bl 8001f98 <__aeabi_dmul> 80098a6: 4a6a ldr r2, [pc, #424] @ (8009a50 ) 80098a8: 4b6a ldr r3, [pc, #424] @ (8009a54 ) 80098aa: f7f7 fbcd bl 8001048 <__aeabi_dadd> 80098ae: 0032 movs r2, r6 80098b0: 003b movs r3, r7 80098b2: f7f8 fb71 bl 8001f98 <__aeabi_dmul> 80098b6: 4a68 ldr r2, [pc, #416] @ (8009a58 ) 80098b8: 4b68 ldr r3, [pc, #416] @ (8009a5c ) 80098ba: f7f7 fbc5 bl 8001048 <__aeabi_dadd> 80098be: 0032 movs r2, r6 80098c0: 003b movs r3, r7 80098c2: f7f8 fb69 bl 8001f98 <__aeabi_dmul> 80098c6: 4a66 ldr r2, [pc, #408] @ (8009a60 ) 80098c8: 4b66 ldr r3, [pc, #408] @ (8009a64 ) 80098ca: f7f7 fbbd bl 8001048 <__aeabi_dadd> 80098ce: 9a00 ldr r2, [sp, #0] 80098d0: 9b01 ldr r3, [sp, #4] 80098d2: f7f8 fb61 bl 8001f98 <__aeabi_dmul> 80098d6: 4a64 ldr r2, [pc, #400] @ (8009a68 ) 80098d8: 9000 str r0, [sp, #0] 80098da: 9101 str r1, [sp, #4] 80098dc: 4b63 ldr r3, [pc, #396] @ (8009a6c ) 80098de: 0030 movs r0, r6 80098e0: 0039 movs r1, r7 80098e2: f7f8 fb59 bl 8001f98 <__aeabi_dmul> 80098e6: 4a62 ldr r2, [pc, #392] @ (8009a70 ) 80098e8: 4b62 ldr r3, [pc, #392] @ (8009a74 ) 80098ea: f7f8 fe1d bl 8002528 <__aeabi_dsub> 80098ee: 0032 movs r2, r6 80098f0: 003b movs r3, r7 80098f2: f7f8 fb51 bl 8001f98 <__aeabi_dmul> 80098f6: 4a60 ldr r2, [pc, #384] @ (8009a78 ) 80098f8: 4b60 ldr r3, [pc, #384] @ (8009a7c ) 80098fa: f7f8 fe15 bl 8002528 <__aeabi_dsub> 80098fe: 0032 movs r2, r6 8009900: 003b movs r3, r7 8009902: f7f8 fb49 bl 8001f98 <__aeabi_dmul> 8009906: 4a5e ldr r2, [pc, #376] @ (8009a80 ) 8009908: 4b5e ldr r3, [pc, #376] @ (8009a84 ) 800990a: f7f8 fe0d bl 8002528 <__aeabi_dsub> 800990e: 0032 movs r2, r6 8009910: 003b movs r3, r7 8009912: f7f8 fb41 bl 8001f98 <__aeabi_dmul> 8009916: 4a5c ldr r2, [pc, #368] @ (8009a88 ) 8009918: 4b5c ldr r3, [pc, #368] @ (8009a8c ) 800991a: f7f8 fe05 bl 8002528 <__aeabi_dsub> 800991e: 0032 movs r2, r6 8009920: 003b movs r3, r7 8009922: f7f8 fb39 bl 8001f98 <__aeabi_dmul> 8009926: 0002 movs r2, r0 8009928: 000b movs r3, r1 800992a: 9800 ldr r0, [sp, #0] 800992c: 9901 ldr r1, [sp, #4] 800992e: f7f7 fb8b bl 8001048 <__aeabi_dadd> 8009932: 002b movs r3, r5 8009934: 0022 movs r2, r4 8009936: f7f8 fb2f bl 8001f98 <__aeabi_dmul> 800993a: 9b02 ldr r3, [sp, #8] 800993c: 3301 adds r3, #1 800993e: d143 bne.n 80099c8 8009940: 0002 movs r2, r0 8009942: 000b movs r3, r1 8009944: 0020 movs r0, r4 8009946: 0029 movs r1, r5 8009948: f7f8 fdee bl 8002528 <__aeabi_dsub> 800994c: e742 b.n 80097d4 800994e: 2200 movs r2, #0 8009950: 4b36 ldr r3, [pc, #216] @ (8009a2c ) 8009952: f7f8 fde9 bl 8002528 <__aeabi_dsub> 8009956: 2200 movs r2, #0 8009958: 0006 movs r6, r0 800995a: 000f movs r7, r1 800995c: 0020 movs r0, r4 800995e: 0029 movs r1, r5 8009960: 4b32 ldr r3, [pc, #200] @ (8009a2c ) 8009962: f7f7 fb71 bl 8001048 <__aeabi_dadd> 8009966: 000b movs r3, r1 8009968: 0002 movs r2, r0 800996a: 0039 movs r1, r7 800996c: 0030 movs r0, r6 800996e: f7f7 fecf bl 8001710 <__aeabi_ddiv> 8009972: 2301 movs r3, #1 8009974: 0004 movs r4, r0 8009976: 000d movs r5, r1 8009978: e772 b.n 8009860 800997a: 4b45 ldr r3, [pc, #276] @ (8009a90 ) 800997c: 429e cmp r6, r3 800997e: d819 bhi.n 80099b4 8009980: 2200 movs r2, #0 8009982: 4b44 ldr r3, [pc, #272] @ (8009a94 ) 8009984: f7f8 fdd0 bl 8002528 <__aeabi_dsub> 8009988: 2200 movs r2, #0 800998a: 0006 movs r6, r0 800998c: 000f movs r7, r1 800998e: 0020 movs r0, r4 8009990: 0029 movs r1, r5 8009992: 4b40 ldr r3, [pc, #256] @ (8009a94 ) 8009994: f7f8 fb00 bl 8001f98 <__aeabi_dmul> 8009998: 2200 movs r2, #0 800999a: 4b24 ldr r3, [pc, #144] @ (8009a2c ) 800999c: f7f7 fb54 bl 8001048 <__aeabi_dadd> 80099a0: 000b movs r3, r1 80099a2: 0002 movs r2, r0 80099a4: 0039 movs r1, r7 80099a6: 0030 movs r0, r6 80099a8: f7f7 feb2 bl 8001710 <__aeabi_ddiv> 80099ac: 2302 movs r3, #2 80099ae: 0004 movs r4, r0 80099b0: 000d movs r5, r1 80099b2: e755 b.n 8009860 80099b4: 000b movs r3, r1 80099b6: 0002 movs r2, r0 80099b8: 4937 ldr r1, [pc, #220] @ (8009a98 ) 80099ba: 2000 movs r0, #0 80099bc: f7f7 fea8 bl 8001710 <__aeabi_ddiv> 80099c0: 2303 movs r3, #3 80099c2: 0004 movs r4, r0 80099c4: 000d movs r5, r1 80099c6: e74b b.n 8009860 80099c8: 9b02 ldr r3, [sp, #8] 80099ca: 4f34 ldr r7, [pc, #208] @ (8009a9c ) 80099cc: 00de lsls r6, r3, #3 80099ce: 4b34 ldr r3, [pc, #208] @ (8009aa0 ) 80099d0: 19bf adds r7, r7, r6 80099d2: 199e adds r6, r3, r6 80099d4: 6832 ldr r2, [r6, #0] 80099d6: 6873 ldr r3, [r6, #4] 80099d8: f7f8 fda6 bl 8002528 <__aeabi_dsub> 80099dc: 0022 movs r2, r4 80099de: 002b movs r3, r5 80099e0: f7f8 fda2 bl 8002528 <__aeabi_dsub> 80099e4: 000b movs r3, r1 80099e6: 0002 movs r2, r0 80099e8: 6838 ldr r0, [r7, #0] 80099ea: 6879 ldr r1, [r7, #4] 80099ec: f7f8 fd9c bl 8002528 <__aeabi_dsub> 80099f0: 9b03 ldr r3, [sp, #12] 80099f2: 0004 movs r4, r0 80099f4: 000d movs r5, r1 80099f6: 2b00 cmp r3, #0 80099f8: db00 blt.n 80099fc 80099fa: e6f4 b.n 80097e6 80099fc: 2180 movs r1, #128 @ 0x80 80099fe: 0609 lsls r1, r1, #24 8009a00: 186b adds r3, r5, r1 8009a02: 0004 movs r4, r0 8009a04: 001d movs r5, r3 8009a06: e6ee b.n 80097e6 8009a08: 4d26 ldr r5, [pc, #152] @ (8009aa4 ) 8009a0a: e6ec b.n 80097e6 8009a0c: 440fffff .word 0x440fffff 8009a10: 7ff00000 .word 0x7ff00000 8009a14: 54442d18 .word 0x54442d18 8009a18: 3ff921fb .word 0x3ff921fb 8009a1c: 3fdbffff .word 0x3fdbffff 8009a20: 3e1fffff .word 0x3e1fffff 8009a24: 8800759c .word 0x8800759c 8009a28: 7e37e43c .word 0x7e37e43c 8009a2c: 3ff00000 .word 0x3ff00000 8009a30: 3ff2ffff .word 0x3ff2ffff 8009a34: 3fe5ffff .word 0x3fe5ffff 8009a38: e322da11 .word 0xe322da11 8009a3c: 3f90ad3a .word 0x3f90ad3a 8009a40: 24760deb .word 0x24760deb 8009a44: 3fa97b4b .word 0x3fa97b4b 8009a48: a0d03d51 .word 0xa0d03d51 8009a4c: 3fb10d66 .word 0x3fb10d66 8009a50: c54c206e .word 0xc54c206e 8009a54: 3fb745cd .word 0x3fb745cd 8009a58: 920083ff .word 0x920083ff 8009a5c: 3fc24924 .word 0x3fc24924 8009a60: 5555550d .word 0x5555550d 8009a64: 3fd55555 .word 0x3fd55555 8009a68: 2c6a6c2f .word 0x2c6a6c2f 8009a6c: bfa2b444 .word 0xbfa2b444 8009a70: 52defd9a .word 0x52defd9a 8009a74: 3fadde2d .word 0x3fadde2d 8009a78: af749a6d .word 0xaf749a6d 8009a7c: 3fb3b0f2 .word 0x3fb3b0f2 8009a80: fe231671 .word 0xfe231671 8009a84: 3fbc71c6 .word 0x3fbc71c6 8009a88: 9998ebc4 .word 0x9998ebc4 8009a8c: 3fc99999 .word 0x3fc99999 8009a90: 40037fff .word 0x40037fff 8009a94: 3ff80000 .word 0x3ff80000 8009a98: bff00000 .word 0xbff00000 8009a9c: 08009f88 .word 0x08009f88 8009aa0: 08009f68 .word 0x08009f68 8009aa4: bff921fb .word 0xbff921fb 08009aa8 <__ieee754_atan2f>: 8009aa8: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} 8009aaa: 25ff movs r5, #255 @ 0xff 8009aac: 004a lsls r2, r1, #1 8009aae: 9101 str r1, [sp, #4] 8009ab0: 0852 lsrs r2, r2, #1 8009ab2: 05ed lsls r5, r5, #23 8009ab4: 42aa cmp r2, r5 8009ab6: d804 bhi.n 8009ac2 <__ieee754_atan2f+0x1a> 8009ab8: 0043 lsls r3, r0, #1 8009aba: 0007 movs r7, r0 8009abc: 085b lsrs r3, r3, #1 8009abe: 42ab cmp r3, r5 8009ac0: d902 bls.n 8009ac8 <__ieee754_atan2f+0x20> 8009ac2: f7f6 fc23 bl 800030c <__aeabi_fadd> 8009ac6: bdfe pop {r1, r2, r3, r4, r5, r6, r7, pc} 8009ac8: 24fe movs r4, #254 @ 0xfe 8009aca: 05a4 lsls r4, r4, #22 8009acc: 42a1 cmp r1, r4 8009ace: d102 bne.n 8009ad6 <__ieee754_atan2f+0x2e> 8009ad0: f000 f864 bl 8009b9c 8009ad4: e7f7 b.n 8009ac6 <__ieee754_atan2f+0x1e> 8009ad6: 2602 movs r6, #2 8009ad8: 178c asrs r4, r1, #30 8009ada: 4034 ands r4, r6 8009adc: 0fc6 lsrs r6, r0, #31 8009ade: 4334 orrs r4, r6 8009ae0: 2b00 cmp r3, #0 8009ae2: d105 bne.n 8009af0 <__ieee754_atan2f+0x48> 8009ae4: 2c02 cmp r4, #2 8009ae6: d045 beq.n 8009b74 <__ieee754_atan2f+0xcc> 8009ae8: 2c03 cmp r4, #3 8009aea: d1ec bne.n 8009ac6 <__ieee754_atan2f+0x1e> 8009aec: 4823 ldr r0, [pc, #140] @ (8009b7c <__ieee754_atan2f+0xd4>) 8009aee: e7ea b.n 8009ac6 <__ieee754_atan2f+0x1e> 8009af0: 2a00 cmp r2, #0 8009af2: d103 bne.n 8009afc <__ieee754_atan2f+0x54> 8009af4: 2f00 cmp r7, #0 8009af6: da3f bge.n 8009b78 <__ieee754_atan2f+0xd0> 8009af8: 4821 ldr r0, [pc, #132] @ (8009b80 <__ieee754_atan2f+0xd8>) 8009afa: e7e4 b.n 8009ac6 <__ieee754_atan2f+0x1e> 8009afc: 42aa cmp r2, r5 8009afe: d10e bne.n 8009b1e <__ieee754_atan2f+0x76> 8009b00: 3c01 subs r4, #1 8009b02: 4293 cmp r3, r2 8009b04: d104 bne.n 8009b10 <__ieee754_atan2f+0x68> 8009b06: 4b1f ldr r3, [pc, #124] @ (8009b84 <__ieee754_atan2f+0xdc>) 8009b08: 2c02 cmp r4, #2 8009b0a: d905 bls.n 8009b18 <__ieee754_atan2f+0x70> 8009b0c: 481e ldr r0, [pc, #120] @ (8009b88 <__ieee754_atan2f+0xe0>) 8009b0e: e7da b.n 8009ac6 <__ieee754_atan2f+0x1e> 8009b10: 2000 movs r0, #0 8009b12: 2c02 cmp r4, #2 8009b14: d8d7 bhi.n 8009ac6 <__ieee754_atan2f+0x1e> 8009b16: 4b1d ldr r3, [pc, #116] @ (8009b8c <__ieee754_atan2f+0xe4>) 8009b18: 00a4 lsls r4, r4, #2 8009b1a: 58e0 ldr r0, [r4, r3] 8009b1c: e7d3 b.n 8009ac6 <__ieee754_atan2f+0x1e> 8009b1e: 42ab cmp r3, r5 8009b20: d0e8 beq.n 8009af4 <__ieee754_atan2f+0x4c> 8009b22: 1a9b subs r3, r3, r2 8009b24: 15db asrs r3, r3, #23 8009b26: 2b3c cmp r3, #60 @ 0x3c 8009b28: dc14 bgt.n 8009b54 <__ieee754_atan2f+0xac> 8009b2a: 2900 cmp r1, #0 8009b2c: da01 bge.n 8009b32 <__ieee754_atan2f+0x8a> 8009b2e: 333c adds r3, #60 @ 0x3c 8009b30: db12 blt.n 8009b58 <__ieee754_atan2f+0xb0> 8009b32: f7f6 fd75 bl 8000620 <__aeabi_fdiv> 8009b36: f000 f941 bl 8009dbc 8009b3a: f000 f82f bl 8009b9c 8009b3e: 2c01 cmp r4, #1 8009b40: d00c beq.n 8009b5c <__ieee754_atan2f+0xb4> 8009b42: 2c02 cmp r4, #2 8009b44: d00e beq.n 8009b64 <__ieee754_atan2f+0xbc> 8009b46: 2c00 cmp r4, #0 8009b48: d0bd beq.n 8009ac6 <__ieee754_atan2f+0x1e> 8009b4a: 4911 ldr r1, [pc, #68] @ (8009b90 <__ieee754_atan2f+0xe8>) 8009b4c: f7f6 fbde bl 800030c <__aeabi_fadd> 8009b50: 4910 ldr r1, [pc, #64] @ (8009b94 <__ieee754_atan2f+0xec>) 8009b52: e00c b.n 8009b6e <__ieee754_atan2f+0xc6> 8009b54: 4810 ldr r0, [pc, #64] @ (8009b98 <__ieee754_atan2f+0xf0>) 8009b56: e7f2 b.n 8009b3e <__ieee754_atan2f+0x96> 8009b58: 2000 movs r0, #0 8009b5a: e7f0 b.n 8009b3e <__ieee754_atan2f+0x96> 8009b5c: 2380 movs r3, #128 @ 0x80 8009b5e: 061b lsls r3, r3, #24 8009b60: 18c0 adds r0, r0, r3 8009b62: e7b0 b.n 8009ac6 <__ieee754_atan2f+0x1e> 8009b64: 490a ldr r1, [pc, #40] @ (8009b90 <__ieee754_atan2f+0xe8>) 8009b66: f7f6 fbd1 bl 800030c <__aeabi_fadd> 8009b6a: 1c01 adds r1, r0, #0 8009b6c: 4809 ldr r0, [pc, #36] @ (8009b94 <__ieee754_atan2f+0xec>) 8009b6e: f7f7 f87b bl 8000c68 <__aeabi_fsub> 8009b72: e7a8 b.n 8009ac6 <__ieee754_atan2f+0x1e> 8009b74: 4807 ldr r0, [pc, #28] @ (8009b94 <__ieee754_atan2f+0xec>) 8009b76: e7a6 b.n 8009ac6 <__ieee754_atan2f+0x1e> 8009b78: 4807 ldr r0, [pc, #28] @ (8009b98 <__ieee754_atan2f+0xf0>) 8009b7a: e7a4 b.n 8009ac6 <__ieee754_atan2f+0x1e> 8009b7c: c0490fdb .word 0xc0490fdb 8009b80: bfc90fdb .word 0xbfc90fdb 8009b84: 08009fb4 .word 0x08009fb4 8009b88: 3f490fdb .word 0x3f490fdb 8009b8c: 08009fa8 .word 0x08009fa8 8009b90: 33bbbd2e .word 0x33bbbd2e 8009b94: 40490fdb .word 0x40490fdb 8009b98: 3fc90fdb .word 0x3fc90fdb 08009b9c : 8009b9c: 23a1 movs r3, #161 @ 0xa1 8009b9e: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} 8009ba0: 0045 lsls r5, r0, #1 8009ba2: 1c04 adds r4, r0, #0 8009ba4: 9001 str r0, [sp, #4] 8009ba6: 086d lsrs r5, r5, #1 8009ba8: 05db lsls r3, r3, #23 8009baa: 429d cmp r5, r3 8009bac: d30f bcc.n 8009bce 8009bae: 23ff movs r3, #255 @ 0xff 8009bb0: 05db lsls r3, r3, #23 8009bb2: 429d cmp r5, r3 8009bb4: d904 bls.n 8009bc0 8009bb6: 1c01 adds r1, r0, #0 8009bb8: f7f6 fba8 bl 800030c <__aeabi_fadd> 8009bbc: 1c04 adds r4, r0, #0 8009bbe: e004 b.n 8009bca 8009bc0: 9b01 ldr r3, [sp, #4] 8009bc2: 2b00 cmp r3, #0 8009bc4: dc00 bgt.n 8009bc8 8009bc6: e0cc b.n 8009d62 8009bc8: 4c67 ldr r4, [pc, #412] @ (8009d68 ) 8009bca: 1c20 adds r0, r4, #0 8009bcc: bdfe pop {r1, r2, r3, r4, r5, r6, r7, pc} 8009bce: 4b67 ldr r3, [pc, #412] @ (8009d6c ) 8009bd0: 429d cmp r5, r3 8009bd2: d80f bhi.n 8009bf4 8009bd4: 23c4 movs r3, #196 @ 0xc4 8009bd6: 059b lsls r3, r3, #22 8009bd8: 429d cmp r5, r3 8009bda: d208 bcs.n 8009bee 8009bdc: 4964 ldr r1, [pc, #400] @ (8009d70 ) 8009bde: f7f6 fb95 bl 800030c <__aeabi_fadd> 8009be2: 21fe movs r1, #254 @ 0xfe 8009be4: 0589 lsls r1, r1, #22 8009be6: f7f6 fb7d bl 80002e4 <__aeabi_fcmpgt> 8009bea: 2800 cmp r0, #0 8009bec: d1ed bne.n 8009bca 8009bee: 2601 movs r6, #1 8009bf0: 4276 negs r6, r6 8009bf2: e01b b.n 8009c2c 8009bf4: f000 f8e2 bl 8009dbc 8009bf8: 4b5e ldr r3, [pc, #376] @ (8009d74 ) 8009bfa: 1c04 adds r4, r0, #0 8009bfc: 429d cmp r5, r3 8009bfe: d87b bhi.n 8009cf8 8009c00: 4b5d ldr r3, [pc, #372] @ (8009d78 ) 8009c02: 429d cmp r5, r3 8009c04: d867 bhi.n 8009cd6 8009c06: 1c01 adds r1, r0, #0 8009c08: f7f6 fb80 bl 800030c <__aeabi_fadd> 8009c0c: 21fe movs r1, #254 @ 0xfe 8009c0e: 0589 lsls r1, r1, #22 8009c10: f7f7 f82a bl 8000c68 <__aeabi_fsub> 8009c14: 2180 movs r1, #128 @ 0x80 8009c16: 1c05 adds r5, r0, #0 8009c18: 05c9 lsls r1, r1, #23 8009c1a: 1c20 adds r0, r4, #0 8009c1c: f7f6 fb76 bl 800030c <__aeabi_fadd> 8009c20: 1c01 adds r1, r0, #0 8009c22: 1c28 adds r0, r5, #0 8009c24: f7f6 fcfc bl 8000620 <__aeabi_fdiv> 8009c28: 2600 movs r6, #0 8009c2a: 1c04 adds r4, r0, #0 8009c2c: 1c21 adds r1, r4, #0 8009c2e: 1c20 adds r0, r4, #0 8009c30: f7f6 fedc bl 80009ec <__aeabi_fmul> 8009c34: 1c01 adds r1, r0, #0 8009c36: 1c07 adds r7, r0, #0 8009c38: f7f6 fed8 bl 80009ec <__aeabi_fmul> 8009c3c: 494f ldr r1, [pc, #316] @ (8009d7c ) 8009c3e: 1c05 adds r5, r0, #0 8009c40: f7f6 fed4 bl 80009ec <__aeabi_fmul> 8009c44: 494e ldr r1, [pc, #312] @ (8009d80 ) 8009c46: f7f6 fb61 bl 800030c <__aeabi_fadd> 8009c4a: 1c29 adds r1, r5, #0 8009c4c: f7f6 fece bl 80009ec <__aeabi_fmul> 8009c50: 494c ldr r1, [pc, #304] @ (8009d84 ) 8009c52: f7f6 fb5b bl 800030c <__aeabi_fadd> 8009c56: 1c29 adds r1, r5, #0 8009c58: f7f6 fec8 bl 80009ec <__aeabi_fmul> 8009c5c: 494a ldr r1, [pc, #296] @ (8009d88 ) 8009c5e: f7f6 fb55 bl 800030c <__aeabi_fadd> 8009c62: 1c29 adds r1, r5, #0 8009c64: f7f6 fec2 bl 80009ec <__aeabi_fmul> 8009c68: 4948 ldr r1, [pc, #288] @ (8009d8c ) 8009c6a: f7f6 fb4f bl 800030c <__aeabi_fadd> 8009c6e: 1c29 adds r1, r5, #0 8009c70: f7f6 febc bl 80009ec <__aeabi_fmul> 8009c74: 4946 ldr r1, [pc, #280] @ (8009d90 ) 8009c76: f7f6 fb49 bl 800030c <__aeabi_fadd> 8009c7a: 1c39 adds r1, r7, #0 8009c7c: f7f6 feb6 bl 80009ec <__aeabi_fmul> 8009c80: 4944 ldr r1, [pc, #272] @ (8009d94 ) 8009c82: 1c07 adds r7, r0, #0 8009c84: 1c28 adds r0, r5, #0 8009c86: f7f6 feb1 bl 80009ec <__aeabi_fmul> 8009c8a: 4943 ldr r1, [pc, #268] @ (8009d98 ) 8009c8c: f7f6 ffec bl 8000c68 <__aeabi_fsub> 8009c90: 1c29 adds r1, r5, #0 8009c92: f7f6 feab bl 80009ec <__aeabi_fmul> 8009c96: 4941 ldr r1, [pc, #260] @ (8009d9c ) 8009c98: f7f6 ffe6 bl 8000c68 <__aeabi_fsub> 8009c9c: 1c29 adds r1, r5, #0 8009c9e: f7f6 fea5 bl 80009ec <__aeabi_fmul> 8009ca2: 493f ldr r1, [pc, #252] @ (8009da0 ) 8009ca4: f7f6 ffe0 bl 8000c68 <__aeabi_fsub> 8009ca8: 1c29 adds r1, r5, #0 8009caa: f7f6 fe9f bl 80009ec <__aeabi_fmul> 8009cae: 493d ldr r1, [pc, #244] @ (8009da4 ) 8009cb0: f7f6 ffda bl 8000c68 <__aeabi_fsub> 8009cb4: 1c29 adds r1, r5, #0 8009cb6: f7f6 fe99 bl 80009ec <__aeabi_fmul> 8009cba: 1c01 adds r1, r0, #0 8009cbc: 1c38 adds r0, r7, #0 8009cbe: f7f6 fb25 bl 800030c <__aeabi_fadd> 8009cc2: 1c21 adds r1, r4, #0 8009cc4: f7f6 fe92 bl 80009ec <__aeabi_fmul> 8009cc8: 1c73 adds r3, r6, #1 8009cca: d134 bne.n 8009d36 8009ccc: 1c01 adds r1, r0, #0 8009cce: 1c20 adds r0, r4, #0 8009cd0: f7f6 ffca bl 8000c68 <__aeabi_fsub> 8009cd4: e772 b.n 8009bbc 8009cd6: 21fe movs r1, #254 @ 0xfe 8009cd8: 0589 lsls r1, r1, #22 8009cda: f7f6 ffc5 bl 8000c68 <__aeabi_fsub> 8009cde: 21fe movs r1, #254 @ 0xfe 8009ce0: 1c05 adds r5, r0, #0 8009ce2: 0589 lsls r1, r1, #22 8009ce4: 1c20 adds r0, r4, #0 8009ce6: f7f6 fb11 bl 800030c <__aeabi_fadd> 8009cea: 1c01 adds r1, r0, #0 8009cec: 1c28 adds r0, r5, #0 8009cee: f7f6 fc97 bl 8000620 <__aeabi_fdiv> 8009cf2: 2601 movs r6, #1 8009cf4: 1c04 adds r4, r0, #0 8009cf6: e799 b.n 8009c2c 8009cf8: 4b2b ldr r3, [pc, #172] @ (8009da8 ) 8009cfa: 429d cmp r5, r3 8009cfc: d814 bhi.n 8009d28 8009cfe: 21ff movs r1, #255 @ 0xff 8009d00: 0589 lsls r1, r1, #22 8009d02: f7f6 ffb1 bl 8000c68 <__aeabi_fsub> 8009d06: 21ff movs r1, #255 @ 0xff 8009d08: 1c05 adds r5, r0, #0 8009d0a: 0589 lsls r1, r1, #22 8009d0c: 1c20 adds r0, r4, #0 8009d0e: f7f6 fe6d bl 80009ec <__aeabi_fmul> 8009d12: 21fe movs r1, #254 @ 0xfe 8009d14: 0589 lsls r1, r1, #22 8009d16: f7f6 faf9 bl 800030c <__aeabi_fadd> 8009d1a: 1c01 adds r1, r0, #0 8009d1c: 1c28 adds r0, r5, #0 8009d1e: f7f6 fc7f bl 8000620 <__aeabi_fdiv> 8009d22: 2602 movs r6, #2 8009d24: 1c04 adds r4, r0, #0 8009d26: e781 b.n 8009c2c 8009d28: 1c01 adds r1, r0, #0 8009d2a: 4820 ldr r0, [pc, #128] @ (8009dac ) 8009d2c: f7f6 fc78 bl 8000620 <__aeabi_fdiv> 8009d30: 2603 movs r6, #3 8009d32: 1c04 adds r4, r0, #0 8009d34: e77a b.n 8009c2c 8009d36: 4b1e ldr r3, [pc, #120] @ (8009db0 ) 8009d38: 00b6 lsls r6, r6, #2 8009d3a: 58f1 ldr r1, [r6, r3] 8009d3c: f7f6 ff94 bl 8000c68 <__aeabi_fsub> 8009d40: 1c21 adds r1, r4, #0 8009d42: f7f6 ff91 bl 8000c68 <__aeabi_fsub> 8009d46: 4d1b ldr r5, [pc, #108] @ (8009db4 ) 8009d48: 1c01 adds r1, r0, #0 8009d4a: 5970 ldr r0, [r6, r5] 8009d4c: f7f6 ff8c bl 8000c68 <__aeabi_fsub> 8009d50: 9b01 ldr r3, [sp, #4] 8009d52: 1c04 adds r4, r0, #0 8009d54: 2b00 cmp r3, #0 8009d56: db00 blt.n 8009d5a 8009d58: e737 b.n 8009bca 8009d5a: 2380 movs r3, #128 @ 0x80 8009d5c: 061b lsls r3, r3, #24 8009d5e: 18c4 adds r4, r0, r3 8009d60: e733 b.n 8009bca 8009d62: 4c15 ldr r4, [pc, #84] @ (8009db8 ) 8009d64: e731 b.n 8009bca 8009d66: 46c0 nop @ (mov r8, r8) 8009d68: 3fc90fdb .word 0x3fc90fdb 8009d6c: 3edfffff .word 0x3edfffff 8009d70: 7149f2ca .word 0x7149f2ca 8009d74: 3f97ffff .word 0x3f97ffff 8009d78: 3f2fffff .word 0x3f2fffff 8009d7c: 3c8569d7 .word 0x3c8569d7 8009d80: 3d4bda59 .word 0x3d4bda59 8009d84: 3d886b35 .word 0x3d886b35 8009d88: 3dba2e6e .word 0x3dba2e6e 8009d8c: 3e124925 .word 0x3e124925 8009d90: 3eaaaaab .word 0x3eaaaaab 8009d94: bd15a221 .word 0xbd15a221 8009d98: 3d6ef16b .word 0x3d6ef16b 8009d9c: 3d9d8795 .word 0x3d9d8795 8009da0: 3de38e38 .word 0x3de38e38 8009da4: 3e4ccccd .word 0x3e4ccccd 8009da8: 401bffff .word 0x401bffff 8009dac: bf800000 .word 0xbf800000 8009db0: 08009fc0 .word 0x08009fc0 8009db4: 08009fd0 .word 0x08009fd0 8009db8: bfc90fdb .word 0xbfc90fdb 08009dbc : 8009dbc: 0040 lsls r0, r0, #1 8009dbe: 0840 lsrs r0, r0, #1 8009dc0: 4770 bx lr ... 08009dc4 <_init>: 8009dc4: b5f8 push {r3, r4, r5, r6, r7, lr} 8009dc6: 46c0 nop @ (mov r8, r8) 8009dc8: bcf8 pop {r3, r4, r5, r6, r7} 8009dca: bc08 pop {r3} 8009dcc: 469e mov lr, r3 8009dce: 4770 bx lr 08009dd0 <_fini>: 8009dd0: b5f8 push {r3, r4, r5, r6, r7, lr} 8009dd2: 46c0 nop @ (mov r8, r8) 8009dd4: bcf8 pop {r3, r4, r5, r6, r7} 8009dd6: bc08 pop {r3} 8009dd8: 469e mov lr, r3 8009dda: 4770 bx lr