92 lines
2.5 KiB
Plaintext
92 lines
2.5 KiB
Plaintext
#define iHN 9
|
|
#define iHZ 8
|
|
#define iVL 10
|
|
#define LOW_U_THR 100
|
|
|
|
static bool sequenceComplete, thresholdCrossed;
|
|
uint32_t HZ, HN, VL;
|
|
|
|
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_SWM);
|
|
Chip_SWM_EnableFixedPin(SWM_FIXED_ADC8);
|
|
Chip_SWM_EnableFixedPin(SWM_FIXED_ADC9);
|
|
Chip_SWM_EnableFixedPin(SWM_FIXED_ADC10);
|
|
Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_SWM);
|
|
|
|
/*disable adc pullups on pins 13,17,18*/
|
|
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_IOCON);
|
|
LPC_IOCON->PIO0[IOCON_PIO17] = 0;
|
|
LPC_IOCON->PIO0[IOCON_PIO18] = 0;
|
|
LPC_IOCON->PIO0[IOCON_PIO13] = 0;
|
|
|
|
static void ADC_Init(void){
|
|
Chip_ADC_Init(LPC_ADC, 0);
|
|
Chip_ADC_StartCalibration(LPC_ADC);
|
|
while (!(Chip_ADC_IsCalibrationDone(LPC_ADC))) {}
|
|
Chip_ADC_SetClockRate(LPC_ADC, 1000);//ADC_MAX_SAMPLE_RATE
|
|
|
|
Chip_ADC_SetupSequencer(LPC_ADC, ADC_SEQA_IDX,
|
|
(ADC_SEQ_CTRL_CHANSEL(iHZ) |
|
|
ADC_SEQ_CTRL_CHANSEL(iHN) |
|
|
ADC_SEQ_CTRL_CHANSEL(iVL) |
|
|
ADC_SEQ_CTRL_MODE_EOS));
|
|
/* Setup threshold 0 low and high values to about 25% and 75% of max */
|
|
Chip_ADC_SetThrLowValue(LPC_ADC, 0, ((1 * 0xFFF) / 4));
|
|
Chip_ADC_SetThrHighValue(LPC_ADC, 0, ((4 * 0xFFF) / 4));
|
|
|
|
Chip_ADC_ClearFlags(LPC_ADC, Chip_ADC_GetFlags(LPC_ADC));/* Clear all pending interrupts */
|
|
Chip_ADC_EnableInt(LPC_ADC, (ADC_INTEN_SEQA_ENABLE | ADC_INTEN_OVRRUN_ENABLE));/* Enable ADC overrun and sequence A completion interrupts */
|
|
|
|
/* Enable ADC NVIC interrupt */
|
|
NVIC_EnableIRQ(ADC_SEQA_IRQn);
|
|
|
|
/* Enable sequencer */
|
|
Chip_ADC_EnableSequencer(LPC_ADC, ADC_SEQA_IDX);
|
|
}
|
|
|
|
void ADC_SEQA_IRQHandler(void)
|
|
{
|
|
uint32_t pending;
|
|
|
|
/* Get pending interrupts */
|
|
pending = Chip_ADC_GetFlags(LPC_ADC);
|
|
|
|
/* Sequence A completion interrupt */
|
|
if (pending & ADC_FLAGS_SEQA_INT_MASK) {
|
|
sequenceComplete = true;
|
|
}
|
|
|
|
/* Threshold crossing interrupt on ADC input channel */
|
|
if (pending & ADC_FLAGS_THCMP_MASK(iHN) & ADC_FLAGS_THCMP_MASK(iHZ) & ADC_FLAGS_THCMP_MASK(iVL)) {
|
|
thresholdCrossed = true;
|
|
}
|
|
|
|
/* Clear any pending interrupts */
|
|
Chip_ADC_ClearFlags(LPC_ADC, pending);
|
|
}
|
|
|
|
void SysTick_Handler(void)
|
|
{
|
|
static uint32_t count;
|
|
|
|
/* Every 1/2 second */
|
|
if (count++ == 100 / 2) {
|
|
count = 0;
|
|
|
|
/* Manual start for ADC conversion sequence A */
|
|
Chip_ADC_StartSequencer(LPC_ADC, ADC_SEQA_IDX);
|
|
}
|
|
}
|
|
|
|
int main(void) {
|
|
SystemCoreClockUpdate();
|
|
ADC_Init();
|
|
SysTick_Config(SystemCoreClock / 100);
|
|
|
|
if (sequenceComplete) {
|
|
sequenceComplete = false;
|
|
|
|
HZ = ADC_DR_RESULT(LPC_ADC->DR[iHZ]);
|
|
HN = ADC_DR_RESULT(LPC_ADC->DR[iHN]);
|
|
VL = ADC_DR_RESULT(LPC_ADC->DR[iVL]);
|
|
}
|
|
} |